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* gcc: (gcc).                  The GNU Compiler Collection.
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   This file documents the use of the GNU compilers.

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File: gcc.info,  Node: i386 and x86-64 Options,  Next: HPPA Options,  Prev: MIPS Options,  Up: Submodel Options

Intel 386 and AMD x86-64 Options
--------------------------------

   These `-m' options are defined for the i386 and x86-64 family of
computers:

`-mtune=CPU-TYPE'
     Tune to CPU-TYPE everything applicable about the generated code,
     except for the ABI and the set of available instructions.  The
     choices for CPU-TYPE are `i386', `i486', `i586', `i686',
     `pentium', `pentium-mmx', `pentiumpro', `pentium2', `pentium3',
     `pentium4', `k6', `k6-2', `k6-3', `athlon', `athlon-tbird',
     `athlon-4', `athlon-xp', `athlon-mp', `winchip-c6', `winchip2',
     `k8', `c3' and `c3-2'.

     While picking a specific CPU-TYPE will schedule things
     appropriately for that particular chip, the compiler will not
     generate any code that does not run on the i386 without the
     `-march=CPU-TYPE' option being used.  `i586' is equivalent to
     `pentium' and `i686' is equivalent to `pentiumpro'.  `k6' and
     `athlon' are the AMD chips as opposed to the Intel ones.

`-march=CPU-TYPE'
     Generate instructions for the machine type CPU-TYPE.  The choices
     for CPU-TYPE are the same as for `-mtune'.  Moreover, specifying
     `-march=CPU-TYPE' implies `-mtune=CPU-TYPE'.

`-mcpu=CPU-TYPE'
     A deprecated synonym for `-mtune'.

`-m386'
`-m486'
`-mpentium'
`-mpentiumpro'
     These options are synonyms for `-mtune=i386', `-mtune=i486',
     `-mtune=pentium', and `-mtune=pentiumpro' respectively.  These
     synonyms are deprecated.

`-mfpmath=UNIT'
     generate floating point arithmetics for selected unit UNIT.  the
     choices for UNIT are:

    `387'
          Use the standard 387 floating point coprocessor present
          majority of chips and emulated otherwise.  Code compiled with
          this option will run almost everywhere.  The temporary
          results are computed in 80bit precision instead of precision
          specified by the type resulting in slightly different results
          compared to most of other chips. See `-ffloat-store' for more
          detailed description.

          This is the default choice for i386 compiler.

    `sse'
          Use scalar floating point instructions present in the SSE
          instruction set.  This instruction set is supported by
          Pentium3 and newer chips, in the AMD line by Athlon-4,
          Athlon-xp and Athlon-mp chips.  The earlier version of SSE
          instruction set supports only single precision arithmetics,
          thus the double and extended precision arithmetics is still
          done using 387.  Later version, present only in Pentium4 and
          the future AMD x86-64 chips supports double precision
          arithmetics too.

          For i387 you need to use `-march=CPU-TYPE', `-msse' or
          `-msse2' switches to enable SSE extensions and make this
          option effective.  For x86-64 compiler, these extensions are
          enabled by default.

          The resulting code should be considerably faster in majority
          of cases and avoid the numerical instability problems of 387
          code, but may break some existing code that expects
          temporaries to be 80bit.

          This is the default choice for x86-64 compiler.

    `pni'
          Use all SSE extensions enabled by `-msse2' as well as the new
          SSE extensions in Prescott New Instructions. `-mpni' also
          enables 2 builtin functions, `__builtin_ia32_monitor' and
          `__builtin_ia32_mwait', for new instructions `monitor' and
          `mwait'.

    `sse,387'
          Attempt to utilize both instruction sets at once.  This
          effectively double the amount of available registers and on
          chips with separate execution units for 387 and SSE the
          execution resources too.  Use this option with care, as it is
          still experimental, because gcc register allocator does not
          model separate functional units well resulting in instable
          performance.

`-masm=DIALECT'
     Output asm instructions using selected DIALECT. Supported choices
     are `intel' or `att' (the default one).

`-mieee-fp'
`-mno-ieee-fp'
     Control whether or not the compiler uses IEEE floating point
     comparisons.  These handle correctly the case where the result of a
     comparison is unordered.

`-msoft-float'
     Generate output containing library calls for floating point.
     *Warning:* the requisite libraries are not part of GCC.  Normally
     the facilities of the machine's usual C compiler are used, but
     this can't be done directly in cross-compilation.  You must make
     your own arrangements to provide suitable library functions for
     cross-compilation.

     On machines where a function returns floating point results in the
     80387 register stack, some floating point opcodes may be emitted
     even if `-msoft-float' is used.

`-mno-fp-ret-in-387'
     Do not use the FPU registers for return values of functions.

     The usual calling convention has functions return values of types
     `float' and `double' in an FPU register, even if there is no FPU.
     The idea is that the operating system should emulate an FPU.

     The option `-mno-fp-ret-in-387' causes such values to be returned
     in ordinary CPU registers instead.

`-mno-fancy-math-387'
     Some 387 emulators do not support the `sin', `cos' and `sqrt'
     instructions for the 387.  Specify this option to avoid generating
     those instructions.  This option is the default on FreeBSD,
     OpenBSD and NetBSD.  This option is overridden when `-march'
     indicates that the target cpu will always have an FPU and so the
     instruction will not need emulation.  As of revision 2.6.1, these
     instructions are not generated unless you also use the
     `-funsafe-math-optimizations' switch.

`-malign-double'
`-mno-align-double'
     Control whether GCC aligns `double', `long double', and `long
     long' variables on a two word boundary or a one word boundary.
     Aligning `double' variables on a two word boundary will produce
     code that runs somewhat faster on a `Pentium' at the expense of
     more memory.

     *Warning:* if you use the `-malign-double' switch, structures
     containing the above types will be aligned differently than the
     published application binary interface specifications for the 386
     and will not be binary compatible with structures in code compiled
     without that switch.

`-m96bit-long-double'

`-m128bit-long-double'
     These switches control the size of `long double' type. The i386
     application binary interface specifies the size to be 96 bits, so
     `-m96bit-long-double' is the default in 32 bit mode.

     Modern architectures (Pentium and newer) would prefer `long double'
     to be aligned to an 8 or 16 byte boundary.  In arrays or structures
     conforming to the ABI, this would not be possible.  So specifying a
     `-m128bit-long-double' will align `long double' to a 16 byte
     boundary by padding the `long double' with an additional 32 bit
     zero.

     In the x86-64 compiler, `-m128bit-long-double' is the default
     choice as its ABI specifies that `long double' is to be aligned on
     16 byte boundary.

     Notice that neither of these options enable any extra precision
     over the x87 standard of 80 bits for a `long double'.

     *Warning:* if you override the default value for your target ABI,
     the structures and arrays containing `long double' will change
     their size as well as function calling convention for function
     taking `long double' will be modified.  Hence they will not be
     binary compatible with arrays or structures in code compiled
     without that switch.

`-msvr3-shlib'
`-mno-svr3-shlib'
     Control whether GCC places uninitialized local variables into the
     `bss' or `data' segments.  `-msvr3-shlib' places them into `bss'.
     These options are meaningful only on System V Release 3.

`-mrtd'
     Use a different function-calling convention, in which functions
     that take a fixed number of arguments return with the `ret' NUM
     instruction, which pops their arguments while returning.  This
     saves one instruction in the caller since there is no need to pop
     the arguments there.

     You can specify that an individual function is called with this
     calling sequence with the function attribute `stdcall'.  You can
     also override the `-mrtd' option by using the function attribute
     `cdecl'.  *Note Function Attributes::.

     *Warning:* this calling convention is incompatible with the one
     normally used on Unix, so you cannot use it if you need to call
     libraries compiled with the Unix compiler.

     Also, you must provide function prototypes for all functions that
     take variable numbers of arguments (including `printf'); otherwise
     incorrect code will be generated for calls to those functions.

     In addition, seriously incorrect code will result if you call a
     function with too many arguments.  (Normally, extra arguments are
     harmlessly ignored.)

`-mregparm=NUM'
     Control how many registers are used to pass integer arguments.  By
     default, no registers are used to pass arguments, and at most 3
     registers can be used.  You can control this behavior for a
     specific function by using the function attribute `regparm'.
     *Note Function Attributes::.

     *Warning:* if you use this switch, and NUM is nonzero, then you
     must build all modules with the same value, including any
     libraries.  This includes the system libraries and startup modules.

`-mpreferred-stack-boundary=NUM'
     Attempt to keep the stack boundary aligned to a 2 raised to NUM
     byte boundary.  If `-mpreferred-stack-boundary' is not specified,
     the default is 4 (16 bytes or 128 bits), except when optimizing
     for code size (`-Os'), in which case the default is the minimum
     correct alignment (4 bytes for x86, and 8 bytes for x86-64).

     On Pentium and PentiumPro, `double' and `long double' values
     should be aligned to an 8 byte boundary (see `-malign-double') or
     suffer significant run time performance penalties.  On Pentium
     III, the Streaming SIMD Extension (SSE) data type `__m128' suffers
     similar penalties if it is not 16 byte aligned.

     To ensure proper alignment of this values on the stack, the stack
     boundary must be as aligned as that required by any value stored
     on the stack.  Further, every function must be generated such that
     it keeps the stack aligned.  Thus calling a function compiled with
     a higher preferred stack boundary from a function compiled with a
     lower preferred stack boundary will most likely misalign the
     stack.  It is recommended that libraries that use callbacks always
     use the default setting.

     This extra alignment does consume extra stack space, and generally
     increases code size.  Code that is sensitive to stack space usage,
     such as embedded systems and operating system kernels, may want to
     reduce the preferred alignment to `-mpreferred-stack-boundary=2'.

`-mmmx'
`-mno-mmx'

`-msse'
`-mno-sse'

`-msse2'
`-mno-sse2'

`-mpni'
`-mno-pni'

`-m3dnow'
`-mno-3dnow'
     These switches enable or disable the use of built-in functions
     that allow direct access to the MMX, SSE and 3Dnow extensions of
     the instruction set.

     *Note X86 Built-in Functions::, for details of the functions
     enabled and disabled by these switches.

     To have SSE/SSE2 instructions generated automatically from
     floating-point code, see `-mfpmath=sse'.

`-mpush-args'
`-mno-push-args'
     Use PUSH operations to store outgoing parameters.  This method is
     shorter and usually equally fast as method using SUB/MOV
     operations and is enabled by default.  In some cases disabling it
     may improve performance because of improved scheduling and reduced
     dependencies.

`-maccumulate-outgoing-args'
     If enabled, the maximum amount of space required for outgoing
     arguments will be computed in the function prologue.  This is
     faster on most modern CPUs because of reduced dependencies,
     improved scheduling and reduced stack usage when preferred stack
     boundary is not equal to 2.  The drawback is a notable increase in
     code size.  This switch implies `-mno-push-args'.

`-mthreads'
     Support thread-safe exception handling on `Mingw32'.  Code that
     relies on thread-safe exception handling must compile and link all
     code with the `-mthreads' option.  When compiling, `-mthreads'
     defines `-D_MT'; when linking, it links in a special thread helper
     library `-lmingwthrd' which cleans up per thread exception
     handling data.

`-mno-align-stringops'
     Do not align destination of inlined string operations.  This
     switch reduces code size and improves performance in case the
     destination is already aligned, but gcc don't know about it.

`-minline-all-stringops'
     By default GCC inlines string operations only when destination is
     known to be aligned at least to 4 byte boundary.  This enables
     more inlining, increase code size, but may improve performance of
     code that depends on fast memcpy, strlen and memset for short
     lengths.

`-momit-leaf-frame-pointer'
     Don't keep the frame pointer in a register for leaf functions.
     This avoids the instructions to save, set up and restore frame
     pointers and makes an extra register available in leaf functions.
     The option `-fomit-frame-pointer' removes the frame pointer for
     all functions which might make debugging harder.

`-mtls-direct-seg-refs'
`-mno-tls-direct-seg-refs'
     Controls whether TLS variables may be accessed with offsets from
     the TLS segment register (`%gs' for 32-bit, `%fs' for 64-bit), or
     whether the thread base pointer must be added.  Whether or not this
     is legal depends on the operating system, and whether it maps the
     segment to cover the entire TLS area.

     For systems that use GNU libc, the default is on.

   These `-m' switches are supported in addition to the above on AMD
x86-64 processors in 64-bit environments.

`-m32'
`-m64'
     Generate code for a 32-bit or 64-bit environment.  The 32-bit
     environment sets int, long and pointer to 32 bits and generates
     code that runs on any i386 system.  The 64-bit environment sets
     int to 32 bits and long and pointer to 64 bits and generates code
     for AMD's x86-64 architecture.

`-mno-red-zone'
     Do not use a so called red zone for x86-64 code.  The red zone is
     mandated by the x86-64 ABI, it is a 128-byte area beyond the
     location of the stack pointer that will not be modified by signal
     or interrupt handlers and therefore can be used for temporary data
     without adjusting the stack pointer.  The flag `-mno-red-zone'
     disables this red zone.

`-mcmodel=small'
     Generate code for the small code model: the program and its
     symbols must be linked in the lower 2 GB of the address space.
     Pointers are 64 bits.  Programs can be statically or dynamically
     linked.  This is the default code model.

`-mcmodel=kernel'
     Generate code for the kernel code model.  The kernel runs in the
     negative 2 GB of the address space.  This model has to be used for
     Linux kernel code.

`-mcmodel=medium'
     Generate code for the medium model: The program is linked in the
     lower 2 GB of the address space but symbols can be located
     anywhere in the address space.  Programs can be statically or
     dynamically linked, but building of shared libraries are not
     supported with the medium model.

`-mcmodel=large'
     Generate code for the large model: This model makes no assumptions
     about addresses and sizes of sections.  Currently GCC does not
     implement this model.


File: gcc.info,  Node: HPPA Options,  Next: Intel 960 Options,  Prev: i386 and x86-64 Options,  Up: Submodel Options

HPPA Options
------------

   These `-m' options are defined for the HPPA family of computers:

`-march=ARCHITECTURE-TYPE'
     Generate code for the specified architecture.  The choices for
     ARCHITECTURE-TYPE are `1.0' for PA 1.0, `1.1' for PA 1.1, and
     `2.0' for PA 2.0 processors.  Refer to `/usr/lib/sched.models' on
     an HP-UX system to determine the proper architecture option for
     your machine.  Code compiled for lower numbered architectures will
     run on higher numbered architectures, but not the other way around.

     PA 2.0 support currently requires gas snapshot 19990413 or later.
     The next release of binutils (current is 2.9.1) will probably
     contain PA 2.0 support.

`-mpa-risc-1-0'
`-mpa-risc-1-1'
`-mpa-risc-2-0'
     Synonyms for `-march=1.0', `-march=1.1', and `-march=2.0'
     respectively.

`-mbig-switch'
     Generate code suitable for big switch tables.  Use this option
     only if the assembler/linker complain about out of range branches
     within a switch table.

`-mjump-in-delay'
     Fill delay slots of function calls with unconditional jump
     instructions by modifying the return pointer for the function call
     to be the target of the conditional jump.

`-mdisable-fpregs'
     Prevent floating point registers from being used in any manner.
     This is necessary for compiling kernels which perform lazy context
     switching of floating point registers.  If you use this option and
     attempt to perform floating point operations, the compiler will
     abort.

`-mdisable-indexing'
     Prevent the compiler from using indexing address modes.  This
     avoids some rather obscure problems when compiling MIG generated
     code under MACH.

`-mno-space-regs'
     Generate code that assumes the target has no space registers.
     This allows GCC to generate faster indirect calls and use unscaled
     index address modes.

     Such code is suitable for level 0 PA systems and kernels.

`-mfast-indirect-calls'
     Generate code that assumes calls never cross space boundaries.
     This allows GCC to emit code which performs faster indirect calls.

     This option will not work in the presence of shared libraries or
     nested functions.

`-mlong-load-store'
     Generate 3-instruction load and store sequences as sometimes
     required by the HP-UX 10 linker.  This is equivalent to the `+k'
     option to the HP compilers.

`-mportable-runtime'
     Use the portable calling conventions proposed by HP for ELF
     systems.

`-mgas'
     Enable the use of assembler directives only GAS understands.

`-mschedule=CPU-TYPE'
     Schedule code according to the constraints for the machine type
     CPU-TYPE.  The choices for CPU-TYPE are `700' `7100', `7100LC',
     `7200', `7300' and `8000'.  Refer to `/usr/lib/sched.models' on an
     HP-UX system to determine the proper scheduling option for your
     machine.  The default scheduling is `8000'.

`-mlinker-opt'
     Enable the optimization pass in the HP-UX linker.  Note this makes
     symbolic debugging impossible.  It also triggers a bug in the
     HP-UX 8 and HP-UX 9 linkers in which they give bogus error
     messages when linking some programs.

`-msoft-float'
     Generate output containing library calls for floating point.
     *Warning:* the requisite libraries are not available for all HPPA
     targets.  Normally the facilities of the machine's usual C
     compiler are used, but this cannot be done directly in
     cross-compilation.  You must make your own arrangements to provide
     suitable library functions for cross-compilation.  The embedded
     target `hppa1.1-*-pro' does provide software floating point
     support.

     `-msoft-float' changes the calling convention in the output file;
     therefore, it is only useful if you compile _all_ of a program with
     this option.  In particular, you need to compile `libgcc.a', the
     library that comes with GCC, with `-msoft-float' in order for this
     to work.

`-msio'
     Generate the predefine, `_SIO', for server IO.  The default is
     `-mwsio'.  This generates the predefines, `__hp9000s700',
     `__hp9000s700__' and `_WSIO', for workstation IO.  These options
     are available under HP-UX and HI-UX.

`-mgnu-ld'
     Use GNU ld specific options.  This passes `-shared' to ld when
     building a shared library.  It is the default when GCC is
     configured, explicitly or implicitly, with the GNU linker.  This
     option does not have any affect on which ld is called, it only
     changes what parameters are passed to that ld.  The ld that is
     called is determined by the `--with-ld' configure option, gcc's
     program search path, and finally by the user's `PATH'.  The linker
     used by GCC can be printed using `which `gcc -print-prog-name=ld`'.

`-mhp-ld'
     Use HP ld specific options.  This passes `-b' to ld when building
     a shared library and passes `+Accept TypeMismatch' to ld on all
     links.  It is the default when GCC is configured, explicitly or
     implicitly, with the HP linker.  This option does not have any
     affect on which ld is called, it only changes what parameters are
     passed to that ld.  The ld that is called is determined by the
     `--with-ld' configure option, gcc's program search path, and
     finally by the user's `PATH'.  The linker used by GCC can be
     printed using `which `gcc -print-prog-name=ld`'.

`-mlong-calls'
     Generate code that uses long call sequences.  This ensures that a
     call is always able to reach linker generated stubs.  The default
     is to generate long calls only when the distance from the call
     site to the beginning of the function or translation unit, as the
     case may be, exceeds a predefined limit set by the branch type
     being used.  The limits for normal calls are 7,600,000 and 240,000
     bytes, respectively for the PA 2.0 and PA 1.X architectures.
     Sibcalls are always limited at 240,000 bytes.

     Distances are measured from the beginning of functions when using
     the `-ffunction-sections' option, or when using the `-mgas' and
     `-mno-portable-runtime' options together under HP-UX with the SOM
     linker.

     It is normally not desirable to use this option as it will degrade
     performance.  However, it may be useful in large applications,
     particularly when partial linking is used to build the application.

     The types of long calls used depends on the capabilities of the
     assembler and linker, and the type of code being generated.  The
     impact on systems that support long absolute calls, and long pic
     symbol-difference or pc-relative calls should be relatively small.
     However, an indirect call is used on 32-bit ELF systems in pic code
     and it is quite long.

`-nolibdld'
     Suppress the generation of link options to search libdld.sl when
     the `-static' option is specified on HP-UX 10 and later.

`-static'
     The HP-UX implementation of setlocale in libc has a dependency on
     libdld.sl.  There isn't an archive version of libdld.sl.  Thus,
     when the `-static' option is specified, special link options are
     needed to resolve this dependency.

     On HP-UX 10 and later, the GCC driver adds the necessary options to
     link with libdld.sl when the `-static' option is specified.  This
     causes the resulting binary to be dynamic.  On the 64-bit port,
     the linkers generate dynamic binaries by default in any case.  The
     `-nolibdld' option can be used to prevent the GCC driver from
     adding these link options.

`-threads'
     Add support for multithreading with the "dce thread" library under
     HP-UX.  This option sets flags for both the preprocessor and
     linker.


File: gcc.info,  Node: Intel 960 Options,  Next: DEC Alpha Options,  Prev: HPPA Options,  Up: Submodel Options

Intel 960 Options
-----------------

   These `-m' options are defined for the Intel 960 implementations:

`-mCPU-TYPE'
     Assume the defaults for the machine type CPU-TYPE for some of the
     other options, including instruction scheduling, floating point
     support, and addressing modes.  The choices for CPU-TYPE are `ka',
     `kb', `mc', `ca', `cf', `sa', and `sb'.  The default is `kb'.

`-mnumerics'
`-msoft-float'
     The `-mnumerics' option indicates that the processor does support
     floating-point instructions.  The `-msoft-float' option indicates
     that floating-point support should not be assumed.

`-mleaf-procedures'
`-mno-leaf-procedures'
     Do (or do not) attempt to alter leaf procedures to be callable
     with the `bal' instruction as well as `call'.  This will result in
     more efficient code for explicit calls when the `bal' instruction
     can be substituted by the assembler or linker, but less efficient
     code in other cases, such as calls via function pointers, or using
     a linker that doesn't support this optimization.

`-mtail-call'
`-mno-tail-call'
     Do (or do not) make additional attempts (beyond those of the
     machine-independent portions of the compiler) to optimize
     tail-recursive calls into branches.  You may not want to do this
     because the detection of cases where this is not valid is not
     totally complete.  The default is `-mno-tail-call'.

`-mcomplex-addr'
`-mno-complex-addr'
     Assume (or do not assume) that the use of a complex addressing
     mode is a win on this implementation of the i960.  Complex
     addressing modes may not be worthwhile on the K-series, but they
     definitely are on the C-series.  The default is currently
     `-mcomplex-addr' for all processors except the CB and CC.

`-mcode-align'
`-mno-code-align'
     Align code to 8-byte boundaries for faster fetching (or don't
     bother).  Currently turned on by default for C-series
     implementations only.

`-mic-compat'
`-mic2.0-compat'
`-mic3.0-compat'
     Enable compatibility with iC960 v2.0 or v3.0.

`-masm-compat'
`-mintel-asm'
     Enable compatibility with the iC960 assembler.

`-mstrict-align'
`-mno-strict-align'
     Do not permit (do permit) unaligned accesses.

`-mold-align'
     Enable structure-alignment compatibility with Intel's gcc release
     version 1.3 (based on gcc 1.37).  This option implies
     `-mstrict-align'.

`-mlong-double-64'
     Implement type `long double' as 64-bit floating point numbers.
     Without the option `long double' is implemented by 80-bit floating
     point numbers.  The only reason we have it because there is no
     128-bit `long double' support in `fp-bit.c' yet.  So it is only
     useful for people using soft-float targets.  Otherwise, we should
     recommend against use of it.

`-mmove-coalescence'
`-mno-move-coalescence'
     Enable (or disable) coalescing several move instructions in one
     move instruction.  This optimization is on only when unaligned
     access is permitted.  By default the optimization is off.


File: gcc.info,  Node: DEC Alpha Options,  Next: DEC Alpha/VMS Options,  Prev: Intel 960 Options,  Up: Submodel Options

DEC Alpha Options
-----------------

   These `-m' options are defined for the DEC Alpha implementations:

`-mno-soft-float'
`-msoft-float'
     Use (do not use) the hardware floating-point instructions for
     floating-point operations.  When `-msoft-float' is specified,
     functions in `libgcc.a' will be used to perform floating-point
     operations.  Unless they are replaced by routines that emulate the
     floating-point operations, or compiled in such a way as to call
     such emulations routines, these routines will issue floating-point
     operations.   If you are compiling for an Alpha without
     floating-point operations, you must ensure that the library is
     built so as not to call them.

     Note that Alpha implementations without floating-point operations
     are required to have floating-point registers.

`-mfp-reg'
`-mno-fp-regs'
     Generate code that uses (does not use) the floating-point register
     set.  `-mno-fp-regs' implies `-msoft-float'.  If the floating-point
     register set is not used, floating point operands are passed in
     integer registers as if they were integers and floating-point
     results are passed in `$0' instead of `$f0'.  This is a
     non-standard calling sequence, so any function with a
     floating-point argument or return value called by code compiled
     with `-mno-fp-regs' must also be compiled with that option.

     A typical use of this option is building a kernel that does not
     use, and hence need not save and restore, any floating-point
     registers.

`-mieee'
     The Alpha architecture implements floating-point hardware
     optimized for maximum performance.  It is mostly compliant with
     the IEEE floating point standard.  However, for full compliance,
     software assistance is required.  This option generates code fully
     IEEE compliant code _except_ that the INEXACT-FLAG is not
     maintained (see below).  If this option is turned on, the
     preprocessor macro `_IEEE_FP' is defined during compilation.  The
     resulting code is less efficient but is able to correctly support
     denormalized numbers and exceptional IEEE values such as
     not-a-number and plus/minus infinity.  Other Alpha compilers call
     this option `-ieee_with_no_inexact'.

`-mieee-with-inexact'
     This is like `-mieee' except the generated code also maintains the
     IEEE INEXACT-FLAG.  Turning on this option causes the generated
     code to implement fully-compliant IEEE math.  In addition to
     `_IEEE_FP', `_IEEE_FP_EXACT' is defined as a preprocessor macro.
     On some Alpha implementations the resulting code may execute
     significantly slower than the code generated by default.  Since
     there is very little code that depends on the INEXACT-FLAG, you
     should normally not specify this option.  Other Alpha compilers
     call this option `-ieee_with_inexact'.

`-mfp-trap-mode=TRAP-MODE'
     This option controls what floating-point related traps are enabled.
     Other Alpha compilers call this option `-fptm TRAP-MODE'.  The
     trap mode can be set to one of four values:

    `n'
          This is the default (normal) setting.  The only traps that
          are enabled are the ones that cannot be disabled in software
          (e.g., division by zero trap).

    `u'
          In addition to the traps enabled by `n', underflow traps are
          enabled as well.

    `su'
          Like `su', but the instructions are marked to be safe for
          software completion (see Alpha architecture manual for
          details).

    `sui'
          Like `su', but inexact traps are enabled as well.

`-mfp-rounding-mode=ROUNDING-MODE'
     Selects the IEEE rounding mode.  Other Alpha compilers call this
     option `-fprm ROUNDING-MODE'.  The ROUNDING-MODE can be one of:

    `n'
          Normal IEEE rounding mode.  Floating point numbers are
          rounded towards the nearest machine number or towards the
          even machine number in case of a tie.

    `m'
          Round towards minus infinity.

    `c'
          Chopped rounding mode.  Floating point numbers are rounded
          towards zero.

    `d'
          Dynamic rounding mode.  A field in the floating point control
          register (FPCR, see Alpha architecture reference manual)
          controls the rounding mode in effect.  The C library
          initializes this register for rounding towards plus infinity.
          Thus, unless your program modifies the FPCR, `d' corresponds
          to round towards plus infinity.

`-mtrap-precision=TRAP-PRECISION'
     In the Alpha architecture, floating point traps are imprecise.
     This means without software assistance it is impossible to recover
     from a floating trap and program execution normally needs to be
     terminated.  GCC can generate code that can assist operating
     system trap handlers in determining the exact location that caused
     a floating point trap.  Depending on the requirements of an
     application, different levels of precisions can be selected:

    `p'
          Program precision.  This option is the default and means a
          trap handler can only identify which program caused a
          floating point exception.

    `f'
          Function precision.  The trap handler can determine the
          function that caused a floating point exception.

    `i'
          Instruction precision.  The trap handler can determine the
          exact instruction that caused a floating point exception.

     Other Alpha compilers provide the equivalent options called
     `-scope_safe' and `-resumption_safe'.

`-mieee-conformant'
     This option marks the generated code as IEEE conformant.  You must
     not use this option unless you also specify `-mtrap-precision=i'
     and either `-mfp-trap-mode=su' or `-mfp-trap-mode=sui'.  Its only
     effect is to emit the line `.eflag 48' in the function prologue of
     the generated assembly file.  Under DEC Unix, this has the effect
     that IEEE-conformant math library routines will be linked in.

`-mbuild-constants'
     Normally GCC examines a 32- or 64-bit integer constant to see if
     it can construct it from smaller constants in two or three
     instructions.  If it cannot, it will output the constant as a
     literal and generate code to load it from the data segment at
     runtime.

     Use this option to require GCC to construct _all_ integer constants
     using code, even if it takes more instructions (the maximum is
     six).

     You would typically use this option to build a shared library
     dynamic loader.  Itself a shared library, it must relocate itself
     in memory before it can find the variables and constants in its
     own data segment.

`-malpha-as'
`-mgas'
     Select whether to generate code to be assembled by the
     vendor-supplied assembler (`-malpha-as') or by the GNU assembler
     `-mgas'.

`-mbwx'
`-mno-bwx'
`-mcix'
`-mno-cix'
`-mfix'
`-mno-fix'
`-mmax'
`-mno-max'
     Indicate whether GCC should generate code to use the optional BWX,
     CIX, FIX and MAX instruction sets.  The default is to use the
     instruction sets supported by the CPU type specified via `-mcpu='
     option or that of the CPU on which GCC was built if none was
     specified.

`-mfloat-vax'
`-mfloat-ieee'
     Generate code that uses (does not use) VAX F and G floating point
     arithmetic instead of IEEE single and double precision.

`-mexplicit-relocs'
`-mno-explicit-relocs'
     Older Alpha assemblers provided no way to generate symbol
     relocations except via assembler macros.  Use of these macros does
     not allow optimal instruction scheduling.  GNU binutils as of
     version 2.12 supports a new syntax that allows the compiler to
     explicitly mark which relocations should apply to which
     instructions.  This option is mostly useful for debugging, as GCC
     detects the capabilities of the assembler when it is built and
     sets the default accordingly.

`-msmall-data'
`-mlarge-data'
     When `-mexplicit-relocs' is in effect, static data is accessed via
     "gp-relative" relocations.  When `-msmall-data' is used, objects 8
     bytes long or smaller are placed in a "small data area" (the
     `.sdata' and `.sbss' sections) and are accessed via 16-bit
     relocations off of the `$gp' register.  This limits the size of
     the small data area to 64KB, but allows the variables to be
     directly accessed via a single instruction.

     The default is `-mlarge-data'.  With this option the data area is
     limited to just below 2GB.  Programs that require more than 2GB of
     data must use `malloc' or `mmap' to allocate the data in the heap
     instead of in the program's data segment.

     When generating code for shared libraries, `-fpic' implies
     `-msmall-data' and `-fPIC' implies `-mlarge-data'.

`-msmall-text'
`-mlarge-text'
     When `-msmall-text' is used, the compiler assumes that the code of
     the entire program (or shared library) fits in 4MB, and is thus
     reachable with a branch instruction.  When `-msmall-data' is used,
     the compiler can assume that all local symbols share the same
     `$gp' value, and thus reduce the number of instructions required
     for a function call from 4 to 1.

     The default is `-mlarge-text'.

`-mcpu=CPU_TYPE'
     Set the instruction set and instruction scheduling parameters for
     machine type CPU_TYPE.  You can specify either the `EV' style name
     or the corresponding chip number.  GCC supports scheduling
     parameters for the EV4, EV5 and EV6 family of processors and will
     choose the default values for the instruction set from the
     processor you specify.  If you do not specify a processor type,
     GCC will default to the processor on which the compiler was built.

     Supported values for CPU_TYPE are

    `ev4'

    `ev45'
    `21064'
          Schedules as an EV4 and has no instruction set extensions.

    `ev5'
    `21164'
          Schedules as an EV5 and has no instruction set extensions.

    `ev56'
    `21164a'
          Schedules as an EV5 and supports the BWX extension.

    `pca56'
    `21164pc'
    `21164PC'
          Schedules as an EV5 and supports the BWX and MAX extensions.

    `ev6'
    `21264'
          Schedules as an EV6 and supports the BWX, FIX, and MAX
          extensions.

    `ev67'

    `21264a'
          Schedules as an EV6 and supports the BWX, CIX, FIX, and MAX
          extensions.

`-mtune=CPU_TYPE'
     Set only the instruction scheduling parameters for machine type
     CPU_TYPE.  The instruction set is not changed.

`-mmemory-latency=TIME'
     Sets the latency the scheduler should assume for typical memory
     references as seen by the application.  This number is highly
     dependent on the memory access patterns used by the application
     and the size of the external cache on the machine.

     Valid options for TIME are

    `NUMBER'
          A decimal number representing clock cycles.

    `L1'
    `L2'
    `L3'
    `main'
          The compiler contains estimates of the number of clock cycles
          for "typical" EV4 & EV5 hardware for the Level 1, 2 & 3 caches
          (also called Dcache, Scache, and Bcache), as well as to main
          memory.  Note that L3 is only valid for EV5.


File: gcc.info,  Node: DEC Alpha/VMS Options,  Next: H8/300 Options,  Prev: DEC Alpha Options,  Up: Submodel Options

DEC Alpha/VMS Options
---------------------

   These `-m' options are defined for the DEC Alpha/VMS implementations:

`-mvms-return-codes'
     Return VMS condition codes from main.  The default is to return
     POSIX style condition (e.g. error) codes.


File: gcc.info,  Node: H8/300 Options,  Next: SH Options,  Prev: DEC Alpha/VMS Options,  Up: Submodel Options

H8/300 Options
--------------

   These `-m' options are defined for the H8/300 implementations:

`-mrelax'
     Shorten some address references at link time, when possible; uses
     the linker option `-relax'.  *Note `ld' and the H8/300:
     (ld.info)H8/300, for a fuller description.

`-mh'
     Generate code for the H8/300H.

`-ms'
     Generate code for the H8S.

`-mn'
     Generate code for the H8S and H8/300H in the normal mode.  This
     switch must be used either with -mh or -ms.

`-ms2600'
     Generate code for the H8S/2600.  This switch must be used with
     `-ms'.

`-mint32'
     Make `int' data 32 bits by default.

`-malign-300'
     On the H8/300H and H8S, use the same alignment rules as for the
     H8/300.  The default for the H8/300H and H8S is to align longs and
     floats on 4 byte boundaries.  `-malign-300' causes them to be
     aligned on 2 byte boundaries.  This option has no effect on the
     H8/300.


File: gcc.info,  Node: SH Options,  Next: System V Options,  Prev: H8/300 Options,  Up: Submodel Options

SH Options
----------

   These `-m' options are defined for the SH implementations:

`-m1'
     Generate code for the SH1.

`-m2'
     Generate code for the SH2.

`-m2e'
     Generate code for the SH2e.

`-m3'
     Generate code for the SH3.

`-m3e'
     Generate code for the SH3e.

`-m4-nofpu'
     Generate code for the SH4 without a floating-point unit.

`-m4-single-only'
     Generate code for the SH4 with a floating-point unit that only
     supports single-precision arithmetic.

`-m4-single'
     Generate code for the SH4 assuming the floating-point unit is in
     single-precision mode by default.

`-m4'
     Generate code for the SH4.

`-mb'
     Compile code for the processor in big endian mode.

`-ml'
     Compile code for the processor in little endian mode.

`-mdalign'
     Align doubles at 64-bit boundaries.  Note that this changes the
     calling conventions, and thus some functions from the standard C
     library will not work unless you recompile it first with
     `-mdalign'.

`-mrelax'
     Shorten some address references at link time, when possible; uses
     the linker option `-relax'.

`-mbigtable'
     Use 32-bit offsets in `switch' tables.  The default is to use
     16-bit offsets.

`-mfmovd'
     Enable the use of the instruction `fmovd'.

`-mhitachi'
     Comply with the calling conventions defined by Renesas.

`-mnomacsave'
     Mark the `MAC' register as call-clobbered, even if `-mhitachi' is
     given.

`-mieee'
     Increase IEEE-compliance of floating-point code.

`-misize'
     Dump instruction size and location in the assembly code.

`-mpadstruct'
     This option is deprecated.  It pads structures to multiple of 4
     bytes, which is incompatible with the SH ABI.

`-mspace'
     Optimize for space instead of speed.  Implied by `-Os'.

`-mprefergot'
     When generating position-independent code, emit function calls
     using the Global Offset Table instead of the Procedure Linkage
     Table.

`-musermode'
     Generate a library function call to invalidate instruction cache
     entries, after fixing up a trampoline.  This library function call
     doesn't assume it can write to the whole memory address space.
     This is the default when the target is `sh-*-linux*'.


File: gcc.info,  Node: System V Options,  Next: TMS320C3x/C4x Options,  Prev: SH Options,  Up: Submodel Options

Options for System V
--------------------

   These additional options are available on System V Release 4 for
compatibility with other compilers on those systems:

`-G'
     Create a shared object.  It is recommended that `-symbolic' or
     `-shared' be used instead.

`-Qy'
     Identify the versions of each tool used by the compiler, in a
     `.ident' assembler directive in the output.

`-Qn'
     Refrain from adding `.ident' directives to the output file (this is
     the default).

`-YP,DIRS'
     Search the directories DIRS, and no others, for libraries
     specified with `-l'.

`-Ym,DIR'
     Look in the directory DIR to find the M4 preprocessor.  The
     assembler uses this option.


File: gcc.info,  Node: TMS320C3x/C4x Options,  Next: V850 Options,  Prev: System V Options,  Up: Submodel Options

TMS320C3x/C4x Options
---------------------

   These `-m' options are defined for TMS320C3x/C4x implementations:

`-mcpu=CPU_TYPE'
     Set the instruction set, register set, and instruction scheduling
     parameters for machine type CPU_TYPE.  Supported values for
     CPU_TYPE are `c30', `c31', `c32', `c40', and `c44'.  The default
     is `c40' to generate code for the TMS320C40.

`-mbig-memory'

`-mbig'
`-msmall-memory'
`-msmall'
     Generates code for the big or small memory model.  The small memory
     model assumed that all data fits into one 64K word page.  At
     run-time the data page (DP) register must be set to point to the
     64K page containing the .bss and .data program sections.  The big
     memory model is the default and requires reloading of the DP
     register for every direct memory access.

`-mbk'
`-mno-bk'
     Allow (disallow) allocation of general integer operands into the
     block count register BK.

`-mdb'
`-mno-db'
     Enable (disable) generation of code using decrement and branch,
     DBcond(D), instructions.  This is enabled by default for the C4x.
     To be on the safe side, this is disabled for the C3x, since the
     maximum iteration count on the C3x is 2^23 + 1 (but who iterates
     loops more than 2^23 times on the C3x?).  Note that GCC will try
     to reverse a loop so that it can utilize the decrement and branch
     instruction, but will give up if there is more than one memory
     reference in the loop.  Thus a loop where the loop counter is
     decremented can generate slightly more efficient code, in cases
     where the RPTB instruction cannot be utilized.

`-mdp-isr-reload'
`-mparanoid'
     Force the DP register to be saved on entry to an interrupt service
     routine (ISR), reloaded to point to the data section, and restored
     on exit from the ISR.  This should not be required unless someone
     has violated the small memory model by modifying the DP register,
     say within an object library.

`-mmpyi'
`-mno-mpyi'
     For the C3x use the 24-bit MPYI instruction for integer multiplies
     instead of a library call to guarantee 32-bit results.  Note that
     if one of the operands is a constant, then the multiplication will
     be performed using shifts and adds.  If the `-mmpyi' option is not
     specified for the C3x, then squaring operations are performed
     inline instead of a library call.

`-mfast-fix'
`-mno-fast-fix'
     The C3x/C4x FIX instruction to convert a floating point value to an
     integer value chooses the nearest integer less than or equal to the
     floating point value rather than to the nearest integer.  Thus if
     the floating point number is negative, the result will be
     incorrectly truncated an additional code is necessary to detect
     and correct this case.  This option can be used to disable
     generation of the additional code required to correct the result.

`-mrptb'
`-mno-rptb'
     Enable (disable) generation of repeat block sequences using the
     RPTB instruction for zero overhead looping.  The RPTB construct is
     only used for innermost loops that do not call functions or jump
     across the loop boundaries.  There is no advantage having nested
     RPTB loops due to the overhead required to save and restore the
     RC, RS, and RE registers.  This is enabled by default with `-O2'.

`-mrpts=COUNT'
`-mno-rpts'
     Enable (disable) the use of the single instruction repeat
     instruction RPTS.  If a repeat block contains a single
     instruction, and the loop count can be guaranteed to be less than
     the value COUNT, GCC will emit a RPTS instruction instead of a
     RPTB.  If no value is specified, then a RPTS will be emitted even
     if the loop count cannot be determined at compile time.  Note that
     the repeated instruction following RPTS does not have to be
     reloaded from memory each iteration, thus freeing up the CPU buses
     for operands.  However, since interrupts are blocked by this
     instruction, it is disabled by default.

`-mloop-unsigned'
`-mno-loop-unsigned'
     The maximum iteration count when using RPTS and RPTB (and DB on
     the C40) is 2^31 + 1 since these instructions test if the
     iteration count is negative to terminate the loop.  If the
     iteration count is unsigned there is a possibility than the 2^31 +
     1 maximum iteration count may be exceeded.  This switch allows an
     unsigned iteration count.

`-mti'
     Try to emit an assembler syntax that the TI assembler (asm30) is
     happy with.  This also enforces compatibility with the API
     employed by the TI C3x C compiler.  For example, long doubles are
     passed as structures rather than in floating point registers.

`-mregparm'
`-mmemparm'
     Generate code that uses registers (stack) for passing arguments to
     functions.  By default, arguments are passed in registers where
     possible rather than by pushing arguments on to the stack.

`-mparallel-insns'
`-mno-parallel-insns'
     Allow the generation of parallel instructions.  This is enabled by
     default with `-O2'.

`-mparallel-mpy'
`-mno-parallel-mpy'
     Allow the generation of MPY||ADD and MPY||SUB parallel
     instructions, provided `-mparallel-insns' is also specified.
     These instructions have tight register constraints which can
     pessimize the code generation of large functions.

