This is
/es/build/frv-050408/1/frv550-uclinux/X-tools-build/gcc/doc/gcc.info,
produced by makeinfo version 4.0 from
/es/build/frv-050408/1/frv550-uclinux/sources/tools-src/gcc/doc/gcc.texi.

START-INFO-DIR-ENTRY
* usegcc: (usegcc).			Using the GNU C compiler.
END-INFO-DIR-ENTRY

Copyright (C) 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.

   Permission is granted to copy, distribute and/or modify this document
under the terms of the GNU Free Documentation License, Version 1.2 or
any later version published by the Free Software Foundation; with the
Invariant Sections being "GNU General Public License" and "Funding Free
Software", the Front-Cover texts being (a) (see below), and with the
Back-Cover Texts being (b) (see below).  A copy of the license is
included in the section entitled "GNU Free Documentation License".

   (a) The FSF's Front-Cover Text is:

   A GNU Manual

   (b) The FSF's Back-Cover Text is:

   You have freedom to copy and modify this GNU Manual, like GNU
software.  Copies published by the Free Software Foundation raise
funds for GNU development.
INFO-DIR-SECTION Programming
START-INFO-DIR-ENTRY
* gcc: (gcc).                  The GNU Compiler Collection.
END-INFO-DIR-ENTRY
   This file documents the use of the GNU compilers.

   Published by the Free Software Foundation
59 Temple Place - Suite 330
Boston, MA 02111-1307 USA

File: gcc.info,  Node: ARM Options,  Next: MN10200 Options,  Prev: SPARC Options,  Up: Submodel Options

ARM Options
-----------

   These `-m' options are defined for Advanced RISC Machines (ARM)
architectures:

`-mapcs-frame'
     Generate a stack frame that is compliant with the ARM Procedure
     Call Standard for all functions, even if this is not strictly
     necessary for correct execution of the code.  Specifying
     `-fomit-frame-pointer' with this option will cause the stack
     frames not to be generated for leaf functions.  The default is
     `-mno-apcs-frame'.

`-mapcs'
     This is a synonym for `-mapcs-frame'.

`-mapcs-26'
     Generate code for a processor running with a 26-bit program
     counter, and conforming to the function calling standards for the
     APCS 26-bit option.  This option replaces the `-m2' and `-m3'
     options of previous releases of the compiler.

`-mapcs-32'
     Generate code for a processor running with a 32-bit program
     counter, and conforming to the function calling standards for the
     APCS 32-bit option.  This option replaces the `-m6' option of
     previous releases of the compiler.

`-matpcs'
     Generate code that conforms to the ATPCS (ARM Thumb Procedure Call
     Standard).  This ABI standard is slightly different from the APCS
     standard and is incompatible in the way that small structures are
     returned from a function.  For the APCS a structure like this:

          struct { char a; char b; }

     would be returned in memory, whereas for the ATPCS it is returned
     in a register.

`-msa1110-fix'
     Due to a bug in the StrongARM 1110 hardware the LDRSH and LDRSB
     instructions can fail to execute correctly under certain
     circumstances.  Specifying this command line enables a workaround
     in the compiler which causes each and every LDRSH and LDRSB
     instruction to be issued twice.  The second instruction is
     guaranteed to work.

`-mthumb-interwork'
     Generate code which supports calling between the ARM and Thumb
     instruction sets.  Without this option the two instruction sets
     cannot be reliably used inside one program.  The default is
     `-mno-thumb-interwork', since slightly larger code is generated
     when `-mthumb-interwork' is specified.

`-mno-sched-prolog'
     Prevent the reordering of instructions in the function prolog, or
     the merging of those instruction with the instructions in the
     function's body.  This means that all functions will start with a
     recognizable set of instructions (or in fact one of a choice from
     a small set of different function prologues), and this information
     can be used to locate the start if functions inside an executable
     piece of code.  The default is `-msched-prolog'.

`-mhard-float'
     Generate output containing floating point instructions.  This is
     the default.

`-msoft-float'
     Generate output containing library calls for floating point.
     *Warning:* the requisite libraries are not available for all ARM
     targets.  Normally the facilities of the machine's usual C
     compiler are used, but this cannot be done directly in
     cross-compilation.  You must make your own arrangements to provide
     suitable library functions for cross-compilation.

     `-msoft-float' changes the calling convention in the output file;
     therefore, it is only useful if you compile _all_ of a program with
     this option.  In particular, you need to compile `libgcc.a', the
     library that comes with GCC, with `-msoft-float' in order for this
     to work.

`-mlittle-endian'
     Generate code for a processor running in little-endian mode.  This
     is the default for all standard configurations.

`-mbig-endian'
     Generate code for a processor running in big-endian mode; the
     default is to compile code for a little-endian processor.

`-mwords-little-endian'
     This option only applies when generating code for big-endian
     processors.  Generate code for a little-endian word order but a
     big-endian byte order.  That is, a byte order of the form
     `32107654'.  Note: this option should only be used if you require
     compatibility with code for big-endian ARM processors generated by
     versions of the compiler prior to 2.8.

`-malignment-traps'
     Generate code that will not trap if the MMU has alignment traps
     enabled.  On ARM architectures prior to ARMv4, there were no
     instructions to access half-word objects stored in memory.
     However, when reading from memory a feature of the ARM
     architecture allows a word load to be used, even if the address is
     unaligned, and the processor core will rotate the data as it is
     being loaded.  This option tells the compiler that such misaligned
     accesses will cause a MMU trap and that it should instead
     synthesize the access as a series of byte accesses.  The compiler
     can still use word accesses to load half-word data if it knows
     that the address is aligned to a word boundary.

     This option is ignored when compiling for ARM architecture 4 or
     later, since these processors have instructions to directly access
     half-word objects in memory.

`-mno-alignment-traps'
     Generate code that assumes that the MMU will not trap unaligned
     accesses.  This produces better code when the target instruction
     set does not have half-word memory operations (i.e.
     implementations prior to ARMv4).

     Note that you cannot use this option to access unaligned word
     objects, since the processor will only fetch one 32-bit aligned
     object from memory.

     The default setting for most targets is `-mno-alignment-traps',
     since this produces better code when there are no half-word memory
     instructions available.

`-mshort-load-bytes'
`-mno-short-load-words'
     These are deprecated aliases for `-malignment-traps'.

`-mno-short-load-bytes'
`-mshort-load-words'
     This are deprecated aliases for `-mno-alignment-traps'.

`-mcpu=NAME'
     This specifies the name of the target ARM processor.  GCC uses
     this name to determine what kind of instructions it can emit when
     generating assembly code.  Permissible names are: `arm2', `arm250',
     `arm3', `arm6', `arm60', `arm600', `arm610', `arm620', `arm7',
     `arm7m', `arm7d', `arm7dm', `arm7di', `arm7dmi', `arm70', `arm700',
     `arm700i', `arm710', `arm710c', `arm7100', `arm7500', `arm7500fe',
     `arm7tdmi', `arm8', `strongarm', `strongarm110', `strongarm1100',
     `arm8', `arm810', `arm9', `arm9e', `arm920', `arm920t',
     `arm926ejs', `arm940t', `arm9tdmi', `arm10tdmi', `arm1020t',
     `arm1026ejs', `arm1136js', `arm1136jfs' ,`xscale', `iwmmxt',
     `ep9312'.

`-mtune=NAME'
     This option is very similar to the `-mcpu=' option, except that
     instead of specifying the actual target processor type, and hence
     restricting which instructions can be used, it specifies that GCC
     should tune the performance of the code as if the target were of
     the type specified in this option, but still choosing the
     instructions that it will generate based on the cpu specified by a
     `-mcpu=' option.  For some ARM implementations better performance
     can be obtained by using this option.

`-march=NAME'
     This specifies the name of the target ARM architecture.  GCC uses
     this name to determine what kind of instructions it can emit when
     generating assembly code.  This option can be used in conjunction
     with or instead of the `-mcpu=' option.  Permissible names are:
     `armv2', `armv2a', `armv3', `armv3m', `armv4', `armv4t', `armv5',
     `armv5t', `armv5te', `armv6j', `iwmmxt', `ep9312'.

`-mfpe=NUMBER'
`-mfp=NUMBER'
     This specifies the version of the floating point emulation
     available on the target.  Permissible values are 2 and 3.  `-mfp='
     is a synonym for `-mfpe=', for compatibility with older versions
     of GCC.

`-mstructure-size-boundary=N'
     The size of all structures and unions will be rounded up to a
     multiple of the number of bits set by this option.  Permissible
     values are 8 and 32.  The default value varies for different
     toolchains.  For the COFF targeted toolchain the default value is
     8.  Specifying the larger number can produce faster, more
     efficient code, but can also increase the size of the program.
     The two values are potentially incompatible.  Code compiled with
     one value cannot necessarily expect to work with code or libraries
     compiled with the other value, if they exchange information using
     structures or unions.

`-mabort-on-noreturn'
     Generate a call to the function `abort' at the end of a `noreturn'
     function.  It will be executed if the function tries to return.

`-mlong-calls'
`-mno-long-calls'
     Tells the compiler to perform function calls by first loading the
     address of the function into a register and then performing a
     subroutine call on this register.  This switch is needed if the
     target function will lie outside of the 64 megabyte addressing
     range of the offset based version of subroutine call instruction.

     Even if this switch is enabled, not all function calls will be
     turned into long calls.  The heuristic is that static functions,
     functions which have the `short-call' attribute, functions that
     are inside the scope of a `#pragma no_long_calls' directive and
     functions whose definitions have already been compiled within the
     current compilation unit, will not be turned into long calls.  The
     exception to this rule is that weak function definitions,
     functions with the `long-call' attribute or the `section'
     attribute, and functions that are within the scope of a `#pragma
     long_calls' directive, will always be turned into long calls.

     This feature is not enabled by default.  Specifying
     `-mno-long-calls' will restore the default behavior, as will
     placing the function calls within the scope of a `#pragma
     long_calls_off' directive.  Note these switches have no effect on
     how the compiler generates code to handle function calls via
     function pointers.

`-mnop-fun-dllimport'
     Disable support for the `dllimport' attribute.

`-msingle-pic-base'
     Treat the register used for PIC addressing as read-only, rather
     than loading it in the prologue for each function.  The run-time
     system is responsible for initializing this register with an
     appropriate value before execution begins.

`-mpic-register=REG'
     Specify the register to be used for PIC addressing.  The default
     is R10 unless stack-checking is enabled, when R9 is used.

`-mxscale-insert-ldm-nops'
`-mno-xscale-insert-ldm-nops'
     The XScale processors have a hardware problem which can cause a
     function return instruction to take longer to execute than it
     should.  This problem can be worked around by inserting no-op
     instructions at stategic places in the code.  This switch (enabled
     by default) tells the compiler to do this, provided also that
     optimisations have been enabled and optimizing for size `-Os' has
     not been enabled.  It will result in slightly larger code however,
     which may be undesirable.  Hence the inverse switch is able to
     turn this behaviour off.

`-mcirrus-fix-invalid-insns'
     Insert NOPs into the instruction stream to in order to work around
     problems with invalid Maverick instruction combinations.  This
     option is only valid if the `-mcpu=ep9312' option has been used to
     enable generation of instructions for the Cirrus Maverick floating
     point co-processor.  This option is not enabled by default, since
     the problem is only present in older Maverick implementations.
     The default can be re-enabled by use of the
     `-mno-cirrus-fix-invalid-insns' switch.

`-mpoke-function-name'
     Write the name of each function into the text section, directly
     preceding the function prologue.  The generated code is similar to
     this:

               t0
                   .ascii "arm_poke_function_name", 0
                   .align
               t1
                   .word 0xff000000 + (t1 - t0)
               arm_poke_function_name
                   mov     ip, sp
                   stmfd   sp!, {fp, ip, lr, pc}
                   sub     fp, ip, #4

     When performing a stack backtrace, code can inspect the value of
     `pc' stored at `fp + 0'.  If the trace function then looks at
     location `pc - 12' and the top 8 bits are set, then we know that
     there is a function name embedded immediately preceding this
     location and has length `((pc[-3]) & 0xff000000)'.

`-mthumb'
     Generate code for the 16-bit Thumb instruction set.  The default
     is to use the 32-bit ARM instruction set.

`-mtpcs-frame'
     Generate a stack frame that is compliant with the Thumb Procedure
     Call Standard for all non-leaf functions.  (A leaf function is one
     that does not call any other functions.)  The default is
     `-mno-tpcs-frame'.

`-mtpcs-leaf-frame'
     Generate a stack frame that is compliant with the Thumb Procedure
     Call Standard for all leaf functions.  (A leaf function is one
     that does not call any other functions.)  The default is
     `-mno-apcs-leaf-frame'.

`-mcallee-super-interworking'
     Gives all externally visible functions in the file being compiled
     an ARM instruction set header which switches to Thumb mode before
     executing the rest of the function.  This allows these functions
     to be called from non-interworking code.

`-mcaller-super-interworking'
     Allows calls via function pointers (including virtual functions) to
     execute correctly regardless of whether the target code has been
     compiled for interworking or not.  There is a small overhead in
     the cost of executing a function pointer if this option is enabled.


File: gcc.info,  Node: MN10200 Options,  Next: MN10300 Options,  Prev: ARM Options,  Up: Submodel Options

MN10200 Options
---------------

   These `-m' options are defined for Matsushita MN10200 architectures:
`-mrelax'
     Indicate to the linker that it should perform a relaxation
     optimization pass to shorten branches, calls and absolute memory
     addresses.  This option only has an effect when used on the
     command line for the final link step.

     This option makes symbolic debugging impossible.


File: gcc.info,  Node: MN10300 Options,  Next: M32R/D Options,  Prev: MN10200 Options,  Up: Submodel Options

MN10300 Options
---------------

   These `-m' options are defined for Matsushita MN10300 architectures:

`-mmult-bug'
     Generate code to avoid bugs in the multiply instructions for the
     MN10300 processors.  This is the default.

`-mno-mult-bug'
     Do not generate code to avoid bugs in the multiply instructions
     for the MN10300 processors.

`-mam33'
     Generate code which uses features specific to the AM33 processor.

`-mno-am33'
     Do not generate code which uses features specific to the AM33
     processor.  This is the default.

`-mno-crt0'
     Do not link in the C run-time initialization object file.

`-mrelax'
     Indicate to the linker that it should perform a relaxation
     optimization pass to shorten branches, calls and absolute memory
     addresses.  This option only has an effect when used on the
     command line for the final link step.

     This option makes symbolic debugging impossible.


File: gcc.info,  Node: M32R/D Options,  Next: M88K Options,  Prev: MN10300 Options,  Up: Submodel Options

M32R/D Options
--------------

   These `-m' options are defined for Mitsubishi M32R/D architectures:

`-m32rx'
     Generate code for the M32R/X.

`-m32r'
     Generate code for the M32R.  This is the default.

`-mcode-model=small'
     Assume all objects live in the lower 16MB of memory (so that their
     addresses can be loaded with the `ld24' instruction), and assume
     all subroutines are reachable with the `bl' instruction.  This is
     the default.

     The addressability of a particular object can be set with the
     `model' attribute.

`-mcode-model=medium'
     Assume objects may be anywhere in the 32-bit address space (the
     compiler will generate `seth/add3' instructions to load their
     addresses), and assume all subroutines are reachable with the `bl'
     instruction.

`-mcode-model=large'
     Assume objects may be anywhere in the 32-bit address space (the
     compiler will generate `seth/add3' instructions to load their
     addresses), and assume subroutines may not be reachable with the
     `bl' instruction (the compiler will generate the much slower
     `seth/add3/jl' instruction sequence).

`-msdata=none'
     Disable use of the small data area.  Variables will be put into
     one of `.data', `bss', or `.rodata' (unless the `section'
     attribute has been specified).  This is the default.

     The small data area consists of sections `.sdata' and `.sbss'.
     Objects may be explicitly put in the small data area with the
     `section' attribute using one of these sections.

`-msdata=sdata'
     Put small global and static data in the small data area, but do not
     generate special code to reference them.

`-msdata=use'
     Put small global and static data in the small data area, and
     generate special instructions to reference them.

`-G NUM'
     Put global and static objects less than or equal to NUM bytes into
     the small data or bss sections instead of the normal data or bss
     sections.  The default value of NUM is 8.  The `-msdata' option
     must be set to one of `sdata' or `use' for this option to have any
     effect.

     All modules should be compiled with the same `-G NUM' value.
     Compiling with different values of NUM may or may not work; if it
     doesn't the linker will give an error message--incorrect code will
     not be generated.


File: gcc.info,  Node: M88K Options,  Next: RS/6000 and PowerPC Options,  Prev: M32R/D Options,  Up: Submodel Options

M88K Options
------------

   These `-m' options are defined for Motorola 88k architectures:

`-m88000'
     Generate code that works well on both the m88100 and the m88110.

`-m88100'
     Generate code that works best for the m88100, but that also runs
     on the m88110.

`-m88110'
     Generate code that works best for the m88110, and may not run on
     the m88100.

`-mbig-pic'
     Obsolete option to be removed from the next revision.  Use `-fPIC'.

`-midentify-revision'
     Include an `ident' directive in the assembler output recording the
     source file name, compiler name and version, timestamp, and
     compilation flags used.

`-mno-underscores'
     In assembler output, emit symbol names without adding an underscore
     character at the beginning of each name.  The default is to use an
     underscore as prefix on each name.

`-mocs-debug-info'
`-mno-ocs-debug-info'
     Include (or omit) additional debugging information (about
     registers used in each stack frame) as specified in the 88open
     Object Compatibility Standard, "OCS".  This extra information
     allows debugging of code that has had the frame pointer
     eliminated.  The default for SVr4 and Delta 88 SVr3.2 is to
     include this information; other 88k configurations omit this
     information by default.

`-mocs-frame-position'
     When emitting COFF debugging information for automatic variables
     and parameters stored on the stack, use the offset from the
     canonical frame address, which is the stack pointer (register 31)
     on entry to the function.  The SVr4 and Delta88 SVr3.2, and BCS
     configurations use `-mocs-frame-position'; other 88k
     configurations have the default `-mno-ocs-frame-position'.

`-mno-ocs-frame-position'
     When emitting COFF debugging information for automatic variables
     and parameters stored on the stack, use the offset from the frame
     pointer register (register 30).  When this option is in effect,
     the frame pointer is not eliminated when debugging information is
     selected by the -g switch.

`-moptimize-arg-area'
     Save space by reorganizing the stack frame.  This option generates
     code that does not agree with the 88open specifications, but uses
     less memory.

`-mno-optimize-arg-area'
     Do not reorganize the stack frame to save space.  This is the
     default.  The generated conforms to the specification, but uses
     more memory.

`-mshort-data-NUM'
     Generate smaller data references by making them relative to `r0',
     which allows loading a value using a single instruction (rather
     than the usual two).  You control which data references are
     affected by specifying NUM with this option.  For example, if you
     specify `-mshort-data-512', then the data references affected are
     those involving displacements of less than 512 bytes.
     `-mshort-data-NUM' is not effective for NUM greater than 64k.

`-mserialize-volatile'
`-mno-serialize-volatile'
     Do, or don't, generate code to guarantee sequential consistency of
     volatile memory references.  By default, consistency is guaranteed.

     The order of memory references made by the MC88110 processor does
     not always match the order of the instructions requesting those
     references.  In particular, a load instruction may execute before
     a preceding store instruction.  Such reordering violates
     sequential consistency of volatile memory references, when there
     are multiple processors.   When consistency must be guaranteed,
     GCC generates special instructions, as needed, to force execution
     in the proper order.

     The MC88100 processor does not reorder memory references and so
     always provides sequential consistency.  However, by default, GCC
     generates the special instructions to guarantee consistency even
     when you use `-m88100', so that the code may be run on an MC88110
     processor.  If you intend to run your code only on the MC88100
     processor, you may use `-mno-serialize-volatile'.

     The extra code generated to guarantee consistency may affect the
     performance of your application.  If you know that you can safely
     forgo this guarantee, you may use `-mno-serialize-volatile'.

`-msvr4'
`-msvr3'
     Turn on (`-msvr4') or off (`-msvr3') compiler extensions related
     to System V release 4 (SVr4).  This controls the following:

       1. Which variant of the assembler syntax to emit.

       2. `-msvr4' makes the C preprocessor recognize `#pragma weak'
          that is used on System V release 4.

       3. `-msvr4' makes GCC issue additional declaration directives
          used in SVr4.

     `-msvr4' is the default for the m88k-motorola-sysv4 configuration.
     `-msvr3' is the default for all other m88k configurations.

`-mversion-03.00'
     This option is obsolete, and is ignored.

`-mno-check-zero-division'
`-mcheck-zero-division'
     Do, or don't, generate code to guarantee that integer division by
     zero will be detected.  By default, detection is guaranteed.

     Some models of the MC88100 processor fail to trap upon integer
     division by zero under certain conditions.  By default, when
     compiling code that might be run on such a processor, GCC
     generates code that explicitly checks for zero-valued divisors and
     traps with exception number 503 when one is detected.  Use of
     `-mno-check-zero-division' suppresses such checking for code
     generated to run on an MC88100 processor.

     GCC assumes that the MC88110 processor correctly detects all
     instances of integer division by zero.  When `-m88110' is
     specified, no explicit checks for zero-valued divisors are
     generated, and both `-mcheck-zero-division' and
     `-mno-check-zero-division' are ignored.

`-muse-div-instruction'
     Use the div instruction for signed integer division on the MC88100
     processor.  By default, the div instruction is not used.

     On the MC88100 processor the signed integer division instruction
     div) traps to the operating system on a negative operand.  The
     operating system transparently completes the operation, but at a
     large cost in execution time.  By default, when compiling code
     that might be run on an MC88100 processor, GCC emulates signed
     integer division using the unsigned integer division instruction
     divu), thereby avoiding the large penalty of a trap to the
     operating system.  Such emulation has its own, smaller, execution
     cost in both time and space.  To the extent that your code's
     important signed integer division operations are performed on two
     nonnegative operands, it may be desirable to use the div
     instruction directly.

     On the MC88110 processor the div instruction (also known as the
     divs instruction) processes negative operands without trapping to
     the operating system.  When `-m88110' is specified,
     `-muse-div-instruction' is ignored, and the div instruction is used
     for signed integer division.

     Note that the result of dividing `INT_MIN' by -1 is undefined.  In
     particular, the behavior of such a division with and without
     `-muse-div-instruction' may differ.

`-mtrap-large-shift'
`-mhandle-large-shift'
     Include code to detect bit-shifts of more than 31 bits;
     respectively, trap such shifts or emit code to handle them
     properly.  By default GCC makes no special provision for large bit
     shifts.

`-mwarn-passed-structs'
     Warn when a function passes a struct as an argument or result.
     Structure-passing conventions have changed during the evolution of
     the C language, and are often the source of portability problems.
     By default, GCC issues no such warning.

