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/tmp/gdb-8.1/gdb/cris-tdep.c
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1 /* Target dependent code for CRIS, for GDB, the GNU debugger.
2
3 Copyright (C) 2001-2018 Free Software Foundation, Inc.
4
5 Contributed by Axis Communications AB.
6 Written by Hendrik Ruijter, Stefan Andersson, and Orjan Friberg.
7
8 This file is part of GDB.
9
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
14
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22
23 #include "defs.h"
24 #include "frame.h"
25 #include "frame-unwind.h"
26 #include "frame-base.h"
27 #include "trad-frame.h"
28 #include "dwarf2-frame.h"
29 #include "symtab.h"
30 #include "inferior.h"
31 #include "gdbtypes.h"
32 #include "gdbcore.h"
33 #include "gdbcmd.h"
34 #include "target.h"
35 #include "value.h"
36 #include "opcode/cris.h"
37 #include "osabi.h"
38 #include "arch-utils.h"
39 #include "regcache.h"
40
41 #include "objfiles.h"
42
43 #include "solib.h" /* Support for shared libraries. */
44 #include "solib-svr4.h"
45 #include "dis-asm.h"
46
47 #include "cris-tdep.h"
48
49 enum cris_num_regs
50 {
51 /* There are no floating point registers. Used in gdbserver low-linux.c. */
52 NUM_FREGS = 0,
53
54 /* There are 16 general registers. */
55 NUM_GENREGS = 16,
56
57 /* There are 16 special registers. */
58 NUM_SPECREGS = 16,
59
60 /* CRISv32 has a pseudo PC register, not noted here. */
61
62 /* CRISv32 has 16 support registers. */
63 NUM_SUPPREGS = 16
64 };
65
66 /* Register numbers of various important registers.
67 CRIS_FP_REGNUM Contains address of executing stack frame.
68 STR_REGNUM Contains the address of structure return values.
69 RET_REGNUM Contains the return value when shorter than or equal to 32 bits
70 ARG1_REGNUM Contains the first parameter to a function.
71 ARG2_REGNUM Contains the second parameter to a function.
72 ARG3_REGNUM Contains the third parameter to a function.
73 ARG4_REGNUM Contains the fourth parameter to a function. Rest on stack.
74 gdbarch_sp_regnum Contains address of top of stack.
75 gdbarch_pc_regnum Contains address of next instruction.
76 SRP_REGNUM Subroutine return pointer register.
77 BRP_REGNUM Breakpoint return pointer register. */
78
79 enum cris_regnums
80 {
81 /* Enums with respect to the general registers, valid for all
82 CRIS versions. The frame pointer is always in R8. */
83 CRIS_FP_REGNUM = 8,
84 /* ABI related registers. */
85 STR_REGNUM = 9,
86 RET_REGNUM = 10,
87 ARG1_REGNUM = 10,
88 ARG2_REGNUM = 11,
89 ARG3_REGNUM = 12,
90 ARG4_REGNUM = 13,
91
92 /* Registers which happen to be common. */
93 VR_REGNUM = 17,
94 MOF_REGNUM = 23,
95 SRP_REGNUM = 27,
96
97 /* CRISv10 et al. specific registers. */
98 P0_REGNUM = 16,
99 P4_REGNUM = 20,
100 CCR_REGNUM = 21,
101 P8_REGNUM = 24,
102 IBR_REGNUM = 25,
103 IRP_REGNUM = 26,
104 BAR_REGNUM = 28,
105 DCCR_REGNUM = 29,
106 BRP_REGNUM = 30,
107 USP_REGNUM = 31,
108
109 /* CRISv32 specific registers. */
110 ACR_REGNUM = 15,
111 BZ_REGNUM = 16,
112 PID_REGNUM = 18,
113 SRS_REGNUM = 19,
114 WZ_REGNUM = 20,
115 EXS_REGNUM = 21,
116 EDA_REGNUM = 22,
117 DZ_REGNUM = 24,
118 EBP_REGNUM = 25,
119 ERP_REGNUM = 26,
120 NRP_REGNUM = 28,
121 CCS_REGNUM = 29,
122 CRISV32USP_REGNUM = 30, /* Shares name but not number with CRISv10. */
123 SPC_REGNUM = 31,
124 CRISV32PC_REGNUM = 32, /* Shares name but not number with CRISv10. */
125
126 S0_REGNUM = 33,
127 S1_REGNUM = 34,
128 S2_REGNUM = 35,
129 S3_REGNUM = 36,
130 S4_REGNUM = 37,
131 S5_REGNUM = 38,
132 S6_REGNUM = 39,
133 S7_REGNUM = 40,
134 S8_REGNUM = 41,
135 S9_REGNUM = 42,
136 S10_REGNUM = 43,
137 S11_REGNUM = 44,
138 S12_REGNUM = 45,
139 S13_REGNUM = 46,
140 S14_REGNUM = 47,
141 S15_REGNUM = 48,
142 };
143
144 extern const struct cris_spec_reg cris_spec_regs[];
145
146 /* CRIS version, set via the user command 'set cris-version'. Affects
147 register names and sizes. */
148 static unsigned int usr_cmd_cris_version;
149
150 /* Indicates whether to trust the above variable. */
151 static int usr_cmd_cris_version_valid = 0;
152
153 static const char cris_mode_normal[] = "normal";
154 static const char cris_mode_guru[] = "guru";
155 static const char *const cris_modes[] = {
156 cris_mode_normal,
157 cris_mode_guru,
158 0
159 };
160
161 /* CRIS mode, set via the user command 'set cris-mode'. Affects
162 type of break instruction among other things. */
163 static const char *usr_cmd_cris_mode = cris_mode_normal;
164
165 /* Whether to make use of Dwarf-2 CFI (default on). */
166 static int usr_cmd_cris_dwarf2_cfi = 1;
167
168 /* Sigtramp identification code copied from i386-linux-tdep.c. */
169
170 #define SIGTRAMP_INSN0 0x9c5f /* movu.w 0xXX, $r9 */
171 #define SIGTRAMP_OFFSET0 0
172 #define SIGTRAMP_INSN1 0xe93d /* break 13 */
173 #define SIGTRAMP_OFFSET1 4
174
175 static const unsigned short sigtramp_code[] =
176 {
177 SIGTRAMP_INSN0, 0x0077, /* movu.w $0x77, $r9 */
178 SIGTRAMP_INSN1 /* break 13 */
179 };
180
181 #define SIGTRAMP_LEN (sizeof sigtramp_code)
182
183 /* Note: same length as normal sigtramp code. */
184
185 static const unsigned short rt_sigtramp_code[] =
186 {
187 SIGTRAMP_INSN0, 0x00ad, /* movu.w $0xad, $r9 */
188 SIGTRAMP_INSN1 /* break 13 */
189 };
190
191 /* If PC is in a sigtramp routine, return the address of the start of
192 the routine. Otherwise, return 0. */
193
194 static CORE_ADDR
195 cris_sigtramp_start (struct frame_info *this_frame)
196 {
197 CORE_ADDR pc = get_frame_pc (this_frame);
198 gdb_byte buf[SIGTRAMP_LEN];
199
200 if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN))
201 return 0;
202
203 if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN0)
204 {
205 if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN1)
206 return 0;
207
208 pc -= SIGTRAMP_OFFSET1;
209 if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN))
210 return 0;
211 }
212
213 if (memcmp (buf, sigtramp_code, SIGTRAMP_LEN) != 0)
214 return 0;
215
216 return pc;
217 }
218
219 /* If PC is in a RT sigtramp routine, return the address of the start of
220 the routine. Otherwise, return 0. */
221
222 static CORE_ADDR
223 cris_rt_sigtramp_start (struct frame_info *this_frame)
224 {
225 CORE_ADDR pc = get_frame_pc (this_frame);
226 gdb_byte buf[SIGTRAMP_LEN];
227
228 if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN))
229 return 0;
230
231 if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN0)
232 {
233 if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN1)
234 return 0;
235
236 pc -= SIGTRAMP_OFFSET1;
237 if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN))
238 return 0;
239 }
240
241 if (memcmp (buf, rt_sigtramp_code, SIGTRAMP_LEN) != 0)
242 return 0;
243
244 return pc;
245 }
246
247 /* Assuming THIS_FRAME is a frame for a GNU/Linux sigtramp routine,
248 return the address of the associated sigcontext structure. */
249
250 static CORE_ADDR
251 cris_sigcontext_addr (struct frame_info *this_frame)
252 {
253 struct gdbarch *gdbarch = get_frame_arch (this_frame);
254 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
255 CORE_ADDR pc;
256 CORE_ADDR sp;
257 gdb_byte buf[4];
258
259 get_frame_register (this_frame, gdbarch_sp_regnum (gdbarch), buf);
260 sp = extract_unsigned_integer (buf, 4, byte_order);
261
262 /* Look for normal sigtramp frame first. */
263 pc = cris_sigtramp_start (this_frame);
264 if (pc)
265 {
266 /* struct signal_frame (arch/cris/kernel/signal.c) contains
267 struct sigcontext as its first member, meaning the SP points to
268 it already. */
269 return sp;
270 }
271
272 pc = cris_rt_sigtramp_start (this_frame);
273 if (pc)
274 {
275 /* struct rt_signal_frame (arch/cris/kernel/signal.c) contains
276 a struct ucontext, which in turn contains a struct sigcontext.
277 Magic digging:
278 4 + 4 + 128 to struct ucontext, then
279 4 + 4 + 12 to struct sigcontext. */
280 return (sp + 156);
281 }
282
283 error (_("Couldn't recognize signal trampoline."));
284 return 0;
285 }
286
287 struct cris_unwind_cache
288 {
289 /* The previous frame's inner most stack address. Used as this
290 frame ID's stack_addr. */
291 CORE_ADDR prev_sp;
292 /* The frame's base, optionally used by the high-level debug info. */
293 CORE_ADDR base;
294 int size;
295 /* How far the SP and r8 (FP) have been offset from the start of
296 the stack frame (as defined by the previous frame's stack
297 pointer). */
298 LONGEST sp_offset;
299 LONGEST r8_offset;
300 int uses_frame;
301
302 /* From old frame_extra_info struct. */
303 CORE_ADDR return_pc;
304 int leaf_function;
305
306 /* Table indicating the location of each and every register. */
307 struct trad_frame_saved_reg *saved_regs;
308 };
309
310 static struct cris_unwind_cache *
311 cris_sigtramp_frame_unwind_cache (struct frame_info *this_frame,
312 void **this_cache)
313 {
314 struct gdbarch *gdbarch = get_frame_arch (this_frame);
315 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
316 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
317 struct cris_unwind_cache *info;
318 CORE_ADDR addr;
319 gdb_byte buf[4];
320 int i;
321
322 if ((*this_cache))
323 return (struct cris_unwind_cache *) (*this_cache);
324
325 info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache);
326 (*this_cache) = info;
327 info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
328
329 /* Zero all fields. */
330 info->prev_sp = 0;
331 info->base = 0;
332 info->size = 0;
333 info->sp_offset = 0;
334 info->r8_offset = 0;
335 info->uses_frame = 0;
336 info->return_pc = 0;
337 info->leaf_function = 0;
338
339 get_frame_register (this_frame, gdbarch_sp_regnum (gdbarch), buf);
340 info->base = extract_unsigned_integer (buf, 4, byte_order);
341
342 addr = cris_sigcontext_addr (this_frame);
343
344 /* Layout of the sigcontext struct:
345 struct sigcontext {
346 struct pt_regs regs;
347 unsigned long oldmask;
348 unsigned long usp;
349 }; */
350
351 if (tdep->cris_version == 10)
352 {
353 /* R0 to R13 are stored in reverse order at offset (2 * 4) in
354 struct pt_regs. */
355 for (i = 0; i <= 13; i++)
356 info->saved_regs[i].addr = addr + ((15 - i) * 4);
357
358 info->saved_regs[MOF_REGNUM].addr = addr + (16 * 4);
359 info->saved_regs[DCCR_REGNUM].addr = addr + (17 * 4);
360 info->saved_regs[SRP_REGNUM].addr = addr + (18 * 4);
361 /* Note: IRP is off by 2 at this point. There's no point in correcting
362 it though since that will mean that the backtrace will show a PC
363 different from what is shown when stopped. */
364 info->saved_regs[IRP_REGNUM].addr = addr + (19 * 4);
365 info->saved_regs[gdbarch_pc_regnum (gdbarch)]
366 = info->saved_regs[IRP_REGNUM];
367 info->saved_regs[gdbarch_sp_regnum (gdbarch)].addr = addr + (24 * 4);
368 }
369 else
370 {
371 /* CRISv32. */
372 /* R0 to R13 are stored in order at offset (1 * 4) in
373 struct pt_regs. */
374 for (i = 0; i <= 13; i++)
375 info->saved_regs[i].addr = addr + ((i + 1) * 4);
376
377 info->saved_regs[ACR_REGNUM].addr = addr + (15 * 4);
378 info->saved_regs[SRS_REGNUM].addr = addr + (16 * 4);
379 info->saved_regs[MOF_REGNUM].addr = addr + (17 * 4);
380 info->saved_regs[SPC_REGNUM].addr = addr + (18 * 4);
381 info->saved_regs[CCS_REGNUM].addr = addr + (19 * 4);
382 info->saved_regs[SRP_REGNUM].addr = addr + (20 * 4);
383 info->saved_regs[ERP_REGNUM].addr = addr + (21 * 4);
384 info->saved_regs[EXS_REGNUM].addr = addr + (22 * 4);
385 info->saved_regs[EDA_REGNUM].addr = addr + (23 * 4);
386
387 /* FIXME: If ERP is in a delay slot at this point then the PC will
388 be wrong at this point. This problem manifests itself in the
389 sigaltstack.exp test case, which occasionally generates FAILs when
390 the signal is received while in a delay slot.
391
392 This could be solved by a couple of read_memory_unsigned_integer and a
393 trad_frame_set_value. */
394 info->saved_regs[gdbarch_pc_regnum (gdbarch)]
395 = info->saved_regs[ERP_REGNUM];
396
397 info->saved_regs[gdbarch_sp_regnum (gdbarch)].addr
398 = addr + (25 * 4);
399 }
400
401 return info;
402 }
403
404 static void
405 cris_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache,
406 struct frame_id *this_id)
407 {
408 struct cris_unwind_cache *cache =
409 cris_sigtramp_frame_unwind_cache (this_frame, this_cache);
410 (*this_id) = frame_id_build (cache->base, get_frame_pc (this_frame));
411 }
412
413 /* Forward declaration. */
414
415 static struct value *cris_frame_prev_register (struct frame_info *this_frame,
416 void **this_cache, int regnum);
417 static struct value *
418 cris_sigtramp_frame_prev_register (struct frame_info *this_frame,
419 void **this_cache, int regnum)
420 {
421 /* Make sure we've initialized the cache. */
422 cris_sigtramp_frame_unwind_cache (this_frame, this_cache);
423 return cris_frame_prev_register (this_frame, this_cache, regnum);
424 }
425
426 static int
427 cris_sigtramp_frame_sniffer (const struct frame_unwind *self,
428 struct frame_info *this_frame,
429 void **this_cache)
430 {
431 if (cris_sigtramp_start (this_frame)
432 || cris_rt_sigtramp_start (this_frame))
433 return 1;
434
435 return 0;
436 }
437
438 static const struct frame_unwind cris_sigtramp_frame_unwind =
439 {
440 SIGTRAMP_FRAME,
441 default_frame_unwind_stop_reason,
442 cris_sigtramp_frame_this_id,
443 cris_sigtramp_frame_prev_register,
444 NULL,
445 cris_sigtramp_frame_sniffer
446 };
447
448 static int
449 crisv32_single_step_through_delay (struct gdbarch *gdbarch,
450 struct frame_info *this_frame)
451 {
452 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
453 ULONGEST erp;
454 int ret = 0;
455
456 if (tdep->cris_mode == cris_mode_guru)
457 erp = get_frame_register_unsigned (this_frame, NRP_REGNUM);
458 else
459 erp = get_frame_register_unsigned (this_frame, ERP_REGNUM);
460
461 if (erp & 0x1)
462 {
463 /* In delay slot - check if there's a breakpoint at the preceding
464 instruction. */
465 if (breakpoint_here_p (get_frame_address_space (this_frame), erp & ~0x1))
466 ret = 1;
467 }
468 return ret;
469 }
470
471 /* The instruction environment needed to find single-step breakpoints. */
472
473 typedef
474 struct instruction_environment
475 {
476 unsigned long reg[NUM_GENREGS];
477 unsigned long preg[NUM_SPECREGS];
478 unsigned long branch_break_address;
479 unsigned long delay_slot_pc;
480 unsigned long prefix_value;
481 int branch_found;
482 int prefix_found;
483 int invalid;
484 int slot_needed;
485 int delay_slot_pc_active;
486 int xflag_found;
487 int disable_interrupt;
488 enum bfd_endian byte_order;
489 } inst_env_type;
490
491 /* Machine-dependencies in CRIS for opcodes. */
492
493 /* Instruction sizes. */
494 enum cris_instruction_sizes
495 {
496 INST_BYTE_SIZE = 0,
497 INST_WORD_SIZE = 1,
498 INST_DWORD_SIZE = 2
499 };
500
501 /* Addressing modes. */
502 enum cris_addressing_modes
503 {
504 REGISTER_MODE = 1,
505 INDIRECT_MODE = 2,
506 AUTOINC_MODE = 3
507 };
508
509 /* Prefix addressing modes. */
510 enum cris_prefix_addressing_modes
511 {
512 PREFIX_INDEX_MODE = 2,
513 PREFIX_ASSIGN_MODE = 3,
514
515 /* Handle immediate byte offset addressing mode prefix format. */
516 PREFIX_OFFSET_MODE = 2
517 };
518
519 /* Masks for opcodes. */
520 enum cris_opcode_masks
521 {
522 BRANCH_SIGNED_SHORT_OFFSET_MASK = 0x1,
523 SIGNED_EXTEND_BIT_MASK = 0x2,
524 SIGNED_BYTE_MASK = 0x80,
525 SIGNED_BYTE_EXTEND_MASK = 0xFFFFFF00,
526 SIGNED_WORD_MASK = 0x8000,
527 SIGNED_WORD_EXTEND_MASK = 0xFFFF0000,
528 SIGNED_DWORD_MASK = 0x80000000,
529 SIGNED_QUICK_VALUE_MASK = 0x20,
530 SIGNED_QUICK_VALUE_EXTEND_MASK = 0xFFFFFFC0
531 };
532
533 /* Functions for opcodes. The general form of the ETRAX 16-bit instruction:
534 Bit 15 - 12 Operand2
535 11 - 10 Mode
536 9 - 6 Opcode
537 5 - 4 Size
538 3 - 0 Operand1 */
539
540 static int
541 cris_get_operand2 (unsigned short insn)
542 {
543 return ((insn & 0xF000) >> 12);
544 }
545
546 static int
547 cris_get_mode (unsigned short insn)
548 {
549 return ((insn & 0x0C00) >> 10);
550 }
551
552 static int
553 cris_get_opcode (unsigned short insn)
554 {
555 return ((insn & 0x03C0) >> 6);
556 }
557
558 static int
559 cris_get_size (unsigned short insn)
560 {
561 return ((insn & 0x0030) >> 4);
562 }
563
564 static int
565 cris_get_operand1 (unsigned short insn)
566 {
567 return (insn & 0x000F);
568 }
569
570 /* Additional functions in order to handle opcodes. */
571
572 static int
573 cris_get_quick_value (unsigned short insn)
574 {
575 return (insn & 0x003F);
576 }
577
578 static int
579 cris_get_bdap_quick_offset (unsigned short insn)
580 {
581 return (insn & 0x00FF);
582 }
583
584 static int
585 cris_get_branch_short_offset (unsigned short insn)
586 {
587 return (insn & 0x00FF);
588 }
589
590 static int
591 cris_get_asr_shift_steps (unsigned long value)
592 {
593 return (value & 0x3F);
594 }
595
596 static int
597 cris_get_clear_size (unsigned short insn)
598 {
599 return ((insn) & 0xC000);
600 }
601
602 static int
603 cris_is_signed_extend_bit_on (unsigned short insn)
604 {
605 return (((insn) & 0x20) == 0x20);
606 }
607
608 static int
609 cris_is_xflag_bit_on (unsigned short insn)
610 {
611 return (((insn) & 0x1000) == 0x1000);
612 }
613
614 static void
615 cris_set_size_to_dword (unsigned short *insn)
616 {
617 *insn &= 0xFFCF;
618 *insn |= 0x20;
619 }
620
621 static signed char
622 cris_get_signed_offset (unsigned short insn)
623 {
624 return ((signed char) (insn & 0x00FF));
625 }
626
627 /* Calls an op function given the op-type, working on the insn and the
628 inst_env. */
629 static void cris_gdb_func (struct gdbarch *, enum cris_op_type, unsigned short,
630 inst_env_type *);
631
632 static struct gdbarch *cris_gdbarch_init (struct gdbarch_info,
633 struct gdbarch_list *);
634
635 static void cris_dump_tdep (struct gdbarch *, struct ui_file *);
636
637 static void set_cris_version (const char *ignore_args, int from_tty,
638 struct cmd_list_element *c);
639
640 static void set_cris_mode (const char *ignore_args, int from_tty,
641 struct cmd_list_element *c);
642
643 static void set_cris_dwarf2_cfi (const char *ignore_args, int from_tty,
644 struct cmd_list_element *c);
645
646 static CORE_ADDR cris_scan_prologue (CORE_ADDR pc,
647 struct frame_info *this_frame,
648 struct cris_unwind_cache *info);
649
650 static CORE_ADDR crisv32_scan_prologue (CORE_ADDR pc,
651 struct frame_info *this_frame,
652 struct cris_unwind_cache *info);
653
654 static CORE_ADDR cris_unwind_pc (struct gdbarch *gdbarch,
655 struct frame_info *next_frame);
656
657 static CORE_ADDR cris_unwind_sp (struct gdbarch *gdbarch,
658 struct frame_info *next_frame);
659
660 /* When arguments must be pushed onto the stack, they go on in reverse
661 order. The below implements a FILO (stack) to do this.
662 Copied from d10v-tdep.c. */
663
664 struct stack_item
665 {
666 int len;
667 struct stack_item *prev;
668 gdb_byte *data;
669 };
670
671 static struct stack_item *
672 push_stack_item (struct stack_item *prev, const gdb_byte *contents, int len)
673 {
674 struct stack_item *si = XNEW (struct stack_item);
675 si->data = (gdb_byte *) xmalloc (len);
676 si->len = len;
677 si->prev = prev;
678 memcpy (si->data, contents, len);
679 return si;
680 }
681
682 static struct stack_item *
683 pop_stack_item (struct stack_item *si)
684 {
685 struct stack_item *dead = si;
686 si = si->prev;
687 xfree (dead->data);
688 xfree (dead);
689 return si;
690 }
691
692 /* Put here the code to store, into fi->saved_regs, the addresses of
693 the saved registers of frame described by FRAME_INFO. This
694 includes special registers such as pc and fp saved in special ways
695 in the stack frame. sp is even more special: the address we return
696 for it IS the sp for the next frame. */
697
698 static struct cris_unwind_cache *
699 cris_frame_unwind_cache (struct frame_info *this_frame,
700 void **this_prologue_cache)
701 {
702 struct gdbarch *gdbarch = get_frame_arch (this_frame);
703 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
704 struct cris_unwind_cache *info;
705
706 if ((*this_prologue_cache))
707 return (struct cris_unwind_cache *) (*this_prologue_cache);
708
709 info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache);
710 (*this_prologue_cache) = info;
711 info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
712
713 /* Zero all fields. */
714 info->prev_sp = 0;
715 info->base = 0;
716 info->size = 0;
717 info->sp_offset = 0;
718 info->r8_offset = 0;
719 info->uses_frame = 0;
720 info->return_pc = 0;
721 info->leaf_function = 0;
722
723 /* Prologue analysis does the rest... */
724 if (tdep->cris_version == 32)
725 crisv32_scan_prologue (get_frame_func (this_frame), this_frame, info);
726 else
727 cris_scan_prologue (get_frame_func (this_frame), this_frame, info);
728
729 return info;
730 }
731
732 /* Given a GDB frame, determine the address of the calling function's
733 frame. This will be used to create a new GDB frame struct. */
734
735 static void
736 cris_frame_this_id (struct frame_info *this_frame,
737 void **this_prologue_cache,
738 struct frame_id *this_id)
739 {
740 struct cris_unwind_cache *info
741 = cris_frame_unwind_cache (this_frame, this_prologue_cache);
742 CORE_ADDR base;
743 CORE_ADDR func;
744 struct frame_id id;
745
746 /* The FUNC is easy. */
747 func = get_frame_func (this_frame);
748
749 /* Hopefully the prologue analysis either correctly determined the
750 frame's base (which is the SP from the previous frame), or set
751 that base to "NULL". */
752 base = info->prev_sp;
753 if (base == 0)
754 return;
755
756 id = frame_id_build (base, func);
757
758 (*this_id) = id;
759 }
760
761 static struct value *
762 cris_frame_prev_register (struct frame_info *this_frame,
763 void **this_prologue_cache, int regnum)
764 {
765 struct cris_unwind_cache *info
766 = cris_frame_unwind_cache (this_frame, this_prologue_cache);
767 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
768 }
769
770 /* Assuming THIS_FRAME is a dummy, return the frame ID of that dummy
771 frame. The frame ID's base needs to match the TOS value saved by
772 save_dummy_frame_tos(), and the PC match the dummy frame's breakpoint. */
773
774 static struct frame_id
775 cris_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
776 {
777 CORE_ADDR sp;
778 sp = get_frame_register_unsigned (this_frame, gdbarch_sp_regnum (gdbarch));
779 return frame_id_build (sp, get_frame_pc (this_frame));
780 }
781
782 static CORE_ADDR
783 cris_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
784 {
785 /* Align to the size of an instruction (so that they can safely be
786 pushed onto the stack). */
787 return sp & ~3;
788 }
789
790 static CORE_ADDR
791 cris_push_dummy_code (struct gdbarch *gdbarch,
792 CORE_ADDR sp, CORE_ADDR funaddr,
793 struct value **args, int nargs,
794 struct type *value_type,
795 CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
796 struct regcache *regcache)
797 {
798 /* Allocate space sufficient for a breakpoint. */
799 sp = (sp - 4) & ~3;
800 /* Store the address of that breakpoint */
801 *bp_addr = sp;
802 /* CRIS always starts the call at the callee's entry point. */
803 *real_pc = funaddr;
804 return sp;
805 }
806
807 static CORE_ADDR
808 cris_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
809 struct regcache *regcache, CORE_ADDR bp_addr,
810 int nargs, struct value **args, CORE_ADDR sp,
811 int struct_return, CORE_ADDR struct_addr)
812 {
813 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
814 int argreg;
815 int argnum;
816
817 struct stack_item *si = NULL;
818
819 /* Push the return address. */
820 regcache_cooked_write_unsigned (regcache, SRP_REGNUM, bp_addr);
821
822 /* Are we returning a value using a structure return or a normal value
823 return? struct_addr is the address of the reserved space for the return
824 structure to be written on the stack. */
825 if (struct_return)
826 {
827 regcache_cooked_write_unsigned (regcache, STR_REGNUM, struct_addr);
828 }
829
830 /* Now load as many as possible of the first arguments into registers,
831 and push the rest onto the stack. */
832 argreg = ARG1_REGNUM;
833
834 for (argnum = 0; argnum < nargs; argnum++)
835 {
836 int len;
837 const gdb_byte *val;
838 int reg_demand;
839 int i;
840
841 len = TYPE_LENGTH (value_type (args[argnum]));
842 val = value_contents (args[argnum]);
843
844 /* How may registers worth of storage do we need for this argument? */
845 reg_demand = (len / 4) + (len % 4 != 0 ? 1 : 0);
846
847 if (len <= (2 * 4) && (argreg + reg_demand - 1 <= ARG4_REGNUM))
848 {
849 /* Data passed by value. Fits in available register(s). */
850 for (i = 0; i < reg_demand; i++)
851 {
852 regcache_cooked_write (regcache, argreg, val);
853 argreg++;
854 val += 4;
855 }
856 }
857 else if (len <= (2 * 4) && argreg <= ARG4_REGNUM)
858 {
859 /* Data passed by value. Does not fit in available register(s).
860 Use the register(s) first, then the stack. */
861 for (i = 0; i < reg_demand; i++)
862 {
863 if (argreg <= ARG4_REGNUM)
864 {
865 regcache_cooked_write (regcache, argreg, val);
866 argreg++;
867 val += 4;
868 }
869 else
870 {
871 /* Push item for later so that pushed arguments
872 come in the right order. */
873 si = push_stack_item (si, val, 4);
874 val += 4;
875 }
876 }
877 }
878 else if (len > (2 * 4))
879 {
880 /* Data passed by reference. Push copy of data onto stack
881 and pass pointer to this copy as argument. */
882 sp = (sp - len) & ~3;
883 write_memory (sp, val, len);
884
885 if (argreg <= ARG4_REGNUM)
886 {
887 regcache_cooked_write_unsigned (regcache, argreg, sp);
888 argreg++;
889 }
890 else
891 {
892 gdb_byte buf[4];
893 store_unsigned_integer (buf, 4, byte_order, sp);
894 si = push_stack_item (si, buf, 4);
895 }
896 }
897 else
898 {
899 /* Data passed by value. No available registers. Put it on
900 the stack. */
901 si = push_stack_item (si, val, len);
902 }
903 }
904
905 while (si)
906 {
907 /* fp_arg must be word-aligned (i.e., don't += len) to match
908 the function prologue. */
909 sp = (sp - si->len) & ~3;
910 write_memory (sp, si->data, si->len);
911 si = pop_stack_item (si);
912 }
913
914 /* Finally, update the SP register. */
915 regcache_cooked_write_unsigned (regcache, gdbarch_sp_regnum (gdbarch), sp);
916
917 return sp;
918 }
919
920 static const struct frame_unwind cris_frame_unwind =
921 {
922 NORMAL_FRAME,
923 default_frame_unwind_stop_reason,
924 cris_frame_this_id,
925 cris_frame_prev_register,
926 NULL,
927 default_frame_sniffer
928 };
929
930 static CORE_ADDR
931 cris_frame_base_address (struct frame_info *this_frame, void **this_cache)
932 {
933 struct cris_unwind_cache *info
934 = cris_frame_unwind_cache (this_frame, this_cache);
935 return info->base;
936 }
937
938 static const struct frame_base cris_frame_base =
939 {
940 &cris_frame_unwind,
941 cris_frame_base_address,
942 cris_frame_base_address,
943 cris_frame_base_address
944 };
945
946 /* Frames information. The definition of the struct frame_info is
947
948 CORE_ADDR frame
949 CORE_ADDR pc
950 enum frame_type type;
951 CORE_ADDR return_pc
952 int leaf_function
953
954 If the compilation option -fno-omit-frame-pointer is present the
955 variable frame will be set to the content of R8 which is the frame
956 pointer register.
957
958 The variable pc contains the address where execution is performed
959 in the present frame. The innermost frame contains the current content
960 of the register PC. All other frames contain the content of the
961 register PC in the next frame.
962
963 The variable `type' indicates the frame's type: normal, SIGTRAMP
964 (associated with a signal handler), dummy (associated with a dummy
965 frame).
966
967 The variable return_pc contains the address where execution should be
968 resumed when the present frame has finished, the return address.
969
970 The variable leaf_function is 1 if the return address is in the register
971 SRP, and 0 if it is on the stack.
972
973 Prologue instructions C-code.
974 The prologue may consist of (-fno-omit-frame-pointer)
975 1) 2)
976 push srp
977 push r8 push r8
978 move.d sp,r8 move.d sp,r8
979 subq X,sp subq X,sp
980 movem rY,[sp] movem rY,[sp]
981 move.S rZ,[r8-U] move.S rZ,[r8-U]
982
983 where 1 is a non-terminal function, and 2 is a leaf-function.
984
985 Note that this assumption is extremely brittle, and will break at the
986 slightest change in GCC's prologue.
987
988 If local variables are declared or register contents are saved on stack
989 the subq-instruction will be present with X as the number of bytes
990 needed for storage. The reshuffle with respect to r8 may be performed
991 with any size S (b, w, d) and any of the general registers Z={0..13}.
992 The offset U should be representable by a signed 8-bit value in all cases.
993 Thus, the prefix word is assumed to be immediate byte offset mode followed
994 by another word containing the instruction.
995
996 Degenerate cases:
997 3)
998 push r8
999 move.d sp,r8
1000 move.d r8,sp
1001 pop r8
1002
1003 Prologue instructions C++-code.
1004 Case 1) and 2) in the C-code may be followed by
1005
1006 move.d r10,rS ; this
1007 move.d r11,rT ; P1
1008 move.d r12,rU ; P2
1009 move.d r13,rV ; P3
1010 move.S [r8+U],rZ ; P4
1011
1012 if any of the call parameters are stored. The host expects these
1013 instructions to be executed in order to get the call parameters right. */
1014
1015 /* Examine the prologue of a function. The variable ip is the address of
1016 the first instruction of the prologue. The variable limit is the address
1017 of the first instruction after the prologue. The variable fi contains the
1018 information in struct frame_info. The variable frameless_p controls whether
1019 the entire prologue is examined (0) or just enough instructions to
1020 determine that it is a prologue (1). */
1021
1022 static CORE_ADDR
1023 cris_scan_prologue (CORE_ADDR pc, struct frame_info *this_frame,
1024 struct cris_unwind_cache *info)
1025 {
1026 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1027 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1028
1029 /* Present instruction. */
1030 unsigned short insn;
1031
1032 /* Next instruction, lookahead. */
1033 unsigned short insn_next;
1034 int regno;
1035
1036 /* Number of byte on stack used for local variables and movem. */
1037 int val;
1038
1039 /* Highest register number in a movem. */
1040 int regsave;
1041
1042 /* move.d r<source_register>,rS */
1043 short source_register;
1044
1045 /* Scan limit. */
1046 int limit;
1047
1048 /* This frame is with respect to a leaf until a push srp is found. */
1049 if (info)
1050 {
1051 info->leaf_function = 1;
1052 }
1053
1054 /* Assume nothing on stack. */
1055 val = 0;
1056 regsave = -1;
1057
1058 /* If we were called without a this_frame, that means we were called
1059 from cris_skip_prologue which already tried to find the end of the
1060 prologue through the symbol information. 64 instructions past current
1061 pc is arbitrarily chosen, but at least it means we'll stop eventually. */
1062 limit = this_frame ? get_frame_pc (this_frame) : pc + 64;
1063
1064 /* Find the prologue instructions. */
1065 while (pc > 0 && pc < limit)
1066 {
1067 insn = read_memory_unsigned_integer (pc, 2, byte_order);
1068 pc += 2;
1069 if (insn == 0xE1FC)
1070 {
1071 /* push <reg> 32 bit instruction. */
1072 insn_next = read_memory_unsigned_integer (pc, 2, byte_order);
1073 pc += 2;
1074 regno = cris_get_operand2 (insn_next);
1075 if (info)
1076 {
1077 info->sp_offset += 4;
1078 }
1079 /* This check, meant to recognize srp, used to be regno ==
1080 (SRP_REGNUM - NUM_GENREGS), but that covers r11 also. */
1081 if (insn_next == 0xBE7E)
1082 {
1083 if (info)
1084 {
1085 info->leaf_function = 0;
1086 }
1087 }
1088 else if (insn_next == 0x8FEE)
1089 {
1090 /* push $r8 */
1091 if (info)
1092 {
1093 info->r8_offset = info->sp_offset;
1094 }
1095 }
1096 }
1097 else if (insn == 0x866E)
1098 {
1099 /* move.d sp,r8 */
1100 if (info)
1101 {
1102 info->uses_frame = 1;
1103 }
1104 continue;
1105 }
1106 else if (cris_get_operand2 (insn) == gdbarch_sp_regnum (gdbarch)
1107 && cris_get_mode (insn) == 0x0000
1108 && cris_get_opcode (insn) == 0x000A)
1109 {
1110 /* subq <val>,sp */
1111 if (info)
1112 {
1113 info->sp_offset += cris_get_quick_value (insn);
1114 }
1115 }
1116 else if (cris_get_mode (insn) == 0x0002
1117 && cris_get_opcode (insn) == 0x000F
1118 && cris_get_size (insn) == 0x0003
1119 && cris_get_operand1 (insn) == gdbarch_sp_regnum (gdbarch))
1120 {
1121 /* movem r<regsave>,[sp] */
1122 regsave = cris_get_operand2 (insn);
1123 }
1124 else if (cris_get_operand2 (insn) == gdbarch_sp_regnum (gdbarch)
1125 && ((insn & 0x0F00) >> 8) == 0x0001
1126 && (cris_get_signed_offset (insn) < 0))
1127 {
1128 /* Immediate byte offset addressing prefix word with sp as base
1129 register. Used for CRIS v8 i.e. ETRAX 100 and newer if <val>
1130 is between 64 and 128.
1131 movem r<regsave>,[sp=sp-<val>] */
1132 if (info)
1133 {
1134 info->sp_offset += -cris_get_signed_offset (insn);
1135 }
1136 insn_next = read_memory_unsigned_integer (pc, 2, byte_order);
1137 pc += 2;
1138 if (cris_get_mode (insn_next) == PREFIX_ASSIGN_MODE
1139 && cris_get_opcode (insn_next) == 0x000F
1140 && cris_get_size (insn_next) == 0x0003
1141 && cris_get_operand1 (insn_next) == gdbarch_sp_regnum
1142 (gdbarch))
1143 {
1144 regsave = cris_get_operand2 (insn_next);
1145 }
1146 else
1147 {
1148 /* The prologue ended before the limit was reached. */
1149 pc -= 4;
1150 break;
1151 }
1152 }
1153 else if (cris_get_mode (insn) == 0x0001
1154 && cris_get_opcode (insn) == 0x0009
1155 && cris_get_size (insn) == 0x0002)
1156 {
1157 /* move.d r<10..13>,r<0..15> */
1158 source_register = cris_get_operand1 (insn);
1159
1160 /* FIXME? In the glibc solibs, the prologue might contain something
1161 like (this example taken from relocate_doit):
1162 move.d $pc,$r0
1163 sub.d 0xfffef426,$r0
1164 which isn't covered by the source_register check below. Question
1165 is whether to add a check for this combo, or make better use of
1166 the limit variable instead. */
1167 if (source_register < ARG1_REGNUM || source_register > ARG4_REGNUM)
1168 {
1169 /* The prologue ended before the limit was reached. */
1170 pc -= 2;
1171 break;
1172 }
1173 }
1174 else if (cris_get_operand2 (insn) == CRIS_FP_REGNUM
1175 /* The size is a fixed-size. */
1176 && ((insn & 0x0F00) >> 8) == 0x0001
1177 /* A negative offset. */
1178 && (cris_get_signed_offset (insn) < 0))
1179 {
1180 /* move.S rZ,[r8-U] (?) */
1181 insn_next = read_memory_unsigned_integer (pc, 2, byte_order);
1182 pc += 2;
1183 regno = cris_get_operand2 (insn_next);
1184 if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch))
1185 && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE
1186 && cris_get_opcode (insn_next) == 0x000F)
1187 {
1188 /* move.S rZ,[r8-U] */
1189 continue;
1190 }
1191 else
1192 {
1193 /* The prologue ended before the limit was reached. */
1194 pc -= 4;
1195 break;
1196 }
1197 }
1198 else if (cris_get_operand2 (insn) == CRIS_FP_REGNUM
1199 /* The size is a fixed-size. */
1200 && ((insn & 0x0F00) >> 8) == 0x0001
1201 /* A positive offset. */
1202 && (cris_get_signed_offset (insn) > 0))
1203 {
1204 /* move.S [r8+U],rZ (?) */
1205 insn_next = read_memory_unsigned_integer (pc, 2, byte_order);
1206 pc += 2;
1207 regno = cris_get_operand2 (insn_next);
1208 if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch))
1209 && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE
1210 && cris_get_opcode (insn_next) == 0x0009
1211 && cris_get_operand1 (insn_next) == regno)
1212 {
1213 /* move.S [r8+U],rZ */
1214 continue;
1215 }
1216 else
1217 {
1218 /* The prologue ended before the limit was reached. */
1219 pc -= 4;
1220 break;
1221 }
1222 }
1223 else
1224 {
1225 /* The prologue ended before the limit was reached. */
1226 pc -= 2;
1227 break;
1228 }
1229 }
1230
1231 /* We only want to know the end of the prologue when this_frame and info
1232 are NULL (called from cris_skip_prologue i.e.). */
1233 if (this_frame == NULL && info == NULL)
1234 {
1235 return pc;
1236 }
1237
1238 info->size = info->sp_offset;
1239
1240 /* Compute the previous frame's stack pointer (which is also the
1241 frame's ID's stack address), and this frame's base pointer. */
1242 if (info->uses_frame)
1243 {
1244 ULONGEST this_base;
1245 /* The SP was moved to the FP. This indicates that a new frame
1246 was created. Get THIS frame's FP value by unwinding it from
1247 the next frame. */
1248 this_base = get_frame_register_unsigned (this_frame, CRIS_FP_REGNUM);
1249 info->base = this_base;
1250 info->saved_regs[CRIS_FP_REGNUM].addr = info->base;
1251
1252 /* The FP points at the last saved register. Adjust the FP back
1253 to before the first saved register giving the SP. */
1254 info->prev_sp = info->base + info->r8_offset;
1255 }
1256 else
1257 {
1258 ULONGEST this_base;
1259 /* Assume that the FP is this frame's SP but with that pushed
1260 stack space added back. */
1261 this_base = get_frame_register_unsigned (this_frame,
1262 gdbarch_sp_regnum (gdbarch));
1263 info->base = this_base;
1264 info->prev_sp = info->base + info->size;
1265 }
1266
1267 /* Calculate the addresses for the saved registers on the stack. */
1268 /* FIXME: The address calculation should really be done on the fly while
1269 we're analyzing the prologue (we only hold one regsave value as it is
1270 now). */
1271 val = info->sp_offset;
1272
1273 for (regno = regsave; regno >= 0; regno--)
1274 {
1275 info->saved_regs[regno].addr = info->base + info->r8_offset - val;
1276 val -= 4;
1277 }
1278
1279 /* The previous frame's SP needed to be computed. Save the computed
1280 value. */
1281 trad_frame_set_value (info->saved_regs,
1282 gdbarch_sp_regnum (gdbarch), info->prev_sp);
1283
1284 if (!info->leaf_function)
1285 {
1286 /* SRP saved on the stack. But where? */
1287 if (info->r8_offset == 0)
1288 {
1289 /* R8 not pushed yet. */
1290 info->saved_regs[SRP_REGNUM].addr = info->base;
1291 }
1292 else
1293 {
1294 /* R8 pushed, but SP may or may not be moved to R8 yet. */
1295 info->saved_regs[SRP_REGNUM].addr = info->base + 4;
1296 }
1297 }
1298
1299 /* The PC is found in SRP (the actual register or located on the stack). */
1300 info->saved_regs[gdbarch_pc_regnum (gdbarch)]
1301 = info->saved_regs[SRP_REGNUM];
1302
1303 return pc;
1304 }
1305
1306 static CORE_ADDR
1307 crisv32_scan_prologue (CORE_ADDR pc, struct frame_info *this_frame,
1308 struct cris_unwind_cache *info)
1309 {
1310 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1311 ULONGEST this_base;
1312
1313 /* Unlike the CRISv10 prologue scanner (cris_scan_prologue), this is not
1314 meant to be a full-fledged prologue scanner. It is only needed for
1315 the cases where we end up in code always lacking DWARF-2 CFI, notably:
1316
1317 * PLT stubs (library calls)
1318 * call dummys
1319 * signal trampolines
1320
1321 For those cases, it is assumed that there is no actual prologue; that
1322 the stack pointer is not adjusted, and (as a consequence) the return
1323 address is not pushed onto the stack. */
1324
1325 /* We only want to know the end of the prologue when this_frame and info
1326 are NULL (called from cris_skip_prologue i.e.). */
1327 if (this_frame == NULL && info == NULL)
1328 {
1329 return pc;
1330 }
1331
1332 /* The SP is assumed to be unaltered. */
1333 this_base = get_frame_register_unsigned (this_frame,
1334 gdbarch_sp_regnum (gdbarch));
1335 info->base = this_base;
1336 info->prev_sp = this_base;
1337
1338 /* The PC is assumed to be found in SRP. */
1339 info->saved_regs[gdbarch_pc_regnum (gdbarch)]
1340 = info->saved_regs[SRP_REGNUM];
1341
1342 return pc;
1343 }
1344
1345 /* Advance pc beyond any function entry prologue instructions at pc
1346 to reach some "real" code. */
1347
1348 /* Given a PC value corresponding to the start of a function, return the PC
1349 of the first instruction after the function prologue. */
1350
1351 static CORE_ADDR
1352 cris_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1353 {
1354 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1355 CORE_ADDR func_addr, func_end;
1356 struct symtab_and_line sal;
1357 CORE_ADDR pc_after_prologue;
1358
1359 /* If we have line debugging information, then the end of the prologue
1360 should the first assembly instruction of the first source line. */
1361 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
1362 {
1363 sal = find_pc_line (func_addr, 0);
1364 if (sal.end > 0 && sal.end < func_end)
1365 return sal.end;
1366 }
1367
1368 if (tdep->cris_version == 32)
1369 pc_after_prologue = crisv32_scan_prologue (pc, NULL, NULL);
1370 else
1371 pc_after_prologue = cris_scan_prologue (pc, NULL, NULL);
1372
1373 return pc_after_prologue;
1374 }
1375
1376 static CORE_ADDR
1377 cris_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1378 {
1379 ULONGEST pc;
1380 pc = frame_unwind_register_unsigned (next_frame,
1381 gdbarch_pc_regnum (gdbarch));
1382 return pc;
1383 }
1384
1385 static CORE_ADDR
1386 cris_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1387 {
1388 ULONGEST sp;
1389 sp = frame_unwind_register_unsigned (next_frame,
1390 gdbarch_sp_regnum (gdbarch));
1391 return sp;
1392 }
1393
1394 /* Implement the breakpoint_kind_from_pc gdbarch method. */
1395
1396 static int
1397 cris_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr)
1398 {
1399 return 2;
1400 }
1401
1402 /* Implement the sw_breakpoint_from_kind gdbarch method. */
1403
1404 static const gdb_byte *
1405 cris_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size)
1406 {
1407 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1408 static unsigned char break8_insn[] = {0x38, 0xe9};
1409 static unsigned char break15_insn[] = {0x3f, 0xe9};
1410
1411 *size = kind;
1412
1413 if (tdep->cris_mode == cris_mode_guru)
1414 return break15_insn;
1415 else
1416 return break8_insn;
1417 }
1418
1419 /* Returns 1 if spec_reg is applicable to the current gdbarch's CRIS version,
1420 0 otherwise. */
1421
1422 static int
1423 cris_spec_reg_applicable (struct gdbarch *gdbarch,
1424 struct cris_spec_reg spec_reg)
1425 {
1426 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1427 unsigned int version = tdep->cris_version;
1428
1429 switch (spec_reg.applicable_version)
1430 {
1431 case cris_ver_version_all:
1432 return 1;
1433 case cris_ver_warning:
1434 /* Indeterminate/obsolete. */
1435 return 0;
1436 case cris_ver_v0_3:
1437 return in_inclusive_range (version, 0U, 3U);
1438 case cris_ver_v3p:
1439 return (version >= 3);
1440 case cris_ver_v8:
1441 return in_inclusive_range (version, 8U, 9U);
1442 case cris_ver_v8p:
1443 return (version >= 8);
1444 case cris_ver_v0_10:
1445 return in_inclusive_range (version, 0U, 10U);
1446 case cris_ver_v3_10:
1447 return in_inclusive_range (version, 3U, 10U);
1448 case cris_ver_v8_10:
1449 return in_inclusive_range (version, 8U, 10U);
1450 case cris_ver_v10:
1451 return (version == 10);
1452 case cris_ver_v10p:
1453 return (version >= 10);
1454 case cris_ver_v32p:
1455 return (version >= 32);
1456 default:
1457 /* Invalid cris version. */
1458 return 0;
1459 }
1460 }
1461
1462 /* Returns the register size in unit byte. Returns 0 for an unimplemented
1463 register, -1 for an invalid register. */
1464
1465 static int
1466 cris_register_size (struct gdbarch *gdbarch, int regno)
1467 {
1468 int i;
1469 int spec_regno;
1470
1471 if (regno >= 0 && regno < NUM_GENREGS)
1472 {
1473 /* General registers (R0 - R15) are 32 bits. */
1474 return 4;
1475 }
1476 else if (regno >= NUM_GENREGS && regno < (NUM_GENREGS + NUM_SPECREGS))
1477 {
1478 /* Special register (R16 - R31). cris_spec_regs is zero-based.
1479 Adjust regno accordingly. */
1480 spec_regno = regno - NUM_GENREGS;
1481
1482 for (i = 0; cris_spec_regs[i].name != NULL; i++)
1483 {
1484 if (cris_spec_regs[i].number == spec_regno
1485 && cris_spec_reg_applicable (gdbarch, cris_spec_regs[i]))
1486 /* Go with the first applicable register. */
1487 return cris_spec_regs[i].reg_size;
1488 }
1489 /* Special register not applicable to this CRIS version. */
1490 return 0;
1491 }
1492 else if (regno >= gdbarch_pc_regnum (gdbarch)
1493 && regno < gdbarch_num_regs (gdbarch))
1494 {
1495 /* This will apply to CRISv32 only where there are additional registers
1496 after the special registers (pseudo PC and support registers). */
1497 return 4;
1498 }
1499
1500
1501 return -1;
1502 }
1503
1504 /* Nonzero if regno should not be fetched from the target. This is the case
1505 for unimplemented (size 0) and non-existant registers. */
1506
1507 static int
1508 cris_cannot_fetch_register (struct gdbarch *gdbarch, int regno)
1509 {
1510 return ((regno < 0 || regno >= gdbarch_num_regs (gdbarch))
1511 || (cris_register_size (gdbarch, regno) == 0));
1512 }
1513
1514 /* Nonzero if regno should not be written to the target, for various
1515 reasons. */
1516
1517 static int
1518 cris_cannot_store_register (struct gdbarch *gdbarch, int regno)
1519 {
1520 /* There are three kinds of registers we refuse to write to.
1521 1. Those that not implemented.
1522 2. Those that are read-only (depends on the processor mode).
1523 3. Those registers to which a write has no effect. */
1524
1525 if (regno < 0
1526 || regno >= gdbarch_num_regs (gdbarch)
1527 || cris_register_size (gdbarch, regno) == 0)
1528 /* Not implemented. */
1529 return 1;
1530
1531 else if (regno == VR_REGNUM)
1532 /* Read-only. */
1533 return 1;
1534
1535 else if (regno == P0_REGNUM || regno == P4_REGNUM || regno == P8_REGNUM)
1536 /* Writing has no effect. */
1537 return 1;
1538
1539 /* IBR, BAR, BRP and IRP are read-only in user mode. Let the debug
1540 agent decide whether they are writable. */
1541
1542 return 0;
1543 }
1544
1545 /* Nonzero if regno should not be fetched from the target. This is the case
1546 for unimplemented (size 0) and non-existant registers. */
1547
1548 static int
1549 crisv32_cannot_fetch_register (struct gdbarch *gdbarch, int regno)
1550 {
1551 return ((regno < 0 || regno >= gdbarch_num_regs (gdbarch))
1552 || (cris_register_size (gdbarch, regno) == 0));
1553 }
1554
1555 /* Nonzero if regno should not be written to the target, for various
1556 reasons. */
1557
1558 static int
1559 crisv32_cannot_store_register (struct gdbarch *gdbarch, int regno)
1560 {
1561 /* There are three kinds of registers we refuse to write to.
1562 1. Those that not implemented.
1563 2. Those that are read-only (depends on the processor mode).
1564 3. Those registers to which a write has no effect. */
1565
1566 if (regno < 0
1567 || regno >= gdbarch_num_regs (gdbarch)
1568 || cris_register_size (gdbarch, regno) == 0)
1569 /* Not implemented. */
1570 return 1;
1571
1572 else if (regno == VR_REGNUM)
1573 /* Read-only. */
1574 return 1;
1575
1576 else if (regno == BZ_REGNUM || regno == WZ_REGNUM || regno == DZ_REGNUM)
1577 /* Writing has no effect. */
1578 return 1;
1579
1580 /* Many special registers are read-only in user mode. Let the debug
1581 agent decide whether they are writable. */
1582
1583 return 0;
1584 }
1585
1586 /* Return the GDB type (defined in gdbtypes.c) for the "standard" data type
1587 of data in register regno. */
1588
1589 static struct type *
1590 cris_register_type (struct gdbarch *gdbarch, int regno)
1591 {
1592 if (regno == gdbarch_pc_regnum (gdbarch))
1593 return builtin_type (gdbarch)->builtin_func_ptr;
1594 else if (regno == gdbarch_sp_regnum (gdbarch)
1595 || regno == CRIS_FP_REGNUM)
1596 return builtin_type (gdbarch)->builtin_data_ptr;
1597 else if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch))
1598 || (regno >= MOF_REGNUM && regno <= USP_REGNUM))
1599 /* Note: R8 taken care of previous clause. */
1600 return builtin_type (gdbarch)->builtin_uint32;
1601 else if (regno >= P4_REGNUM && regno <= CCR_REGNUM)
1602 return builtin_type (gdbarch)->builtin_uint16;
1603 else if (regno >= P0_REGNUM && regno <= VR_REGNUM)
1604 return builtin_type (gdbarch)->builtin_uint8;
1605 else
1606 /* Invalid (unimplemented) register. */
1607 return builtin_type (gdbarch)->builtin_int0;
1608 }
1609
1610 static struct type *
1611 crisv32_register_type (struct gdbarch *gdbarch, int regno)
1612 {
1613 if (regno == gdbarch_pc_regnum (gdbarch))
1614 return builtin_type (gdbarch)->builtin_func_ptr;
1615 else if (regno == gdbarch_sp_regnum (gdbarch)
1616 || regno == CRIS_FP_REGNUM)
1617 return builtin_type (gdbarch)->builtin_data_ptr;
1618 else if ((regno >= 0 && regno <= ACR_REGNUM)
1619 || (regno >= EXS_REGNUM && regno <= SPC_REGNUM)
1620 || (regno == PID_REGNUM)
1621 || (regno >= S0_REGNUM && regno <= S15_REGNUM))
1622 /* Note: R8 and SP taken care of by previous clause. */
1623 return builtin_type (gdbarch)->builtin_uint32;
1624 else if (regno == WZ_REGNUM)
1625 return builtin_type (gdbarch)->builtin_uint16;
1626 else if (regno == BZ_REGNUM || regno == VR_REGNUM || regno == SRS_REGNUM)
1627 return builtin_type (gdbarch)->builtin_uint8;
1628 else
1629 {
1630 /* Invalid (unimplemented) register. Should not happen as there are
1631 no unimplemented CRISv32 registers. */
1632 warning (_("crisv32_register_type: unknown regno %d"), regno);
1633 return builtin_type (gdbarch)->builtin_int0;
1634 }
1635 }
1636
1637 /* Stores a function return value of type type, where valbuf is the address
1638 of the value to be stored. */
1639
1640 /* In the CRIS ABI, R10 and R11 are used to store return values. */
1641
1642 static void
1643 cris_store_return_value (struct type *type, struct regcache *regcache,
1644 const gdb_byte *valbuf)
1645 {
1646 struct gdbarch *gdbarch = regcache->arch ();
1647 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1648 ULONGEST val;
1649 int len = TYPE_LENGTH (type);
1650
1651 if (len <= 4)
1652 {
1653 /* Put the return value in R10. */
1654 val = extract_unsigned_integer (valbuf, len, byte_order);
1655 regcache_cooked_write_unsigned (regcache, ARG1_REGNUM, val);
1656 }
1657 else if (len <= 8)
1658 {
1659 /* Put the return value in R10 and R11. */
1660 val = extract_unsigned_integer (valbuf, 4, byte_order);
1661 regcache_cooked_write_unsigned (regcache, ARG1_REGNUM, val);
1662 val = extract_unsigned_integer (valbuf + 4, len - 4, byte_order);
1663 regcache_cooked_write_unsigned (regcache, ARG2_REGNUM, val);
1664 }
1665 else
1666 error (_("cris_store_return_value: type length too large."));
1667 }
1668
1669 /* Return the name of register regno as a string. Return NULL for an
1670 invalid or unimplemented register. */
1671
1672 static const char *
1673 cris_special_register_name (struct gdbarch *gdbarch, int regno)
1674 {
1675 int spec_regno;
1676 int i;
1677
1678 /* Special register (R16 - R31). cris_spec_regs is zero-based.
1679 Adjust regno accordingly. */
1680 spec_regno = regno - NUM_GENREGS;
1681
1682 /* Assume nothing about the layout of the cris_spec_regs struct
1683 when searching. */
1684 for (i = 0; cris_spec_regs[i].name != NULL; i++)
1685 {
1686 if (cris_spec_regs[i].number == spec_regno
1687 && cris_spec_reg_applicable (gdbarch, cris_spec_regs[i]))
1688 /* Go with the first applicable register. */
1689 return cris_spec_regs[i].name;
1690 }
1691 /* Special register not applicable to this CRIS version. */
1692 return NULL;
1693 }
1694
1695 static const char *
1696 cris_register_name (struct gdbarch *gdbarch, int regno)
1697 {
1698 static const char *cris_genreg_names[] =
1699 { "r0", "r1", "r2", "r3", \
1700 "r4", "r5", "r6", "r7", \
1701 "r8", "r9", "r10", "r11", \
1702 "r12", "r13", "sp", "pc" };
1703
1704 if (regno >= 0 && regno < NUM_GENREGS)
1705 {
1706 /* General register. */
1707 return cris_genreg_names[regno];
1708 }
1709 else if (regno >= NUM_GENREGS && regno < gdbarch_num_regs (gdbarch))
1710 {
1711 return cris_special_register_name (gdbarch, regno);
1712 }
1713 else
1714 {
1715 /* Invalid register. */
1716 return NULL;
1717 }
1718 }
1719
1720 static const char *
1721 crisv32_register_name (struct gdbarch *gdbarch, int regno)
1722 {
1723 static const char *crisv32_genreg_names[] =
1724 { "r0", "r1", "r2", "r3", \
1725 "r4", "r5", "r6", "r7", \
1726 "r8", "r9", "r10", "r11", \
1727 "r12", "r13", "sp", "acr"
1728 };
1729
1730 static const char *crisv32_sreg_names[] =
1731 { "s0", "s1", "s2", "s3", \
1732 "s4", "s5", "s6", "s7", \
1733 "s8", "s9", "s10", "s11", \
1734 "s12", "s13", "s14", "s15"
1735 };
1736
1737 if (regno >= 0 && regno < NUM_GENREGS)
1738 {
1739 /* General register. */
1740 return crisv32_genreg_names[regno];
1741 }
1742 else if (regno >= NUM_GENREGS && regno < (NUM_GENREGS + NUM_SPECREGS))
1743 {
1744 return cris_special_register_name (gdbarch, regno);
1745 }
1746 else if (regno == gdbarch_pc_regnum (gdbarch))
1747 {
1748 return "pc";
1749 }
1750 else if (regno >= S0_REGNUM && regno <= S15_REGNUM)
1751 {
1752 return crisv32_sreg_names[regno - S0_REGNUM];
1753 }
1754 else
1755 {
1756 /* Invalid register. */
1757 return NULL;
1758 }
1759 }
1760
1761 /* Convert DWARF register number REG to the appropriate register
1762 number used by GDB. */
1763
1764 static int
1765 cris_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int reg)
1766 {
1767 /* We need to re-map a couple of registers (SRP is 16 in Dwarf-2 register
1768 numbering, MOF is 18).
1769 Adapted from gcc/config/cris/cris.h. */
1770 static int cris_dwarf_regmap[] = {
1771 0, 1, 2, 3,
1772 4, 5, 6, 7,
1773 8, 9, 10, 11,
1774 12, 13, 14, 15,
1775 27, -1, -1, -1,
1776 -1, -1, -1, 23,
1777 -1, -1, -1, 27,
1778 -1, -1, -1, -1
1779 };
1780 int regnum = -1;
1781
1782 if (reg >= 0 && reg < ARRAY_SIZE (cris_dwarf_regmap))
1783 regnum = cris_dwarf_regmap[reg];
1784
1785 return regnum;
1786 }
1787
1788 /* DWARF-2 frame support. */
1789
1790 static void
1791 cris_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
1792 struct dwarf2_frame_state_reg *reg,
1793 struct frame_info *this_frame)
1794 {
1795 /* The return address column. */
1796 if (regnum == gdbarch_pc_regnum (gdbarch))
1797 reg->how = DWARF2_FRAME_REG_RA;
1798
1799 /* The call frame address. */
1800 else if (regnum == gdbarch_sp_regnum (gdbarch))
1801 reg->how = DWARF2_FRAME_REG_CFA;
1802 }
1803
1804 /* Extract from an array regbuf containing the raw register state a function
1805 return value of type type, and copy that, in virtual format, into
1806 valbuf. */
1807
1808 /* In the CRIS ABI, R10 and R11 are used to store return values. */
1809
1810 static void
1811 cris_extract_return_value (struct type *type, struct regcache *regcache,
1812 gdb_byte *valbuf)
1813 {
1814 struct gdbarch *gdbarch = regcache->arch ();
1815 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1816 ULONGEST val;
1817 int len = TYPE_LENGTH (type);
1818
1819 if (len <= 4)
1820 {
1821 /* Get the return value from R10. */
1822 regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &val);
1823 store_unsigned_integer (valbuf, len, byte_order, val);
1824 }
1825 else if (len <= 8)
1826 {
1827 /* Get the return value from R10 and R11. */
1828 regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &val);
1829 store_unsigned_integer (valbuf, 4, byte_order, val);
1830 regcache_cooked_read_unsigned (regcache, ARG2_REGNUM, &val);
1831 store_unsigned_integer (valbuf + 4, len - 4, byte_order, val);
1832 }
1833 else
1834 error (_("cris_extract_return_value: type length too large"));
1835 }
1836
1837 /* Handle the CRIS return value convention. */
1838
1839 static enum return_value_convention
1840 cris_return_value (struct gdbarch *gdbarch, struct value *function,
1841 struct type *type, struct regcache *regcache,
1842 gdb_byte *readbuf, const gdb_byte *writebuf)
1843 {
1844 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
1845 || TYPE_CODE (type) == TYPE_CODE_UNION
1846 || TYPE_LENGTH (type) > 8)
1847 /* Structs, unions, and anything larger than 8 bytes (2 registers)
1848 goes on the stack. */
1849 return RETURN_VALUE_STRUCT_CONVENTION;
1850
1851 if (readbuf)
1852 cris_extract_return_value (type, regcache, readbuf);
1853 if (writebuf)
1854 cris_store_return_value (type, regcache, writebuf);
1855
1856 return RETURN_VALUE_REGISTER_CONVENTION;
1857 }
1858
1859 /* Calculates a value that measures how good inst_args constraints an
1860 instruction. It stems from cris_constraint, found in cris-dis.c. */
1861
1862 static int
1863 constraint (unsigned int insn, const char *inst_args,
1864 inst_env_type *inst_env)
1865 {
1866 int retval = 0;
1867 int tmp, i;
1868
1869 const gdb_byte *s = (const gdb_byte *) inst_args;
1870
1871 for (; *s; s++)
1872 switch (*s)
1873 {
1874 case 'm':
1875 if ((insn & 0x30) == 0x30)
1876 return -1;
1877 break;
1878
1879 case 'S':
1880 /* A prefix operand. */
1881 if (inst_env->prefix_found)
1882 break;
1883 else
1884 return -1;
1885
1886 case 'B':
1887 /* A "push" prefix. (This check was REMOVED by san 970921.) Check for
1888 valid "push" size. In case of special register, it may be != 4. */
1889 if (inst_env->prefix_found)
1890 break;
1891 else
1892 return -1;
1893
1894 case 'D':
1895 retval = (((insn >> 0xC) & 0xF) == (insn & 0xF));
1896 if (!retval)
1897 return -1;
1898 else
1899 retval += 4;
1900 break;
1901
1902 case 'P':
1903 tmp = (insn >> 0xC) & 0xF;
1904
1905 for (i = 0; cris_spec_regs[i].name != NULL; i++)
1906 {
1907 /* Since we match four bits, we will give a value of
1908 4 - 1 = 3 in a match. If there is a corresponding
1909 exact match of a special register in another pattern, it
1910 will get a value of 4, which will be higher. This should
1911 be correct in that an exact pattern would match better that
1912 a general pattern.
1913 Note that there is a reason for not returning zero; the
1914 pattern for "clear" is partly matched in the bit-pattern
1915 (the two lower bits must be zero), while the bit-pattern
1916 for a move from a special register is matched in the
1917 register constraint.
1918 This also means we will will have a race condition if
1919 there is a partly match in three bits in the bit pattern. */
1920 if (tmp == cris_spec_regs[i].number)
1921 {
1922 retval += 3;
1923 break;
1924 }
1925 }
1926
1927 if (cris_spec_regs[i].name == NULL)
1928 return -1;
1929 break;
1930 }
1931 return retval;
1932 }
1933
1934 /* Returns the number of bits set in the variable value. */
1935
1936 static int
1937 number_of_bits (unsigned int value)
1938 {
1939 int number_of_bits = 0;
1940
1941 while (value != 0)
1942 {
1943 number_of_bits += 1;
1944 value &= (value - 1);
1945 }
1946 return number_of_bits;
1947 }
1948
1949 /* Finds the address that should contain the single step breakpoint(s).
1950 It stems from code in cris-dis.c. */
1951
1952 static int
1953 find_cris_op (unsigned short insn, inst_env_type *inst_env)
1954 {
1955 int i;
1956 int max_level_of_match = -1;
1957 int max_matched = -1;
1958 int level_of_match;
1959
1960 for (i = 0; cris_opcodes[i].name != NULL; i++)
1961 {
1962 if (((cris_opcodes[i].match & insn) == cris_opcodes[i].match)
1963 && ((cris_opcodes[i].lose & insn) == 0)
1964 /* Only CRISv10 instructions, please. */
1965 && (cris_opcodes[i].applicable_version != cris_ver_v32p))
1966 {
1967 level_of_match = constraint (insn, cris_opcodes[i].args, inst_env);
1968 if (level_of_match >= 0)
1969 {
1970 level_of_match +=
1971 number_of_bits (cris_opcodes[i].match | cris_opcodes[i].lose);
1972 if (level_of_match > max_level_of_match)
1973 {
1974 max_matched = i;
1975 max_level_of_match = level_of_match;
1976 if (level_of_match == 16)
1977 {
1978 /* All bits matched, cannot find better. */
1979 break;
1980 }
1981 }
1982 }
1983 }
1984 }
1985 return max_matched;
1986 }
1987
1988 /* Attempts to find single-step breakpoints. Returns -1 on failure which is
1989 actually an internal error. */
1990
1991 static int
1992 find_step_target (struct regcache *regcache, inst_env_type *inst_env)
1993 {
1994 int i;
1995 int offset;
1996 unsigned short insn;
1997 struct gdbarch *gdbarch = regcache->arch ();
1998 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1999
2000 /* Create a local register image and set the initial state. */
2001 for (i = 0; i < NUM_GENREGS; i++)
2002 {
2003 inst_env->reg[i] =
2004 (unsigned long) regcache_raw_get_unsigned (regcache, i);
2005 }
2006 offset = NUM_GENREGS;
2007 for (i = 0; i < NUM_SPECREGS; i++)
2008 {
2009 inst_env->preg[i] =
2010 (unsigned long) regcache_raw_get_unsigned (regcache, offset + i);
2011 }
2012 inst_env->branch_found = 0;
2013 inst_env->slot_needed = 0;
2014 inst_env->delay_slot_pc_active = 0;
2015 inst_env->prefix_found = 0;
2016 inst_env->invalid = 0;
2017 inst_env->xflag_found = 0;
2018 inst_env->disable_interrupt = 0;
2019 inst_env->byte_order = byte_order;
2020
2021 /* Look for a step target. */
2022 do
2023 {
2024 /* Read an instruction from the client. */
2025 insn = read_memory_unsigned_integer
2026 (inst_env->reg[gdbarch_pc_regnum (gdbarch)], 2, byte_order);
2027
2028 /* If the instruction is not in a delay slot the new content of the
2029 PC is [PC] + 2. If the instruction is in a delay slot it is not
2030 that simple. Since a instruction in a delay slot cannot change
2031 the content of the PC, it does not matter what value PC will have.
2032 Just make sure it is a valid instruction. */
2033 if (!inst_env->delay_slot_pc_active)
2034 {
2035 inst_env->reg[gdbarch_pc_regnum (gdbarch)] += 2;
2036 }
2037 else
2038 {
2039 inst_env->delay_slot_pc_active = 0;
2040 inst_env->reg[gdbarch_pc_regnum (gdbarch)]
2041 = inst_env->delay_slot_pc;
2042 }
2043 /* Analyse the present instruction. */
2044 i = find_cris_op (insn, inst_env);
2045 if (i == -1)
2046 {
2047 inst_env->invalid = 1;
2048 }
2049 else
2050 {
2051 cris_gdb_func (gdbarch, cris_opcodes[i].op, insn, inst_env);
2052 }
2053 } while (!inst_env->invalid
2054 && (inst_env->prefix_found || inst_env->xflag_found
2055 || inst_env->slot_needed));
2056 return i;
2057 }
2058
2059 /* There is no hardware single-step support. The function find_step_target
2060 digs through the opcodes in order to find all possible targets.
2061 Either one ordinary target or two targets for branches may be found. */
2062
2063 static std::vector<CORE_ADDR>
2064 cris_software_single_step (struct regcache *regcache)
2065 {
2066 struct gdbarch *gdbarch = regcache->arch ();
2067 inst_env_type inst_env;
2068 std::vector<CORE_ADDR> next_pcs;
2069
2070 /* Analyse the present instruction environment and insert
2071 breakpoints. */
2072 int status = find_step_target (regcache, &inst_env);
2073 if (status == -1)
2074 {
2075 /* Could not find a target. Things are likely to go downhill
2076 from here. */
2077 warning (_("CRIS software single step could not find a step target."));
2078 }
2079 else
2080 {
2081 /* Insert at most two breakpoints. One for the next PC content
2082 and possibly another one for a branch, jump, etc. */
2083 CORE_ADDR next_pc
2084 = (CORE_ADDR) inst_env.reg[gdbarch_pc_regnum (gdbarch)];
2085
2086 next_pcs.push_back (next_pc);
2087 if (inst_env.branch_found
2088 && (CORE_ADDR) inst_env.branch_break_address != next_pc)
2089 {
2090 CORE_ADDR branch_target_address
2091 = (CORE_ADDR) inst_env.branch_break_address;
2092
2093 next_pcs.push_back (branch_target_address);
2094 }
2095 }
2096
2097 return next_pcs;
2098 }
2099
2100 /* Calculates the prefix value for quick offset addressing mode. */
2101
2102 static void
2103 quick_mode_bdap_prefix (unsigned short inst, inst_env_type *inst_env)
2104 {
2105 /* It's invalid to be in a delay slot. You can't have a prefix to this
2106 instruction (not 100% sure). */
2107 if (inst_env->slot_needed || inst_env->prefix_found)
2108 {
2109 inst_env->invalid = 1;
2110 return;
2111 }
2112
2113 inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)];
2114 inst_env->prefix_value += cris_get_bdap_quick_offset (inst);
2115
2116 /* A prefix doesn't change the xflag_found. But the rest of the flags
2117 need updating. */
2118 inst_env->slot_needed = 0;
2119 inst_env->prefix_found = 1;
2120 }
2121
2122 /* Updates the autoincrement register. The size of the increment is derived
2123 from the size of the operation. The PC is always kept aligned on even
2124 word addresses. */
2125
2126 static void
2127 process_autoincrement (int size, unsigned short inst, inst_env_type *inst_env)
2128 {
2129 if (size == INST_BYTE_SIZE)
2130 {
2131 inst_env->reg[cris_get_operand1 (inst)] += 1;
2132
2133 /* The PC must be word aligned, so increase the PC with one
2134 word even if the size is byte. */
2135 if (cris_get_operand1 (inst) == REG_PC)
2136 {
2137 inst_env->reg[REG_PC] += 1;
2138 }
2139 }
2140 else if (size == INST_WORD_SIZE)
2141 {
2142 inst_env->reg[cris_get_operand1 (inst)] += 2;
2143 }
2144 else if (size == INST_DWORD_SIZE)
2145 {
2146 inst_env->reg[cris_get_operand1 (inst)] += 4;
2147 }
2148 else
2149 {
2150 /* Invalid size. */
2151 inst_env->invalid = 1;
2152 }
2153 }
2154
2155 /* Just a forward declaration. */
2156
2157 static unsigned long get_data_from_address (unsigned short *inst,
2158 CORE_ADDR address,
2159 enum bfd_endian byte_order);
2160
2161 /* Calculates the prefix value for the general case of offset addressing
2162 mode. */
2163
2164 static void
2165 bdap_prefix (unsigned short inst, inst_env_type *inst_env)
2166 {
2167 /* It's invalid to be in a delay slot. */
2168 if (inst_env->slot_needed || inst_env->prefix_found)
2169 {
2170 inst_env->invalid = 1;
2171 return;
2172 }
2173
2174 /* The calculation of prefix_value used to be after process_autoincrement,
2175 but that fails for an instruction such as jsr [$r0+12] which is encoded
2176 as 5f0d 0c00 30b9 when compiled with -fpic. Since PC is operand1 it
2177 mustn't be incremented until we have read it and what it points at. */
2178 inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)];
2179
2180 /* The offset is an indirection of the contents of the operand1 register. */
2181 inst_env->prefix_value +=
2182 get_data_from_address (&inst, inst_env->reg[cris_get_operand1 (inst)],
2183 inst_env->byte_order);
2184
2185 if (cris_get_mode (inst) == AUTOINC_MODE)
2186 {
2187 process_autoincrement (cris_get_size (inst), inst, inst_env);
2188 }
2189
2190 /* A prefix doesn't change the xflag_found. But the rest of the flags
2191 need updating. */
2192 inst_env->slot_needed = 0;
2193 inst_env->prefix_found = 1;
2194 }
2195
2196 /* Calculates the prefix value for the index addressing mode. */
2197
2198 static void
2199 biap_prefix (unsigned short inst, inst_env_type *inst_env)
2200 {
2201 /* It's invalid to be in a delay slot. I can't see that it's possible to
2202 have a prefix to this instruction. So I will treat this as invalid. */
2203 if (inst_env->slot_needed || inst_env->prefix_found)
2204 {
2205 inst_env->invalid = 1;
2206 return;
2207 }
2208
2209 inst_env->prefix_value = inst_env->reg[cris_get_operand1 (inst)];
2210
2211 /* The offset is the operand2 value shifted the size of the instruction
2212 to the left. */
2213 inst_env->prefix_value +=
2214 inst_env->reg[cris_get_operand2 (inst)] << cris_get_size (inst);
2215
2216 /* If the PC is operand1 (base) the address used is the address after
2217 the main instruction, i.e. address + 2 (the PC is already compensated
2218 for the prefix operation). */
2219 if (cris_get_operand1 (inst) == REG_PC)
2220 {
2221 inst_env->prefix_value += 2;
2222 }
2223
2224 /* A prefix doesn't change the xflag_found. But the rest of the flags
2225 need updating. */
2226 inst_env->slot_needed = 0;
2227 inst_env->xflag_found = 0;
2228 inst_env->prefix_found = 1;
2229 }
2230
2231 /* Calculates the prefix value for the double indirect addressing mode. */
2232
2233 static void
2234 dip_prefix (unsigned short inst, inst_env_type *inst_env)
2235 {
2236
2237 CORE_ADDR address;
2238
2239 /* It's invalid to be in a delay slot. */
2240 if (inst_env->slot_needed || inst_env->prefix_found)
2241 {
2242 inst_env->invalid = 1;
2243 return;
2244 }
2245
2246 /* The prefix value is one dereference of the contents of the operand1
2247 register. */
2248 address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)];
2249 inst_env->prefix_value
2250 = read_memory_unsigned_integer (address, 4, inst_env->byte_order);
2251
2252 /* Check if the mode is autoincrement. */
2253 if (cris_get_mode (inst) == AUTOINC_MODE)
2254 {
2255 inst_env->reg[cris_get_operand1 (inst)] += 4;
2256 }
2257
2258 /* A prefix doesn't change the xflag_found. But the rest of the flags
2259 need updating. */
2260 inst_env->slot_needed = 0;
2261 inst_env->xflag_found = 0;
2262 inst_env->prefix_found = 1;
2263 }
2264
2265 /* Finds the destination for a branch with 8-bits offset. */
2266
2267 static void
2268 eight_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env)
2269 {
2270
2271 short offset;
2272
2273 /* If we have a prefix or are in a delay slot it's bad. */
2274 if (inst_env->slot_needed || inst_env->prefix_found)
2275 {
2276 inst_env->invalid = 1;
2277 return;
2278 }
2279
2280 /* We have a branch, find out where the branch will land. */
2281 offset = cris_get_branch_short_offset (inst);
2282
2283 /* Check if the offset is signed. */
2284 if (offset & BRANCH_SIGNED_SHORT_OFFSET_MASK)
2285 {
2286 offset |= 0xFF00;
2287 }
2288
2289 /* The offset ends with the sign bit, set it to zero. The address
2290 should always be word aligned. */
2291 offset &= ~BRANCH_SIGNED_SHORT_OFFSET_MASK;
2292
2293 inst_env->branch_found = 1;
2294 inst_env->branch_break_address = inst_env->reg[REG_PC] + offset;
2295
2296 inst_env->slot_needed = 1;
2297 inst_env->prefix_found = 0;
2298 inst_env->xflag_found = 0;
2299 inst_env->disable_interrupt = 1;
2300 }
2301
2302 /* Finds the destination for a branch with 16-bits offset. */
2303
2304 static void
2305 sixteen_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env)
2306 {
2307 short offset;
2308
2309 /* If we have a prefix or is in a delay slot it's bad. */
2310 if (inst_env->slot_needed || inst_env->prefix_found)
2311 {
2312 inst_env->invalid = 1;
2313 return;
2314 }
2315
2316 /* We have a branch, find out the offset for the branch. */
2317 offset = read_memory_integer (inst_env->reg[REG_PC], 2,
2318 inst_env->byte_order);
2319
2320 /* The instruction is one word longer than normal, so add one word
2321 to the PC. */
2322 inst_env->reg[REG_PC] += 2;
2323
2324 inst_env->branch_found = 1;
2325 inst_env->branch_break_address = inst_env->reg[REG_PC] + offset;
2326
2327
2328 inst_env->slot_needed = 1;
2329 inst_env->prefix_found = 0;
2330 inst_env->xflag_found = 0;
2331 inst_env->disable_interrupt = 1;
2332 }
2333
2334 /* Handles the ABS instruction. */
2335
2336 static void
2337 abs_op (unsigned short inst, inst_env_type *inst_env)
2338 {
2339
2340 long value;
2341
2342 /* ABS can't have a prefix, so it's bad if it does. */
2343 if (inst_env->prefix_found)
2344 {
2345 inst_env->invalid = 1;
2346 return;
2347 }
2348
2349 /* Check if the operation affects the PC. */
2350 if (cris_get_operand2 (inst) == REG_PC)
2351 {
2352
2353 /* It's invalid to change to the PC if we are in a delay slot. */
2354 if (inst_env->slot_needed)
2355 {
2356 inst_env->invalid = 1;
2357 return;
2358 }
2359
2360 value = (long) inst_env->reg[REG_PC];
2361
2362 /* The value of abs (SIGNED_DWORD_MASK) is SIGNED_DWORD_MASK. */
2363 if (value != SIGNED_DWORD_MASK)
2364 {
2365 value = -value;
2366 inst_env->reg[REG_PC] = (long) value;
2367 }
2368 }
2369
2370 inst_env->slot_needed = 0;
2371 inst_env->prefix_found = 0;
2372 inst_env->xflag_found = 0;
2373 inst_env->disable_interrupt = 0;
2374 }
2375
2376 /* Handles the ADDI instruction. */
2377
2378 static void
2379 addi_op (unsigned short inst, inst_env_type *inst_env)
2380 {
2381 /* It's invalid to have the PC as base register. And ADDI can't have
2382 a prefix. */
2383 if (inst_env->prefix_found || (cris_get_operand1 (inst) == REG_PC))
2384 {
2385 inst_env->invalid = 1;
2386 return;
2387 }
2388
2389 inst_env->slot_needed = 0;
2390 inst_env->prefix_found = 0;
2391 inst_env->xflag_found = 0;
2392 inst_env->disable_interrupt = 0;
2393 }
2394
2395 /* Handles the ASR instruction. */
2396
2397 static void
2398 asr_op (unsigned short inst, inst_env_type *inst_env)
2399 {
2400 int shift_steps;
2401 unsigned long value;
2402 unsigned long signed_extend_mask = 0;
2403
2404 /* ASR can't have a prefix, so check that it doesn't. */
2405 if (inst_env->prefix_found)
2406 {
2407 inst_env->invalid = 1;
2408 return;
2409 }
2410
2411 /* Check if the PC is the target register. */
2412 if (cris_get_operand2 (inst) == REG_PC)
2413 {
2414 /* It's invalid to change the PC in a delay slot. */
2415 if (inst_env->slot_needed)
2416 {
2417 inst_env->invalid = 1;
2418 return;
2419 }
2420 /* Get the number of bits to shift. */
2421 shift_steps
2422 = cris_get_asr_shift_steps (inst_env->reg[cris_get_operand1 (inst)]);
2423 value = inst_env->reg[REG_PC];
2424
2425 /* Find out how many bits the operation should apply to. */
2426 if (cris_get_size (inst) == INST_BYTE_SIZE)
2427 {
2428 if (value & SIGNED_BYTE_MASK)
2429 {
2430 signed_extend_mask = 0xFF;
2431 signed_extend_mask = signed_extend_mask >> shift_steps;
2432 signed_extend_mask = ~signed_extend_mask;
2433 }
2434 value = value >> shift_steps;
2435 value |= signed_extend_mask;
2436 value &= 0xFF;
2437 inst_env->reg[REG_PC] &= 0xFFFFFF00;
2438 inst_env->reg[REG_PC] |= value;
2439 }
2440 else if (cris_get_size (inst) == INST_WORD_SIZE)
2441 {
2442 if (value & SIGNED_WORD_MASK)
2443 {
2444 signed_extend_mask = 0xFFFF;
2445 signed_extend_mask = signed_extend_mask >> shift_steps;
2446 signed_extend_mask = ~signed_extend_mask;
2447 }
2448 value = value >> shift_steps;
2449 value |= signed_extend_mask;
2450 value &= 0xFFFF;
2451 inst_env->reg[REG_PC] &= 0xFFFF0000;
2452 inst_env->reg[REG_PC] |= value;
2453 }
2454 else if (cris_get_size (inst) == INST_DWORD_SIZE)
2455 {
2456 if (value & SIGNED_DWORD_MASK)
2457 {
2458 signed_extend_mask = 0xFFFFFFFF;
2459 signed_extend_mask = signed_extend_mask >> shift_steps;
2460 signed_extend_mask = ~signed_extend_mask;
2461 }
2462 value = value >> shift_steps;
2463 value |= signed_extend_mask;
2464 inst_env->reg[REG_PC] = value;
2465 }
2466 }
2467 inst_env->slot_needed = 0;
2468 inst_env->prefix_found = 0;
2469 inst_env->xflag_found = 0;
2470 inst_env->disable_interrupt = 0;
2471 }
2472
2473 /* Handles the ASRQ instruction. */
2474
2475 static void
2476 asrq_op (unsigned short inst, inst_env_type *inst_env)
2477 {
2478
2479 int shift_steps;
2480 unsigned long value;
2481 unsigned long signed_extend_mask = 0;
2482
2483 /* ASRQ can't have a prefix, so check that it doesn't. */
2484 if (inst_env->prefix_found)
2485 {
2486 inst_env->invalid = 1;
2487 return;
2488 }
2489
2490 /* Check if the PC is the target register. */
2491 if (cris_get_operand2 (inst) == REG_PC)
2492 {
2493
2494 /* It's invalid to change the PC in a delay slot. */
2495 if (inst_env->slot_needed)
2496 {
2497 inst_env->invalid = 1;
2498 return;
2499 }
2500 /* The shift size is given as a 5 bit quick value, i.e. we don't
2501 want the sign bit of the quick value. */
2502 shift_steps = cris_get_asr_shift_steps (inst);
2503 value = inst_env->reg[REG_PC];
2504 if (value & SIGNED_DWORD_MASK)
2505 {
2506 signed_extend_mask = 0xFFFFFFFF;
2507 signed_extend_mask = signed_extend_mask >> shift_steps;
2508 signed_extend_mask = ~signed_extend_mask;
2509 }
2510 value = value >> shift_steps;
2511 value |= signed_extend_mask;
2512 inst_env->reg[REG_PC] = value;
2513 }
2514 inst_env->slot_needed = 0;
2515 inst_env->prefix_found = 0;
2516 inst_env->xflag_found = 0;
2517 inst_env->disable_interrupt = 0;
2518 }
2519
2520 /* Handles the AX, EI and SETF instruction. */
2521
2522 static void
2523 ax_ei_setf_op (unsigned short inst, inst_env_type *inst_env)
2524 {
2525 if (inst_env->prefix_found)
2526 {
2527 inst_env->invalid = 1;
2528 return;
2529 }
2530 /* Check if the instruction is setting the X flag. */
2531 if (cris_is_xflag_bit_on (inst))
2532 {
2533 inst_env->xflag_found = 1;
2534 }
2535 else
2536 {
2537 inst_env->xflag_found = 0;
2538 }
2539 inst_env->slot_needed = 0;
2540 inst_env->prefix_found = 0;
2541 inst_env->disable_interrupt = 1;
2542 }
2543
2544 /* Checks if the instruction is in assign mode. If so, it updates the assign
2545 register. Note that check_assign assumes that the caller has checked that
2546 there is a prefix to this instruction. The mode check depends on this. */
2547
2548 static void
2549 check_assign (unsigned short inst, inst_env_type *inst_env)
2550 {
2551 /* Check if it's an assign addressing mode. */
2552 if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
2553 {
2554 /* Assign the prefix value to operand 1. */
2555 inst_env->reg[cris_get_operand1 (inst)] = inst_env->prefix_value;
2556 }
2557 }
2558
2559 /* Handles the 2-operand BOUND instruction. */
2560
2561 static void
2562 two_operand_bound_op (unsigned short inst, inst_env_type *inst_env)
2563 {
2564 /* It's invalid to have the PC as the index operand. */
2565 if (cris_get_operand2 (inst) == REG_PC)
2566 {
2567 inst_env->invalid = 1;
2568 return;
2569 }
2570 /* Check if we have a prefix. */
2571 if (inst_env->prefix_found)
2572 {
2573 check_assign (inst, inst_env);
2574 }
2575 /* Check if this is an autoincrement mode. */
2576 else if (cris_get_mode (inst) == AUTOINC_MODE)
2577 {
2578 /* It's invalid to change the PC in a delay slot. */
2579 if (inst_env->slot_needed)
2580 {
2581 inst_env->invalid = 1;
2582 return;
2583 }
2584 process_autoincrement (cris_get_size (inst), inst, inst_env);
2585 }
2586 inst_env->slot_needed = 0;
2587 inst_env->prefix_found = 0;
2588 inst_env->xflag_found = 0;
2589 inst_env->disable_interrupt = 0;
2590 }
2591
2592 /* Handles the 3-operand BOUND instruction. */
2593
2594 static void
2595 three_operand_bound_op (unsigned short inst, inst_env_type *inst_env)
2596 {
2597 /* It's an error if we haven't got a prefix. And it's also an error
2598 if the PC is the destination register. */
2599 if ((!inst_env->prefix_found) || (cris_get_operand1 (inst) == REG_PC))
2600 {
2601 inst_env->invalid = 1;
2602 return;
2603 }
2604 inst_env->slot_needed = 0;
2605 inst_env->prefix_found = 0;
2606 inst_env->xflag_found = 0;
2607 inst_env->disable_interrupt = 0;
2608 }
2609
2610 /* Clears the status flags in inst_env. */
2611
2612 static void
2613 btst_nop_op (unsigned short inst, inst_env_type *inst_env)
2614 {
2615 /* It's an error if we have got a prefix. */
2616 if (inst_env->prefix_found)
2617 {
2618 inst_env->invalid = 1;
2619 return;
2620 }
2621
2622 inst_env->slot_needed = 0;
2623 inst_env->prefix_found = 0;
2624 inst_env->xflag_found = 0;
2625 inst_env->disable_interrupt = 0;
2626 }
2627
2628 /* Clears the status flags in inst_env. */
2629
2630 static void
2631 clearf_di_op (unsigned short inst, inst_env_type *inst_env)
2632 {
2633 /* It's an error if we have got a prefix. */
2634 if (inst_env->prefix_found)
2635 {
2636 inst_env->invalid = 1;
2637 return;
2638 }
2639
2640 inst_env->slot_needed = 0;
2641 inst_env->prefix_found = 0;
2642 inst_env->xflag_found = 0;
2643 inst_env->disable_interrupt = 1;
2644 }
2645
2646 /* Handles the CLEAR instruction if it's in register mode. */
2647
2648 static void
2649 reg_mode_clear_op (unsigned short inst, inst_env_type *inst_env)
2650 {
2651 /* Check if the target is the PC. */
2652 if (cris_get_operand2 (inst) == REG_PC)
2653 {
2654 /* The instruction will clear the instruction's size bits. */
2655 int clear_size = cris_get_clear_size (inst);
2656 if (clear_size == INST_BYTE_SIZE)
2657 {
2658 inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFFFF00;
2659 }
2660 if (clear_size == INST_WORD_SIZE)
2661 {
2662 inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFF0000;
2663 }
2664 if (clear_size == INST_DWORD_SIZE)
2665 {
2666 inst_env->delay_slot_pc = 0x0;
2667 }
2668 /* The jump will be delayed with one delay slot. So we need a delay
2669 slot. */
2670 inst_env->slot_needed = 1;
2671 inst_env->delay_slot_pc_active = 1;
2672 }
2673 else
2674 {
2675 /* The PC will not change => no delay slot. */
2676 inst_env->slot_needed = 0;
2677 }
2678 inst_env->prefix_found = 0;
2679 inst_env->xflag_found = 0;
2680 inst_env->disable_interrupt = 0;
2681 }
2682
2683 /* Handles the TEST instruction if it's in register mode. */
2684
2685 static void
2686 reg_mode_test_op (unsigned short inst, inst_env_type *inst_env)
2687 {
2688 /* It's an error if we have got a prefix. */
2689 if (inst_env->prefix_found)
2690 {
2691 inst_env->invalid = 1;
2692 return;
2693 }
2694 inst_env->slot_needed = 0;
2695 inst_env->prefix_found = 0;
2696 inst_env->xflag_found = 0;
2697 inst_env->disable_interrupt = 0;
2698
2699 }
2700
2701 /* Handles the CLEAR and TEST instruction if the instruction isn't
2702 in register mode. */
2703
2704 static void
2705 none_reg_mode_clear_test_op (unsigned short inst, inst_env_type *inst_env)
2706 {
2707 /* Check if we are in a prefix mode. */
2708 if (inst_env->prefix_found)
2709 {
2710 /* The only way the PC can change is if this instruction is in
2711 assign addressing mode. */
2712 check_assign (inst, inst_env);
2713 }
2714 /* Indirect mode can't change the PC so just check if the mode is
2715 autoincrement. */
2716 else if (cris_get_mode (inst) == AUTOINC_MODE)
2717 {
2718 process_autoincrement (cris_get_size (inst), inst, inst_env);
2719 }
2720 inst_env->slot_needed = 0;
2721 inst_env->prefix_found = 0;
2722 inst_env->xflag_found = 0;
2723 inst_env->disable_interrupt = 0;
2724 }
2725
2726 /* Checks that the PC isn't the destination register or the instructions has
2727 a prefix. */
2728
2729 static void
2730 dstep_logshift_mstep_neg_not_op (unsigned short inst, inst_env_type *inst_env)
2731 {
2732 /* It's invalid to have the PC as the destination. The instruction can't
2733 have a prefix. */
2734 if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found)
2735 {
2736 inst_env->invalid = 1;
2737 return;
2738 }
2739
2740 inst_env->slot_needed = 0;
2741 inst_env->prefix_found = 0;
2742 inst_env->xflag_found = 0;
2743 inst_env->disable_interrupt = 0;
2744 }
2745
2746 /* Checks that the instruction doesn't have a prefix. */
2747
2748 static void
2749 break_op (unsigned short inst, inst_env_type *inst_env)
2750 {
2751 /* The instruction can't have a prefix. */
2752 if (inst_env->prefix_found)
2753 {
2754 inst_env->invalid = 1;
2755 return;
2756 }
2757
2758 inst_env->slot_needed = 0;
2759 inst_env->prefix_found = 0;
2760 inst_env->xflag_found = 0;
2761 inst_env->disable_interrupt = 1;
2762 }
2763
2764 /* Checks that the PC isn't the destination register and that the instruction
2765 doesn't have a prefix. */
2766
2767 static void
2768 scc_op (unsigned short inst, inst_env_type *inst_env)
2769 {
2770 /* It's invalid to have the PC as the destination. The instruction can't
2771 have a prefix. */
2772 if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found)
2773 {
2774 inst_env->invalid = 1;
2775 return;
2776 }
2777
2778 inst_env->slot_needed = 0;
2779 inst_env->prefix_found = 0;
2780 inst_env->xflag_found = 0;
2781 inst_env->disable_interrupt = 1;
2782 }
2783
2784 /* Handles the register mode JUMP instruction. */
2785
2786 static void
2787 reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env)
2788 {
2789 /* It's invalid to do a JUMP in a delay slot. The mode is register, so
2790 you can't have a prefix. */
2791 if ((inst_env->slot_needed) || (inst_env->prefix_found))
2792 {
2793 inst_env->invalid = 1;
2794 return;
2795 }
2796
2797 /* Just change the PC. */
2798 inst_env->reg[REG_PC] = inst_env->reg[cris_get_operand1 (inst)];
2799 inst_env->slot_needed = 0;
2800 inst_env->prefix_found = 0;
2801 inst_env->xflag_found = 0;
2802 inst_env->disable_interrupt = 1;
2803 }
2804
2805 /* Handles the JUMP instruction for all modes except register. */
2806
2807 static void
2808 none_reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env)
2809 {
2810 unsigned long newpc;
2811 CORE_ADDR address;
2812
2813 /* It's invalid to do a JUMP in a delay slot. */
2814 if (inst_env->slot_needed)
2815 {
2816 inst_env->invalid = 1;
2817 }
2818 else
2819 {
2820 /* Check if we have a prefix. */
2821 if (inst_env->prefix_found)
2822 {
2823 check_assign (inst, inst_env);
2824
2825 /* Get the new value for the PC. */
2826 newpc =
2827 read_memory_unsigned_integer ((CORE_ADDR) inst_env->prefix_value,
2828 4, inst_env->byte_order);
2829 }
2830 else
2831 {
2832 /* Get the new value for the PC. */
2833 address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)];
2834 newpc = read_memory_unsigned_integer (address,
2835 4, inst_env->byte_order);
2836
2837 /* Check if we should increment a register. */
2838 if (cris_get_mode (inst) == AUTOINC_MODE)
2839 {
2840 inst_env->reg[cris_get_operand1 (inst)] += 4;
2841 }
2842 }
2843 inst_env->reg[REG_PC] = newpc;
2844 }
2845 inst_env->slot_needed = 0;
2846 inst_env->prefix_found = 0;
2847 inst_env->xflag_found = 0;
2848 inst_env->disable_interrupt = 1;
2849 }
2850
2851 /* Handles moves to special registers (aka P-register) for all modes. */
2852
2853 static void
2854 move_to_preg_op (struct gdbarch *gdbarch, unsigned short inst,
2855 inst_env_type *inst_env)
2856 {
2857 if (inst_env->prefix_found)
2858 {
2859 /* The instruction has a prefix that means we are only interested if
2860 the instruction is in assign mode. */
2861 if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
2862 {
2863 /* The prefix handles the problem if we are in a delay slot. */
2864 if (cris_get_operand1 (inst) == REG_PC)
2865 {
2866 /* Just take care of the assign. */
2867 check_assign (inst, inst_env);
2868 }
2869 }
2870 }
2871 else if (cris_get_mode (inst) == AUTOINC_MODE)
2872 {
2873 /* The instruction doesn't have a prefix, the only case left that we
2874 are interested in is the autoincrement mode. */
2875 if (cris_get_operand1 (inst) == REG_PC)
2876 {
2877 /* If the PC is to be incremented it's invalid to be in a
2878 delay slot. */
2879 if (inst_env->slot_needed)
2880 {
2881 inst_env->invalid = 1;
2882 return;
2883 }
2884
2885 /* The increment depends on the size of the special register. */
2886 if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 1)
2887 {
2888 process_autoincrement (INST_BYTE_SIZE, inst, inst_env);
2889 }
2890 else if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 2)
2891 {
2892 process_autoincrement (INST_WORD_SIZE, inst, inst_env);
2893 }
2894 else
2895 {
2896 process_autoincrement (INST_DWORD_SIZE, inst, inst_env);
2897 }
2898 }
2899 }
2900 inst_env->slot_needed = 0;
2901 inst_env->prefix_found = 0;
2902 inst_env->xflag_found = 0;
2903 inst_env->disable_interrupt = 1;
2904 }
2905
2906 /* Handles moves from special registers (aka P-register) for all modes
2907 except register. */
2908
2909 static void
2910 none_reg_mode_move_from_preg_op (struct gdbarch *gdbarch, unsigned short inst,
2911 inst_env_type *inst_env)
2912 {
2913 if (inst_env->prefix_found)
2914 {
2915 /* The instruction has a prefix that means we are only interested if
2916 the instruction is in assign mode. */
2917 if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
2918 {
2919 /* The prefix handles the problem if we are in a delay slot. */
2920 if (cris_get_operand1 (inst) == REG_PC)
2921 {
2922 /* Just take care of the assign. */
2923 check_assign (inst, inst_env);
2924 }
2925 }
2926 }
2927 /* The instruction doesn't have a prefix, the only case left that we
2928 are interested in is the autoincrement mode. */
2929 else if (cris_get_mode (inst) == AUTOINC_MODE)
2930 {
2931 if (cris_get_operand1 (inst) == REG_PC)
2932 {
2933 /* If the PC is to be incremented it's invalid to be in a
2934 delay slot. */
2935 if (inst_env->slot_needed)
2936 {
2937 inst_env->invalid = 1;
2938 return;
2939 }
2940
2941 /* The increment depends on the size of the special register. */
2942 if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 1)
2943 {
2944 process_autoincrement (INST_BYTE_SIZE, inst, inst_env);
2945 }
2946 else if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 2)
2947 {
2948 process_autoincrement (INST_WORD_SIZE, inst, inst_env);
2949 }
2950 else
2951 {
2952 process_autoincrement (INST_DWORD_SIZE, inst, inst_env);
2953 }
2954 }
2955 }
2956 inst_env->slot_needed = 0;
2957 inst_env->prefix_found = 0;
2958 inst_env->xflag_found = 0;
2959 inst_env->disable_interrupt = 1;
2960 }
2961
2962 /* Handles moves from special registers (aka P-register) when the mode
2963 is register. */
2964
2965 static void
2966 reg_mode_move_from_preg_op (unsigned short inst, inst_env_type *inst_env)
2967 {
2968 /* Register mode move from special register can't have a prefix. */
2969 if (inst_env->prefix_found)
2970 {
2971 inst_env->invalid = 1;
2972 return;
2973 }
2974
2975 if (cris_get_operand1 (inst) == REG_PC)
2976 {
2977 /* It's invalid to change the PC in a delay slot. */
2978 if (inst_env->slot_needed)
2979 {
2980 inst_env->invalid = 1;
2981 return;
2982 }
2983 /* The destination is the PC, the jump will have a delay slot. */
2984 inst_env->delay_slot_pc = inst_env->preg[cris_get_operand2 (inst)];
2985 inst_env->slot_needed = 1;
2986 inst_env->delay_slot_pc_active = 1;
2987 }
2988 else
2989 {
2990 /* If the destination isn't PC, there will be no jump. */
2991 inst_env->slot_needed = 0;
2992 }
2993 inst_env->prefix_found = 0;
2994 inst_env->xflag_found = 0;
2995 inst_env->disable_interrupt = 1;
2996 }
2997
2998 /* Handles the MOVEM from memory to general register instruction. */
2999
3000 static void
3001 move_mem_to_reg_movem_op (unsigned short inst, inst_env_type *inst_env)
3002 {
3003 if (inst_env->prefix_found)
3004 {
3005 /* The prefix handles the problem if we are in a delay slot. Is the
3006 MOVEM instruction going to change the PC? */
3007 if (cris_get_operand2 (inst) >= REG_PC)
3008 {
3009 inst_env->reg[REG_PC] =
3010 read_memory_unsigned_integer (inst_env->prefix_value,
3011 4, inst_env->byte_order);
3012 }
3013 /* The assign value is the value after the increment. Normally, the
3014 assign value is the value before the increment. */
3015 if ((cris_get_operand1 (inst) == REG_PC)
3016 && (cris_get_mode (inst) == PREFIX_ASSIGN_MODE))
3017 {
3018 inst_env->reg[REG_PC] = inst_env->prefix_value;
3019 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
3020 }
3021 }
3022 else
3023 {
3024 /* Is the MOVEM instruction going to change the PC? */
3025 if (cris_get_operand2 (inst) == REG_PC)
3026 {
3027 /* It's invalid to change the PC in a delay slot. */
3028 if (inst_env->slot_needed)
3029 {
3030 inst_env->invalid = 1;
3031 return;
3032 }
3033 inst_env->reg[REG_PC] =
3034 read_memory_unsigned_integer (inst_env->reg[cris_get_operand1 (inst)],
3035 4, inst_env->byte_order);
3036 }
3037 /* The increment is not depending on the size, instead it's depending
3038 on the number of registers loaded from memory. */
3039 if ((cris_get_operand1 (inst) == REG_PC)
3040 && (cris_get_mode (inst) == AUTOINC_MODE))
3041 {
3042 /* It's invalid to change the PC in a delay slot. */
3043 if (inst_env->slot_needed)
3044 {
3045 inst_env->invalid = 1;
3046 return;
3047 }
3048 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
3049 }
3050 }
3051 inst_env->slot_needed = 0;
3052 inst_env->prefix_found = 0;
3053 inst_env->xflag_found = 0;
3054 inst_env->disable_interrupt = 0;
3055 }
3056
3057 /* Handles the MOVEM to memory from general register instruction. */
3058
3059 static void
3060 move_reg_to_mem_movem_op (unsigned short inst, inst_env_type *inst_env)
3061 {
3062 if (inst_env->prefix_found)
3063 {
3064 /* The assign value is the value after the increment. Normally, the
3065 assign value is the value before the increment. */
3066 if ((cris_get_operand1 (inst) == REG_PC)
3067 && (cris_get_mode (inst) == PREFIX_ASSIGN_MODE))
3068 {
3069 /* The prefix handles the problem if we are in a delay slot. */
3070 inst_env->reg[REG_PC] = inst_env->prefix_value;
3071 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
3072 }
3073 }
3074 else
3075 {
3076 /* The increment is not depending on the size, instead it's depending
3077 on the number of registers loaded to memory. */
3078 if ((cris_get_operand1 (inst) == REG_PC)
3079 && (cris_get_mode (inst) == AUTOINC_MODE))
3080 {
3081 /* It's invalid to change the PC in a delay slot. */
3082 if (inst_env->slot_needed)
3083 {
3084 inst_env->invalid = 1;
3085 return;
3086 }
3087 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
3088 }
3089 }
3090 inst_env->slot_needed = 0;
3091 inst_env->prefix_found = 0;
3092 inst_env->xflag_found = 0;
3093 inst_env->disable_interrupt = 0;
3094 }
3095
3096 /* Handles the intructions that's not yet implemented, by setting
3097 inst_env->invalid to true. */
3098
3099 static void
3100 not_implemented_op (unsigned short inst, inst_env_type *inst_env)
3101 {
3102 inst_env->invalid = 1;
3103 }
3104
3105 /* Handles the XOR instruction. */
3106
3107 static void
3108 xor_op (unsigned short inst, inst_env_type *inst_env)
3109 {
3110 /* XOR can't have a prefix. */
3111 if (inst_env->prefix_found)
3112 {
3113 inst_env->invalid = 1;
3114 return;
3115 }
3116
3117 /* Check if the PC is the target. */
3118 if (cris_get_operand2 (inst) == REG_PC)
3119 {
3120 /* It's invalid to change the PC in a delay slot. */
3121 if (inst_env->slot_needed)
3122 {
3123 inst_env->invalid = 1;
3124 return;
3125 }
3126 inst_env->reg[REG_PC] ^= inst_env->reg[cris_get_operand1 (inst)];
3127 }
3128 inst_env->slot_needed = 0;
3129 inst_env->prefix_found = 0;
3130 inst_env->xflag_found = 0;
3131 inst_env->disable_interrupt = 0;
3132 }
3133
3134 /* Handles the MULS instruction. */
3135
3136 static void
3137 muls_op (unsigned short inst, inst_env_type *inst_env)
3138 {
3139 /* MULS/U can't have a prefix. */
3140 if (inst_env->prefix_found)
3141 {
3142 inst_env->invalid = 1;
3143 return;
3144 }
3145
3146 /* Consider it invalid if the PC is the target. */
3147 if (cris_get_operand2 (inst) == REG_PC)
3148 {
3149 inst_env->invalid = 1;
3150 return;
3151 }
3152 inst_env->slot_needed = 0;
3153 inst_env->prefix_found = 0;
3154 inst_env->xflag_found = 0;
3155 inst_env->disable_interrupt = 0;
3156 }
3157
3158 /* Handles the MULU instruction. */
3159
3160 static void
3161 mulu_op (unsigned short inst, inst_env_type *inst_env)
3162 {
3163 /* MULS/U can't have a prefix. */
3164 if (inst_env->prefix_found)
3165 {
3166 inst_env->invalid = 1;
3167 return;
3168 }
3169
3170 /* Consider it invalid if the PC is the target. */
3171 if (cris_get_operand2 (inst) == REG_PC)
3172 {
3173 inst_env->invalid = 1;
3174 return;
3175 }
3176 inst_env->slot_needed = 0;
3177 inst_env->prefix_found = 0;
3178 inst_env->xflag_found = 0;
3179 inst_env->disable_interrupt = 0;
3180 }
3181
3182 /* Calculate the result of the instruction for ADD, SUB, CMP AND, OR and MOVE.
3183 The MOVE instruction is the move from source to register. */
3184
3185 static void
3186 add_sub_cmp_and_or_move_action (unsigned short inst, inst_env_type *inst_env,
3187 unsigned long source1, unsigned long source2)
3188 {
3189 unsigned long pc_mask;
3190 unsigned long operation_mask;
3191
3192 /* Find out how many bits the operation should apply to. */
3193 if (cris_get_size (inst) == INST_BYTE_SIZE)
3194 {
3195 pc_mask = 0xFFFFFF00;
3196 operation_mask = 0xFF;
3197 }
3198 else if (cris_get_size (inst) == INST_WORD_SIZE)
3199 {
3200 pc_mask = 0xFFFF0000;
3201 operation_mask = 0xFFFF;
3202 }
3203 else if (cris_get_size (inst) == INST_DWORD_SIZE)
3204 {
3205 pc_mask = 0x0;
3206 operation_mask = 0xFFFFFFFF;
3207 }
3208 else
3209 {
3210 /* The size is out of range. */
3211 inst_env->invalid = 1;
3212 return;
3213 }
3214
3215 /* The instruction just works on uw_operation_mask bits. */
3216 source2 &= operation_mask;
3217 source1 &= operation_mask;
3218
3219 /* Now calculate the result. The opcode's 3 first bits separates
3220 the different actions. */
3221 switch (cris_get_opcode (inst) & 7)
3222 {
3223 case 0: /* add */
3224 source1 += source2;
3225 break;
3226
3227 case 1: /* move */
3228 source1 = source2;
3229 break;
3230
3231 case 2: /* subtract */
3232 source1 -= source2;
3233 break;
3234
3235 case 3: /* compare */
3236 break;
3237
3238 case 4: /* and */
3239 source1 &= source2;
3240 break;
3241
3242 case 5: /* or */
3243 source1 |= source2;
3244 break;
3245
3246 default:
3247 inst_env->invalid = 1;
3248 return;
3249
3250 break;
3251 }
3252
3253 /* Make sure that the result doesn't contain more than the instruction
3254 size bits. */
3255 source2 &= operation_mask;
3256
3257 /* Calculate the new breakpoint address. */
3258 inst_env->reg[REG_PC] &= pc_mask;
3259 inst_env->reg[REG_PC] |= source1;
3260
3261 }
3262
3263 /* Extends the value from either byte or word size to a dword. If the mode
3264 is zero extend then the value is extended with zero. If instead the mode
3265 is signed extend the sign bit of the value is taken into consideration. */
3266
3267 static unsigned long
3268 do_sign_or_zero_extend (unsigned long value, unsigned short *inst)
3269 {
3270 /* The size can be either byte or word, check which one it is.
3271 Don't check the highest bit, it's indicating if it's a zero
3272 or sign extend. */
3273 if (cris_get_size (*inst) & INST_WORD_SIZE)
3274 {
3275 /* Word size. */
3276 value &= 0xFFFF;
3277
3278 /* Check if the instruction is signed extend. If so, check if value has
3279 the sign bit on. */
3280 if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_WORD_MASK))
3281 {
3282 value |= SIGNED_WORD_EXTEND_MASK;
3283 }
3284 }
3285 else
3286 {
3287 /* Byte size. */
3288 value &= 0xFF;
3289
3290 /* Check if the instruction is signed extend. If so, check if value has
3291 the sign bit on. */
3292 if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_BYTE_MASK))
3293 {
3294 value |= SIGNED_BYTE_EXTEND_MASK;
3295 }
3296 }
3297 /* The size should now be dword. */
3298 cris_set_size_to_dword (inst);
3299 return value;
3300 }
3301
3302 /* Handles the register mode for the ADD, SUB, CMP, AND, OR and MOVE
3303 instruction. The MOVE instruction is the move from source to register. */
3304
3305 static void
3306 reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst,
3307 inst_env_type *inst_env)
3308 {
3309 unsigned long operand1;
3310 unsigned long operand2;
3311
3312 /* It's invalid to have a prefix to the instruction. This is a register
3313 mode instruction and can't have a prefix. */
3314 if (inst_env->prefix_found)
3315 {
3316 inst_env->invalid = 1;
3317 return;
3318 }
3319 /* Check if the instruction has PC as its target. */
3320 if (cris_get_operand2 (inst) == REG_PC)
3321 {
3322 if (inst_env->slot_needed)
3323 {
3324 inst_env->invalid = 1;
3325 return;
3326 }
3327 /* The instruction has the PC as its target register. */
3328 operand1 = inst_env->reg[cris_get_operand1 (inst)];
3329 operand2 = inst_env->reg[REG_PC];
3330
3331 /* Check if it's a extend, signed or zero instruction. */
3332 if (cris_get_opcode (inst) < 4)
3333 {
3334 operand1 = do_sign_or_zero_extend (operand1, &inst);
3335 }
3336 /* Calculate the PC value after the instruction, i.e. where the
3337 breakpoint should be. The order of the udw_operands is vital. */
3338 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1);
3339 }
3340 inst_env->slot_needed = 0;
3341 inst_env->prefix_found = 0;
3342 inst_env->xflag_found = 0;
3343 inst_env->disable_interrupt = 0;
3344 }
3345
3346 /* Returns the data contained at address. The size of the data is derived from
3347 the size of the operation. If the instruction is a zero or signed
3348 extend instruction, the size field is changed in instruction. */
3349
3350 static unsigned long
3351 get_data_from_address (unsigned short *inst, CORE_ADDR address,
3352 enum bfd_endian byte_order)
3353 {
3354 int size = cris_get_size (*inst);
3355 unsigned long value;
3356
3357 /* If it's an extend instruction we don't want the signed extend bit,
3358 because it influences the size. */
3359 if (cris_get_opcode (*inst) < 4)
3360 {
3361 size &= ~SIGNED_EXTEND_BIT_MASK;
3362 }
3363 /* Is there a need for checking the size? Size should contain the number of
3364 bytes to read. */
3365 size = 1 << size;
3366 value = read_memory_unsigned_integer (address, size, byte_order);
3367
3368 /* Check if it's an extend, signed or zero instruction. */
3369 if (cris_get_opcode (*inst) < 4)
3370 {
3371 value = do_sign_or_zero_extend (value, inst);
3372 }
3373 return value;
3374 }
3375
3376 /* Handles the assign addresing mode for the ADD, SUB, CMP, AND, OR and MOVE
3377 instructions. The MOVE instruction is the move from source to register. */
3378
3379 static void
3380 handle_prefix_assign_mode_for_aritm_op (unsigned short inst,
3381 inst_env_type *inst_env)
3382 {
3383 unsigned long operand2;
3384 unsigned long operand3;
3385
3386 check_assign (inst, inst_env);
3387 if (cris_get_operand2 (inst) == REG_PC)
3388 {
3389 operand2 = inst_env->reg[REG_PC];
3390
3391 /* Get the value of the third operand. */
3392 operand3 = get_data_from_address (&inst, inst_env->prefix_value,
3393 inst_env->byte_order);
3394
3395 /* Calculate the PC value after the instruction, i.e. where the
3396 breakpoint should be. The order of the udw_operands is vital. */
3397 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3);
3398 }
3399 inst_env->slot_needed = 0;
3400 inst_env->prefix_found = 0;
3401 inst_env->xflag_found = 0;
3402 inst_env->disable_interrupt = 0;
3403 }
3404
3405 /* Handles the three-operand addressing mode for the ADD, SUB, CMP, AND and
3406 OR instructions. Note that for this to work as expected, the calling
3407 function must have made sure that there is a prefix to this instruction. */
3408
3409 static void
3410 three_operand_add_sub_cmp_and_or_op (unsigned short inst,
3411 inst_env_type *inst_env)
3412 {
3413 unsigned long operand2;
3414 unsigned long operand3;
3415
3416 if (cris_get_operand1 (inst) == REG_PC)
3417 {
3418 /* The PC will be changed by the instruction. */
3419 operand2 = inst_env->reg[cris_get_operand2 (inst)];
3420
3421 /* Get the value of the third operand. */
3422 operand3 = get_data_from_address (&inst, inst_env->prefix_value,
3423 inst_env->byte_order);
3424
3425 /* Calculate the PC value after the instruction, i.e. where the
3426 breakpoint should be. */
3427 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3);
3428 }
3429 inst_env->slot_needed = 0;
3430 inst_env->prefix_found = 0;
3431 inst_env->xflag_found = 0;
3432 inst_env->disable_interrupt = 0;
3433 }
3434
3435 /* Handles the index addresing mode for the ADD, SUB, CMP, AND, OR and MOVE
3436 instructions. The MOVE instruction is the move from source to register. */
3437
3438 static void
3439 handle_prefix_index_mode_for_aritm_op (unsigned short inst,
3440 inst_env_type *inst_env)
3441 {
3442 if (cris_get_operand1 (inst) != cris_get_operand2 (inst))
3443 {
3444 /* If the instruction is MOVE it's invalid. If the instruction is ADD,
3445 SUB, AND or OR something weird is going on (if everything works these
3446 instructions should end up in the three operand version). */
3447 inst_env->invalid = 1;
3448 return;
3449 }
3450 else
3451 {
3452 /* three_operand_add_sub_cmp_and_or does the same as we should do here
3453 so use it. */
3454 three_operand_add_sub_cmp_and_or_op (inst, inst_env);
3455 }
3456 inst_env->slot_needed = 0;
3457 inst_env->prefix_found = 0;
3458 inst_env->xflag_found = 0;
3459 inst_env->disable_interrupt = 0;
3460 }
3461
3462 /* Handles the autoincrement and indirect addresing mode for the ADD, SUB,
3463 CMP, AND OR and MOVE instruction. The MOVE instruction is the move from
3464 source to register. */
3465
3466 static void
3467 handle_inc_and_index_mode_for_aritm_op (unsigned short inst,
3468 inst_env_type *inst_env)
3469 {
3470 unsigned long operand1;
3471 unsigned long operand2;
3472 unsigned long operand3;
3473 int size;
3474
3475 /* The instruction is either an indirect or autoincrement addressing mode.
3476 Check if the destination register is the PC. */
3477 if (cris_get_operand2 (inst) == REG_PC)
3478 {
3479 /* Must be done here, get_data_from_address may change the size
3480 field. */
3481 size = cris_get_size (inst);
3482 operand2 = inst_env->reg[REG_PC];
3483
3484 /* Get the value of the third operand, i.e. the indirect operand. */
3485 operand1 = inst_env->reg[cris_get_operand1 (inst)];
3486 operand3 = get_data_from_address (&inst, operand1, inst_env->byte_order);
3487
3488 /* Calculate the PC value after the instruction, i.e. where the
3489 breakpoint should be. The order of the udw_operands is vital. */
3490 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3);
3491 }
3492 /* If this is an autoincrement addressing mode, check if the increment
3493 changes the PC. */
3494 if ((cris_get_operand1 (inst) == REG_PC)
3495 && (cris_get_mode (inst) == AUTOINC_MODE))
3496 {
3497 /* Get the size field. */
3498 size = cris_get_size (inst);
3499
3500 /* If it's an extend instruction we don't want the signed extend bit,
3501 because it influences the size. */
3502 if (cris_get_opcode (inst) < 4)
3503 {
3504 size &= ~SIGNED_EXTEND_BIT_MASK;
3505 }
3506 process_autoincrement (size, inst, inst_env);
3507 }
3508 inst_env->slot_needed = 0;
3509 inst_env->prefix_found = 0;
3510 inst_env->xflag_found = 0;
3511 inst_env->disable_interrupt = 0;
3512 }
3513
3514 /* Handles the two-operand addressing mode, all modes except register, for
3515 the ADD, SUB CMP, AND and OR instruction. */
3516
3517 static void
3518 none_reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst,
3519 inst_env_type *inst_env)
3520 {
3521 if (inst_env->prefix_found)
3522 {
3523 if (cris_get_mode (inst) == PREFIX_INDEX_MODE)
3524 {
3525 handle_prefix_index_mode_for_aritm_op (inst, inst_env);
3526 }
3527 else if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
3528 {
3529 handle_prefix_assign_mode_for_aritm_op (inst, inst_env);
3530 }
3531 else
3532 {
3533 /* The mode is invalid for a prefixed base instruction. */
3534 inst_env->invalid = 1;
3535 return;
3536 }
3537 }
3538 else
3539 {
3540 handle_inc_and_index_mode_for_aritm_op (inst, inst_env);
3541 }
3542 }
3543
3544 /* Handles the quick addressing mode for the ADD and SUB instruction. */
3545
3546 static void
3547 quick_mode_add_sub_op (unsigned short inst, inst_env_type *inst_env)
3548 {
3549 unsigned long operand1;
3550 unsigned long operand2;
3551
3552 /* It's a bad idea to be in a prefix instruction now. This is a quick mode
3553 instruction and can't have a prefix. */
3554 if (inst_env->prefix_found)
3555 {
3556 inst_env->invalid = 1;
3557 return;
3558 }
3559
3560 /* Check if the instruction has PC as its target. */
3561 if (cris_get_operand2 (inst) == REG_PC)
3562 {
3563 if (inst_env->slot_needed)
3564 {
3565 inst_env->invalid = 1;
3566 return;
3567 }
3568 operand1 = cris_get_quick_value (inst);
3569 operand2 = inst_env->reg[REG_PC];
3570
3571 /* The size should now be dword. */
3572 cris_set_size_to_dword (&inst);
3573
3574 /* Calculate the PC value after the instruction, i.e. where the
3575 breakpoint should be. */
3576 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1);
3577 }
3578 inst_env->slot_needed = 0;
3579 inst_env->prefix_found = 0;
3580 inst_env->xflag_found = 0;
3581 inst_env->disable_interrupt = 0;
3582 }
3583
3584 /* Handles the quick addressing mode for the CMP, AND and OR instruction. */
3585
3586 static void
3587 quick_mode_and_cmp_move_or_op (unsigned short inst, inst_env_type *inst_env)
3588 {
3589 unsigned long operand1;
3590 unsigned long operand2;
3591
3592 /* It's a bad idea to be in a prefix instruction now. This is a quick mode
3593 instruction and can't have a prefix. */
3594 if (inst_env->prefix_found)
3595 {
3596 inst_env->invalid = 1;
3597 return;
3598 }
3599 /* Check if the instruction has PC as its target. */
3600 if (cris_get_operand2 (inst) == REG_PC)
3601 {
3602 if (inst_env->slot_needed)
3603 {
3604 inst_env->invalid = 1;
3605 return;
3606 }
3607 /* The instruction has the PC as its target register. */
3608 operand1 = cris_get_quick_value (inst);
3609 operand2 = inst_env->reg[REG_PC];
3610
3611 /* The quick value is signed, so check if we must do a signed extend. */
3612 if (operand1 & SIGNED_QUICK_VALUE_MASK)
3613 {
3614 /* sign extend */
3615 operand1 |= SIGNED_QUICK_VALUE_EXTEND_MASK;
3616 }
3617 /* The size should now be dword. */
3618 cris_set_size_to_dword (&inst);
3619
3620 /* Calculate the PC value after the instruction, i.e. where the
3621 breakpoint should be. */
3622 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1);
3623 }
3624 inst_env->slot_needed = 0;
3625 inst_env->prefix_found = 0;
3626 inst_env->xflag_found = 0;
3627 inst_env->disable_interrupt = 0;
3628 }
3629
3630 /* Translate op_type to a function and call it. */
3631
3632 static void
3633 cris_gdb_func (struct gdbarch *gdbarch, enum cris_op_type op_type,
3634 unsigned short inst, inst_env_type *inst_env)
3635 {
3636 switch (op_type)
3637 {
3638 case cris_not_implemented_op:
3639 not_implemented_op (inst, inst_env);
3640 break;
3641
3642 case cris_abs_op:
3643 abs_op (inst, inst_env);
3644 break;
3645
3646 case cris_addi_op:
3647 addi_op (inst, inst_env);
3648 break;
3649
3650 case cris_asr_op:
3651 asr_op (inst, inst_env);
3652 break;
3653
3654 case cris_asrq_op:
3655 asrq_op (inst, inst_env);
3656 break;
3657
3658 case cris_ax_ei_setf_op:
3659 ax_ei_setf_op (inst, inst_env);
3660 break;
3661
3662 case cris_bdap_prefix:
3663 bdap_prefix (inst, inst_env);
3664 break;
3665
3666 case cris_biap_prefix:
3667 biap_prefix (inst, inst_env);
3668 break;
3669
3670 case cris_break_op:
3671 break_op (inst, inst_env);
3672 break;
3673
3674 case cris_btst_nop_op:
3675 btst_nop_op (inst, inst_env);
3676 break;
3677
3678 case cris_clearf_di_op:
3679 clearf_di_op (inst, inst_env);
3680 break;
3681
3682 case cris_dip_prefix:
3683 dip_prefix (inst, inst_env);
3684 break;
3685
3686 case cris_dstep_logshift_mstep_neg_not_op:
3687 dstep_logshift_mstep_neg_not_op (inst, inst_env);
3688 break;
3689
3690 case cris_eight_bit_offset_branch_op:
3691 eight_bit_offset_branch_op (inst, inst_env);
3692 break;
3693
3694 case cris_move_mem_to_reg_movem_op:
3695 move_mem_to_reg_movem_op (inst, inst_env);
3696 break;
3697
3698 case cris_move_reg_to_mem_movem_op:
3699 move_reg_to_mem_movem_op (inst, inst_env);
3700 break;
3701
3702 case cris_move_to_preg_op:
3703 move_to_preg_op (gdbarch, inst, inst_env);
3704 break;
3705
3706 case cris_muls_op:
3707 muls_op (inst, inst_env);
3708 break;
3709
3710 case cris_mulu_op:
3711 mulu_op (inst, inst_env);
3712 break;
3713
3714 case cris_none_reg_mode_add_sub_cmp_and_or_move_op:
3715 none_reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env);
3716 break;
3717
3718 case cris_none_reg_mode_clear_test_op:
3719 none_reg_mode_clear_test_op (inst, inst_env);
3720 break;
3721
3722 case cris_none_reg_mode_jump_op:
3723 none_reg_mode_jump_op (inst, inst_env);
3724 break;
3725
3726 case cris_none_reg_mode_move_from_preg_op:
3727 none_reg_mode_move_from_preg_op (gdbarch, inst, inst_env);
3728 break;
3729
3730 case cris_quick_mode_add_sub_op:
3731 quick_mode_add_sub_op (inst, inst_env);
3732 break;
3733
3734 case cris_quick_mode_and_cmp_move_or_op:
3735 quick_mode_and_cmp_move_or_op (inst, inst_env);
3736 break;
3737
3738 case cris_quick_mode_bdap_prefix:
3739 quick_mode_bdap_prefix (inst, inst_env);
3740 break;
3741
3742 case cris_reg_mode_add_sub_cmp_and_or_move_op:
3743 reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env);
3744 break;
3745
3746 case cris_reg_mode_clear_op:
3747 reg_mode_clear_op (inst, inst_env);
3748 break;
3749
3750 case cris_reg_mode_jump_op:
3751 reg_mode_jump_op (inst, inst_env);
3752 break;
3753
3754 case cris_reg_mode_move_from_preg_op:
3755 reg_mode_move_from_preg_op (inst, inst_env);
3756 break;
3757
3758 case cris_reg_mode_test_op:
3759 reg_mode_test_op (inst, inst_env);
3760 break;
3761
3762 case cris_scc_op:
3763 scc_op (inst, inst_env);
3764 break;
3765
3766 case cris_sixteen_bit_offset_branch_op:
3767 sixteen_bit_offset_branch_op (inst, inst_env);
3768 break;
3769
3770 case cris_three_operand_add_sub_cmp_and_or_op:
3771 three_operand_add_sub_cmp_and_or_op (inst, inst_env);
3772 break;
3773
3774 case cris_three_operand_bound_op:
3775 three_operand_bound_op (inst, inst_env);
3776 break;
3777
3778 case cris_two_operand_bound_op:
3779 two_operand_bound_op (inst, inst_env);
3780 break;
3781
3782 case cris_xor_op:
3783 xor_op (inst, inst_env);
3784 break;
3785 }
3786 }
3787
3788 /* Originally from <asm/elf.h>. */
3789 typedef unsigned char cris_elf_greg_t[4];
3790
3791 /* Same as user_regs_struct struct in <asm/user.h>. */
3792 #define CRISV10_ELF_NGREG 35
3793 typedef cris_elf_greg_t cris_elf_gregset_t[CRISV10_ELF_NGREG];
3794
3795 #define CRISV32_ELF_NGREG 32
3796 typedef cris_elf_greg_t crisv32_elf_gregset_t[CRISV32_ELF_NGREG];
3797
3798 /* Unpack a cris_elf_gregset_t into GDB's register cache. */
3799
3800 static void
3801 cris_supply_gregset (struct regcache *regcache, cris_elf_gregset_t *gregsetp)
3802 {
3803 struct gdbarch *gdbarch = regcache->arch ();
3804 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3805 int i;
3806 cris_elf_greg_t *regp = *gregsetp;
3807
3808 /* The kernel dumps all 32 registers as unsigned longs, but supply_register
3809 knows about the actual size of each register so that's no problem. */
3810 for (i = 0; i < NUM_GENREGS + NUM_SPECREGS; i++)
3811 {
3812 regcache_raw_supply (regcache, i, (char *)&regp[i]);
3813 }
3814
3815 if (tdep->cris_version == 32)
3816 {
3817 /* Needed to set pseudo-register PC for CRISv32. */
3818 /* FIXME: If ERP is in a delay slot at this point then the PC will
3819 be wrong. Issue a warning to alert the user. */
3820 regcache_raw_supply (regcache, gdbarch_pc_regnum (gdbarch),
3821 (char *)&regp[ERP_REGNUM]);
3822
3823 if (*(char *)&regp[ERP_REGNUM] & 0x1)
3824 fprintf_unfiltered (gdb_stderr, "Warning: PC in delay slot\n");
3825 }
3826 }
3827
3828 /* Use a local version of this function to get the correct types for
3829 regsets, until multi-arch core support is ready. */
3830
3831 static void
3832 fetch_core_registers (struct regcache *regcache,
3833 char *core_reg_sect, unsigned core_reg_size,
3834 int which, CORE_ADDR reg_addr)
3835 {
3836 cris_elf_gregset_t gregset;
3837
3838 switch (which)
3839 {
3840 case 0:
3841 if (core_reg_size != sizeof (cris_elf_gregset_t)
3842 && core_reg_size != sizeof (crisv32_elf_gregset_t))
3843 {
3844 warning (_("wrong size gregset struct in core file"));
3845 }
3846 else
3847 {
3848 memcpy (&gregset, core_reg_sect, sizeof (gregset));
3849 cris_supply_gregset (regcache, &gregset);
3850 }
3851
3852 default:
3853 /* We've covered all the kinds of registers we know about here,
3854 so this must be something we wouldn't know what to do with
3855 anyway. Just ignore it. */
3856 break;
3857 }
3858 }
3859
3860 static struct core_fns cris_elf_core_fns =
3861 {
3862 bfd_target_elf_flavour, /* core_flavour */
3863 default_check_format, /* check_format */
3864 default_core_sniffer, /* core_sniffer */
3865 fetch_core_registers, /* core_read_registers */
3866 NULL /* next */
3867 };
3868
3869 void
3870 _initialize_cris_tdep (void)
3871 {
3872 gdbarch_register (bfd_arch_cris, cris_gdbarch_init, cris_dump_tdep);
3873
3874 /* CRIS-specific user-commands. */
3875 add_setshow_zuinteger_cmd ("cris-version", class_support,
3876 &usr_cmd_cris_version,
3877 _("Set the current CRIS version."),
3878 _("Show the current CRIS version."),
3879 _("\
3880 Set to 10 for CRISv10 or 32 for CRISv32 if autodetection fails.\n\
3881 Defaults to 10. "),
3882 set_cris_version,
3883 NULL, /* FIXME: i18n: Current CRIS version
3884 is %s. */
3885 &setlist, &showlist);
3886
3887 add_setshow_enum_cmd ("cris-mode", class_support,
3888 cris_modes, &usr_cmd_cris_mode,
3889 _("Set the current CRIS mode."),
3890 _("Show the current CRIS mode."),
3891 _("\
3892 Set to CRIS_MODE_GURU when debugging in guru mode.\n\
3893 Makes GDB use the NRP register instead of the ERP register in certain cases."),
3894 set_cris_mode,
3895 NULL, /* FIXME: i18n: Current CRIS version is %s. */
3896 &setlist, &showlist);
3897
3898 add_setshow_boolean_cmd ("cris-dwarf2-cfi", class_support,
3899 &usr_cmd_cris_dwarf2_cfi,
3900 _("Set the usage of Dwarf-2 CFI for CRIS."),
3901 _("Show the usage of Dwarf-2 CFI for CRIS."),
3902 _("Set this to \"off\" if using gcc-cris < R59."),
3903 set_cris_dwarf2_cfi,
3904 NULL, /* FIXME: i18n: Usage of Dwarf-2 CFI
3905 for CRIS is %d. */
3906 &setlist, &showlist);
3907
3908 deprecated_add_core_fns (&cris_elf_core_fns);
3909 }
3910
3911 /* Prints out all target specific values. */
3912
3913 static void
3914 cris_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
3915 {
3916 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3917 if (tdep != NULL)
3918 {
3919 fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_version = %i\n",
3920 tdep->cris_version);
3921 fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_mode = %s\n",
3922 tdep->cris_mode);
3923 fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_dwarf2_cfi = %i\n",
3924 tdep->cris_dwarf2_cfi);
3925 }
3926 }
3927
3928 static void
3929 set_cris_version (const char *ignore_args, int from_tty,
3930 struct cmd_list_element *c)
3931 {
3932 struct gdbarch_info info;
3933
3934 usr_cmd_cris_version_valid = 1;
3935
3936 /* Update the current architecture, if needed. */
3937 gdbarch_info_init (&info);
3938 if (!gdbarch_update_p (info))
3939 internal_error (__FILE__, __LINE__,
3940 _("cris_gdbarch_update: failed to update architecture."));
3941 }
3942
3943 static void
3944 set_cris_mode (const char *ignore_args, int from_tty,
3945 struct cmd_list_element *c)
3946 {
3947 struct gdbarch_info info;
3948
3949 /* Update the current architecture, if needed. */
3950 gdbarch_info_init (&info);
3951 if (!gdbarch_update_p (info))
3952 internal_error (__FILE__, __LINE__,
3953 "cris_gdbarch_update: failed to update architecture.");
3954 }
3955
3956 static void
3957 set_cris_dwarf2_cfi (const char *ignore_args, int from_tty,
3958 struct cmd_list_element *c)
3959 {
3960 struct gdbarch_info info;
3961
3962 /* Update the current architecture, if needed. */
3963 gdbarch_info_init (&info);
3964 if (!gdbarch_update_p (info))
3965 internal_error (__FILE__, __LINE__,
3966 _("cris_gdbarch_update: failed to update architecture."));
3967 }
3968
3969 static struct gdbarch *
3970 cris_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
3971 {
3972 struct gdbarch *gdbarch;
3973 struct gdbarch_tdep *tdep;
3974 unsigned int cris_version;
3975
3976 if (usr_cmd_cris_version_valid)
3977 {
3978 /* Trust the user's CRIS version setting. */
3979 cris_version = usr_cmd_cris_version;
3980 }
3981 else if (info.abfd && bfd_get_mach (info.abfd) == bfd_mach_cris_v32)
3982 {
3983 cris_version = 32;
3984 }
3985 else
3986 {
3987 /* Assume it's CRIS version 10. */
3988 cris_version = 10;
3989 }
3990
3991 /* Make the current settings visible to the user. */
3992 usr_cmd_cris_version = cris_version;
3993
3994 /* Find a candidate among the list of pre-declared architectures. */
3995 for (arches = gdbarch_list_lookup_by_info (arches, &info);
3996 arches != NULL;
3997 arches = gdbarch_list_lookup_by_info (arches->next, &info))
3998 {
3999 if ((gdbarch_tdep (arches->gdbarch)->cris_version
4000 == usr_cmd_cris_version)
4001 && (gdbarch_tdep (arches->gdbarch)->cris_mode
4002 == usr_cmd_cris_mode)
4003 && (gdbarch_tdep (arches->gdbarch)->cris_dwarf2_cfi
4004 == usr_cmd_cris_dwarf2_cfi))
4005 return arches->gdbarch;
4006 }
4007
4008 /* No matching architecture was found. Create a new one. */
4009 tdep = XCNEW (struct gdbarch_tdep);
4010 info.byte_order = BFD_ENDIAN_LITTLE;
4011 gdbarch = gdbarch_alloc (&info, tdep);
4012
4013 tdep->cris_version = usr_cmd_cris_version;
4014 tdep->cris_mode = usr_cmd_cris_mode;
4015 tdep->cris_dwarf2_cfi = usr_cmd_cris_dwarf2_cfi;
4016
4017 set_gdbarch_return_value (gdbarch, cris_return_value);
4018 set_gdbarch_sp_regnum (gdbarch, 14);
4019
4020 /* Length of ordinary registers used in push_word and a few other
4021 places. register_size() is the real way to know how big a
4022 register is. */
4023
4024 set_gdbarch_double_bit (gdbarch, 64);
4025 /* The default definition of a long double is 2 * gdbarch_double_bit,
4026 which means we have to set this explicitly. */
4027 set_gdbarch_long_double_bit (gdbarch, 64);
4028
4029 /* The total amount of space needed to store (in an array called registers)
4030 GDB's copy of the machine's register state. Note: We can not use
4031 cris_register_size at this point, since it relies on gdbarch
4032 being set. */
4033 switch (tdep->cris_version)
4034 {
4035 case 0:
4036 case 1:
4037 case 2:
4038 case 3:
4039 case 8:
4040 case 9:
4041 /* Old versions; not supported. */
4042 return 0;
4043
4044 case 10:
4045 case 11:
4046 /* CRIS v10 and v11, a.k.a. ETRAX 100LX. In addition to ETRAX 100,
4047 P7 (32 bits), and P15 (32 bits) have been implemented. */
4048 set_gdbarch_pc_regnum (gdbarch, 15);
4049 set_gdbarch_register_type (gdbarch, cris_register_type);
4050 /* There are 32 registers (some of which may not be implemented). */
4051 set_gdbarch_num_regs (gdbarch, 32);
4052 set_gdbarch_register_name (gdbarch, cris_register_name);
4053 set_gdbarch_cannot_store_register (gdbarch, cris_cannot_store_register);
4054 set_gdbarch_cannot_fetch_register (gdbarch, cris_cannot_fetch_register);
4055
4056 set_gdbarch_software_single_step (gdbarch, cris_software_single_step);
4057 break;
4058
4059 case 32:
4060 /* CRIS v32. General registers R0 - R15 (32 bits), special registers
4061 P0 - P15 (32 bits) except P0, P1, P3 (8 bits) and P4 (16 bits)
4062 and pseudo-register PC (32 bits). */
4063 set_gdbarch_pc_regnum (gdbarch, 32);
4064 set_gdbarch_register_type (gdbarch, crisv32_register_type);
4065 /* 32 registers + pseudo-register PC + 16 support registers. */
4066 set_gdbarch_num_regs (gdbarch, 32 + 1 + 16);
4067 set_gdbarch_register_name (gdbarch, crisv32_register_name);
4068
4069 set_gdbarch_cannot_store_register
4070 (gdbarch, crisv32_cannot_store_register);
4071 set_gdbarch_cannot_fetch_register
4072 (gdbarch, crisv32_cannot_fetch_register);
4073
4074 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
4075
4076 set_gdbarch_single_step_through_delay
4077 (gdbarch, crisv32_single_step_through_delay);
4078
4079 break;
4080
4081 default:
4082 /* Unknown version. */
4083 return 0;
4084 }
4085
4086 /* Dummy frame functions (shared between CRISv10 and CRISv32 since they
4087 have the same ABI). */
4088 set_gdbarch_push_dummy_code (gdbarch, cris_push_dummy_code);
4089 set_gdbarch_push_dummy_call (gdbarch, cris_push_dummy_call);
4090 set_gdbarch_frame_align (gdbarch, cris_frame_align);
4091 set_gdbarch_skip_prologue (gdbarch, cris_skip_prologue);
4092
4093 /* The stack grows downward. */
4094 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
4095
4096 set_gdbarch_breakpoint_kind_from_pc (gdbarch, cris_breakpoint_kind_from_pc);
4097 set_gdbarch_sw_breakpoint_from_kind (gdbarch, cris_sw_breakpoint_from_kind);
4098
4099 set_gdbarch_unwind_pc (gdbarch, cris_unwind_pc);
4100 set_gdbarch_unwind_sp (gdbarch, cris_unwind_sp);
4101 set_gdbarch_dummy_id (gdbarch, cris_dummy_id);
4102
4103 if (tdep->cris_dwarf2_cfi == 1)
4104 {
4105 /* Hook in the Dwarf-2 frame sniffer. */
4106 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, cris_dwarf2_reg_to_regnum);
4107 dwarf2_frame_set_init_reg (gdbarch, cris_dwarf2_frame_init_reg);
4108 dwarf2_append_unwinders (gdbarch);
4109 }
4110
4111 if (tdep->cris_mode != cris_mode_guru)
4112 {
4113 frame_unwind_append_unwinder (gdbarch, &cris_sigtramp_frame_unwind);
4114 }
4115
4116 frame_unwind_append_unwinder (gdbarch, &cris_frame_unwind);
4117 frame_base_set_default (gdbarch, &cris_frame_base);
4118
4119 /* Hook in ABI-specific overrides, if they have been registered. */
4120 gdbarch_init_osabi (info, gdbarch);
4121
4122 return gdbarch;
4123 }
set_gdbarch_num_regs
void set_gdbarch_num_regs(struct gdbarch *gdbarch, int num_regs)
Definition: gdbarch.c:2050
gdbarch
Definition: gdbarch.c:127
set_gdbarch_double_bit
void set_gdbarch_double_bit(struct gdbarch *gdbarch, int double_bit)
Definition: gdbarch.c:1723
instruction_environment
Definition: cris-tdep.c:473
set_gdbarch_frame_align
void set_gdbarch_frame_align(struct gdbarch *gdbarch, gdbarch_frame_align_ftype frame_align)
Definition: gdbarch.c:3151
set_gdbarch_have_nonsteppable_watchpoint
void set_gdbarch_have_nonsteppable_watchpoint(struct gdbarch *gdbarch, int have_nonsteppable_watchpoint)
Definition: gdbarch.c:3493
set_gdbarch_cannot_fetch_register
void set_gdbarch_cannot_fetch_register(struct gdbarch *gdbarch, gdbarch_cannot_fetch_register_ftype cannot_fetch_register)
Definition: gdbarch.c:2531
cris_spec_reg_applicable
static int cris_spec_reg_applicable(struct gdbarch *gdbarch, struct cris_spec_reg spec_reg)
Definition: cris-tdep.c:1423
NUM_GENREGS
Definition: cris-tdep.c:55
IBR_REGNUM
Definition: cris-tdep.c:102
crisv32_elf_gregset_t
cris_elf_greg_t crisv32_elf_gregset_t[CRISV32_ELF_NGREG]
Definition: cris-tdep.c:3796
inst_env_type
struct instruction_environment inst_env_type
cris_extract_return_value
static void cris_extract_return_value(struct type *type, struct regcache *regcache, gdb_byte *valbuf)
Definition: cris-tdep.c:1811
regcache_raw_get_unsigned
ULONGEST regcache_raw_get_unsigned(struct regcache *regcache, int regnum)
Definition: common-regcache.c:26
cris_set_size_to_dword
static void cris_set_size_to_dword(unsigned short *insn)
Definition: cris-tdep.c:615
addi_op
static void addi_op(unsigned short inst, inst_env_type *inst_env)
Definition: cris-tdep.c:2379
S8_REGNUM
Definition: cris-tdep.c:134
default_check_format
int default_check_format(bfd *abfd)
Definition: corelow.c:162
set_cris_mode
static void set_cris_mode(const char *ignore_args, int from_tty, struct cmd_list_element *c)
Definition: cris-tdep.c:3944
frame_id_build
struct frame_id frame_id_build(CORE_ADDR stack_addr, CORE_ADDR code_addr)
Definition: frame.c:624
stack_item::prev
struct stack_item * prev
Definition: arm-tdep.c:3328
breakpoint_here_p
enum breakpoint_here breakpoint_here_p(const address_space *aspace, CORE_ADDR pc)
Definition: breakpoint.c:3989
get_data_from_address
static unsigned long get_data_from_address(unsigned short *inst, CORE_ADDR address, enum bfd_endian byte_order)
Definition: cris-tdep.c:3351
AUTOINC_MODE
Definition: cris-tdep.c:506
NUM_SPECREGS
Definition: cris-tdep.c:58
builtin_type::builtin_func_ptr
struct type * builtin_func_ptr
Definition: gdbtypes.h:1565
get_frame_pc
CORE_ADDR get_frame_pc(struct frame_info *frame)
Definition: frame.c:2376
dip_prefix
static void dip_prefix(unsigned short inst, inst_env_type *inst_env)
Definition: cris-tdep.c:2234
usr_cmd_cris_dwarf2_cfi
static int usr_cmd_cris_dwarf2_cfi
Definition: cris-tdep.c:166
CORE_ADDR
bfd_vma CORE_ADDR
Definition: common-types.h:41
S9_REGNUM
Definition: cris-tdep.c:135
gdbarch_init_osabi
void gdbarch_init_osabi(struct gdbarch_info info, struct gdbarch *gdbarch)
Definition: osabi.c:334
dwarf2_frame_state_reg
Definition: dwarf2-frame.h:70
trad_frame_get_prev_register
struct value * trad_frame_get_prev_register(struct frame_info *this_frame, struct trad_frame_saved_reg this_saved_regs[], int regnum)
Definition: trad-frame.c:142
instruction_environment::branch_found
int branch_found
Definition: cris-tdep.c:481
xfree
void xfree(void *)
P8_REGNUM
Definition: cris-tdep.c:101
ARG3_REGNUM
Definition: cris-tdep.c:89
class_support
Definition: command.h:42
SIGNED_WORD_EXTEND_MASK
Definition: cris-tdep.c:527
fetch_core_registers
static void fetch_core_registers(struct regcache *regcache, char *core_reg_sect, unsigned core_reg_size, int which, CORE_ADDR reg_addr)
Definition: cris-tdep.c:3832
cmd_list_element
Definition: cli-decode.h:46
func
void(* func)(char *)
Definition: remote-fileio.c:1104
if
if(!(yy_init))
Definition: ada-lex.c:1075
SIGNED_QUICK_VALUE_EXTEND_MASK
Definition: cris-tdep.c:530
warning
void warning(const char *fmt,...)
Definition: errors.c:26
instruction_environment::slot_needed
int slot_needed
Definition: cris-tdep.c:484
symtab_and_line::end
CORE_ADDR end
Definition: symtab.h:1760
trad_frame_set_value
void trad_frame_set_value(struct trad_frame_saved_reg this_saved_regs[], int regnum, LONGEST val)
Definition: trad-frame.c:99
crisv32_register_type
static struct type * crisv32_register_type(struct gdbarch *gdbarch, int regno)
Definition: cris-tdep.c:1611
gdbarch_tdep::gregset
const struct regset * gregset
Definition: sparc-tdep.h:73
cris_gdb_func
static void cris_gdb_func(struct gdbarch *, enum cris_op_type, unsigned short, inst_env_type *)
Definition: cris-tdep.c:3633
RETURN_VALUE_STRUCT_CONVENTION
Definition: defs.h:258
core_fns
Definition: gdbcore.h:169
cris_breakpoint_kind_from_pc
static int cris_breakpoint_kind_from_pc(struct gdbarch *gdbarch, CORE_ADDR *pcptr)
Definition: cris-tdep.c:1397
frame_unwind_register_unsigned
ULONGEST frame_unwind_register_unsigned(struct frame_info *frame, int regnum)
Definition: frame.c:1279
cris_get_operand1
static int cris_get_operand1(unsigned short insn)
Definition: cris-tdep.c:565
quick_mode_add_sub_op
static void quick_mode_add_sub_op(unsigned short inst, inst_env_type *inst_env)
Definition: cris-tdep.c:3547
PREFIX_INDEX_MODE
Definition: cris-tdep.c:512
builtin_type
const struct builtin_type * builtin_type(struct gdbarch *gdbarch)
Definition: gdbtypes.c:5217
move_reg_to_mem_movem_op
static void move_reg_to_mem_movem_op(unsigned short inst, inst_env_type *inst_env)
Definition: cris-tdep.c:3060
SIGNED_WORD_MASK
Definition: cris-tdep.c:526
eight_bit_offset_branch_op
static void eight_bit_offset_branch_op(unsigned short inst, inst_env_type *inst_env)
Definition: cris-tdep.c:2268
internal_error
void internal_error(const char *file, int line, const char *fmt,...)
Definition: errors.c:50
cris_sw_breakpoint_from_kind
static const gdb_byte * cris_sw_breakpoint_from_kind(struct gdbarch *gdbarch, int kind, int *size)
Definition: cris-tdep.c:1405
cris_store_return_value
static void cris_store_return_value(struct type *type, struct regcache *regcache, const gdb_byte *valbuf)
Definition: cris-tdep.c:1643
gdbarch_update_p
int gdbarch_update_p(struct gdbarch_info info)
Definition: arch-utils.c:525
gdbarch_tdep
Definition: aarch64-tdep.h:55
return_value_convention
return_value_convention
Definition: defs.h:247
biap_prefix
static void biap_prefix(unsigned short inst, inst_env_type *inst_env)
Definition: cris-tdep.c:2199
IRP_REGNUM
Definition: cris-tdep.c:103
SIGTRAMP_INSN0
#define SIGTRAMP_INSN0
Definition: cris-tdep.c:170
builtin_type::builtin_uint8
struct type * builtin_uint8
Definition: gdbtypes.h:1535
add_setshow_enum_cmd
void add_setshow_enum_cmd(const char *name, enum command_class theclass, const char *const *enumlist, const char **var, const char *set_doc, const char *show_doc, const char *help_doc, cmd_const_sfunc_ftype *set_func, show_value_ftype *show_func, struct cmd_list_element **set_list, struct cmd_list_element **show_list)
Definition: cli-decode.c:515
P4_REGNUM
Definition: cris-tdep.c:99
usr_cmd_cris_version
static unsigned int usr_cmd_cris_version
Definition: cris-tdep.c:148
builtin_type::builtin_uint16
struct type * builtin_uint16
Definition: gdbtypes.h:1537
cris_num_regs
cris_num_regs
Definition: cris-tdep.c:49
cris_elf_gregset_t
cris_elf_greg_t cris_elf_gregset_t[CRISV10_ELF_NGREG]
Definition: cris-tdep.c:3793
crisv32_register_name
static const char * crisv32_register_name(struct gdbarch *gdbarch, int regno)
Definition: cris-tdep.c:1721
SIGTRAMP_FRAME
Definition: frame.h:255
cris_instruction_sizes
cris_instruction_sizes
Definition: cris-tdep.c:494
move_to_preg_op
static void move_to_preg_op(struct gdbarch *gdbarch, unsigned short inst, inst_env_type *inst_env)
Definition: cris-tdep.c:2854
frame_info
Definition: frame.c:85
cris_unwind_cache::base
CORE_ADDR base
Definition: cris-tdep.c:293
sixteen_bit_offset_branch_op
static void sixteen_bit_offset_branch_op(unsigned short inst, inst_env_type *inst_env)
Definition: cris-tdep.c:2305
CRISV32USP_REGNUM
Definition: cris-tdep.c:122
cris-tdep.h
cris_sigtramp_start
static CORE_ADDR cris_sigtramp_start(struct frame_info *this_frame)
Definition: cris-tdep.c:195
gdbarch_list_lookup_by_info
struct gdbarch_list * gdbarch_list_lookup_by_info(struct gdbarch_list *arches, const struct gdbarch_info *info)
Definition: gdbarch.c:5309
handle_prefix_assign_mode_for_aritm_op
static void handle_prefix_assign_mode_for_aritm_op(unsigned short inst, inst_env_type *inst_env)
Definition: cris-tdep.c:3380
set_cris_version
static void set_cris_version(const char *ignore_args, int from_tty, struct cmd_list_element *c)
Definition: cris-tdep.c:3929
ax_ei_setf_op
static void ax_ei_setf_op(unsigned short inst, inst_env_type *inst_env)
Definition: cris-tdep.c:2523
gdbarch_list::next
struct gdbarch_list * next
Definition: gdbarch.h:1623
gdbarch_num_regs
int gdbarch_num_regs(struct gdbarch *gdbarch)
Definition: gdbarch.c:2039
SIGNED_BYTE_EXTEND_MASK
Definition: cris-tdep.c:525
reg_mode_add_sub_cmp_and_or_move_op
static void reg_mode_add_sub_cmp_and_or_move_op(unsigned short inst, inst_env_type *inst_env)
Definition: cris-tdep.c:3306
stack_item::data
gdb_byte * data
Definition: arm-tdep.c:3329
WZ_REGNUM
Definition: cris-tdep.c:114
_
#define _(String)
Definition: gdb_locale.h:35
cris_unwind_cache::size
int size
Definition: cris-tdep.c:294
cris_return_value
static enum return_value_convention cris_return_value(struct gdbarch *gdbarch, struct value *function, struct type *type, struct regcache *regcache, gdb_byte *readbuf, const gdb_byte *writebuf)
Definition: cris-tdep.c:1840
ui_file
Definition: ui-file.h:26
break_op
static void break_op(unsigned short inst, inst_env_type *inst_env)
Definition: cris-tdep.c:2749
set_gdbarch_dwarf2_reg_to_regnum
void set_gdbarch_dwarf2_reg_to_regnum(struct gdbarch *gdbarch, gdbarch_dwarf2_reg_to_regnum_ftype dwarf2_reg_to_regnum)
Definition: gdbarch.c:2275
NUM_SUPPREGS
Definition: cris-tdep.c:63
defs.h
set_gdbarch_single_step_through_delay
void set_gdbarch_single_step_through_delay(struct gdbarch *gdbarch, gdbarch_single_step_through_delay_ftype single_step_through_delay)
Definition: gdbarch.c:3282
cris_unwind_cache::return_pc
CORE_ADDR return_pc
Definition: cris-tdep.c:303
gdbarch_tdep
struct gdbarch_tdep * gdbarch_tdep(struct gdbarch *gdbarch)
Definition: gdbarch.c:1491
BZ_REGNUM
Definition: cris-tdep.c:111
cris_frame_prev_register
static struct value * cris_frame_prev_register(struct frame_info *this_frame, void **this_cache, int regnum)
Definition: cris-tdep.c:762
S4_REGNUM
Definition: cris-tdep.c:130
sigtramp_code
static const unsigned short sigtramp_code[]
Definition: cris-tdep.c:175
cris_unwind_cache::sp_offset
LONGEST sp_offset
Definition: cris-tdep.c:298
cris_register_size
static int cris_register_size(struct gdbarch *gdbarch, int regno)
Definition: cris-tdep.c:1466
frame_unwind_append_unwinder
void frame_unwind_append_unwinder(struct gdbarch *gdbarch, const struct frame_unwind *unwinder)
Definition: frame-unwind.c:79
cris_elf_greg_t
unsigned char cris_elf_greg_t[4]
Definition: cris-tdep.c:3789
cris_get_clear_size
static int cris_get_clear_size(unsigned short insn)
Definition: cris-tdep.c:597
cris_push_dummy_code
static CORE_ADDR cris_push_dummy_code(struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr, struct value **args, int nargs, struct type *value_type, CORE_ADDR *real_pc, CORE_ADDR *bp_addr, struct regcache *regcache)
Definition: cris-tdep.c:791
FRAME_OBSTACK_ZALLOC
#define FRAME_OBSTACK_ZALLOC(TYPE)
Definition: frame.h:678
cris_get_branch_short_offset
static int cris_get_branch_short_offset(unsigned short insn)
Definition: cris-tdep.c:585
instruction_environment::prefix_value
unsigned long prefix_value
Definition: cris-tdep.c:480
S1_REGNUM
Definition: cris-tdep.c:127
objfiles.h
arch-utils.h
get_frame_address_space
const address_space * get_frame_address_space(struct frame_info *frame)
Definition: frame.c:2646
do_sign_or_zero_extend
static unsigned long do_sign_or_zero_extend(unsigned long value, unsigned short *inst)
Definition: cris-tdep.c:3268
XNEW
#define XNEW(T)
Definition: poison.h:109
INST_BYTE_SIZE
Definition: cris-tdep.c:496
cris_get_bdap_quick_offset
static int cris_get_bdap_quick_offset(unsigned short insn)
Definition: cris-tdep.c:579
reg_mode_clear_op
static void reg_mode_clear_op(unsigned short inst, inst_env_type *inst_env)
Definition: cris-tdep.c:2649
check_assign
static void check_assign(unsigned short inst, inst_env_type *inst_env)
Definition: cris-tdep.c:2549
gdbarch_register
void gdbarch_register(enum bfd_architecture bfd_architecture, gdbarch_init_ftype *init, gdbarch_dump_tdep_ftype *dump_tdep)
Definition: gdbarch.c:5257
ARG4_REGNUM
Definition: cris-tdep.c:90
add_setshow_zuinteger_cmd
void add_setshow_zuinteger_cmd(const char *name, enum command_class theclass, unsigned int *var, const char *set_doc, const char *show_doc, const char *help_doc, cmd_const_sfunc_ftype *set_func, show_value_ftype *show_func, struct cmd_list_element **set_list, struct cmd_list_element **show_list)
Definition: cli-decode.c:792
ARG1_REGNUM
Definition: cris-tdep.c:87
ERP_REGNUM
Definition: cris-tdep.c:119
cris_opcode_masks
cris_opcode_masks
Definition: cris-tdep.c:520
symtab.h
cris_dummy_id
static struct frame_id cris_dummy_id(struct gdbarch *gdbarch, struct frame_info *this_frame)
Definition: cris-tdep.c:775
frame_base_set_default
void frame_base_set_default(struct gdbarch *gdbarch, const struct frame_base *default_base)
Definition: frame-base.c:95
setlist
struct cmd_list_element * setlist
Definition: cli-cmds.c:111
name
const char *const name
Definition: aarch64-tdep.c:76
stack_item
Definition: arm-tdep.c:3325
cris_rt_sigtramp_start
static CORE_ADDR cris_rt_sigtramp_start(struct frame_info *this_frame)
Definition: cris-tdep.c:223
instruction_environment::byte_order
enum bfd_endian byte_order
Definition: cris-tdep.c:488
set_gdbarch_register_type
void set_gdbarch_register_type(struct gdbarch *gdbarch, gdbarch_register_type_ftype register_type)
Definition: gdbarch.c:2316
read_memory_integer
LONGEST read_memory_integer(CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
Definition: corefile.c:316
cris_get_asr_shift_steps
static int cris_get_asr_shift_steps(unsigned long value)
Definition: cris-tdep.c:591
NORMAL_FRAME
Definition: frame.h:244
cris_frame_base_address
static CORE_ADDR cris_frame_base_address(struct frame_info *this_frame, void **this_cache)
Definition: cris-tdep.c:931
value_contents
const gdb_byte * value_contents(struct value *value)
Definition: value.c:1407
find_cris_op
static int find_cris_op(unsigned short insn, inst_env_type *inst_env)
Definition: cris-tdep.c:1953
cris_modes
static const char *const cris_modes[]
Definition: cris-tdep.c:155
cris_get_opcode
static int cris_get_opcode(unsigned short insn)
Definition: cris-tdep.c:553
pop_stack_item
static struct stack_item * pop_stack_item(struct stack_item *si)
Definition: cris-tdep.c:683
cris_frame_align
static CORE_ADDR cris_frame_align(struct gdbarch *gdbarch, CORE_ADDR sp)
Definition: cris-tdep.c:783
find_pc_line
struct symtab_and_line find_pc_line(CORE_ADDR pc, int notcurrent)
Definition: symtab.c:3288
gdbarch_sp_regnum
int gdbarch_sp_regnum(struct gdbarch *gdbarch)
Definition: gdbarch.c:2146
trad-frame.h
usr_cmd_cris_mode
static const char * usr_cmd_cris_mode
Definition: cris-tdep.c:163
cris_register_name
static const char * cris_register_name(struct gdbarch *gdbarch, int regno)
Definition: cris-tdep.c:1696
EBP_REGNUM
Definition: cris-tdep.c:118
none_reg_mode_add_sub_cmp_and_or_move_op
static void none_reg_mode_add_sub_cmp_and_or_move_op(unsigned short inst, inst_env_type *inst_env)
Definition: cris-tdep.c:3518
stack_item::len
int len
Definition: arm-tdep.c:3327
instruction_environment::delay_slot_pc
unsigned long delay_slot_pc
Definition: cris-tdep.c:479
solib-svr4.h
extract_unsigned_integer
static ULONGEST extract_unsigned_integer(const gdb_byte *addr, int len, enum bfd_endian byte_order)
Definition: defs.h:577
cris_mode_normal
static const char cris_mode_normal[]
Definition: cris-tdep.c:153
regcache_cooked_read_unsigned
enum register_status regcache_cooked_read_unsigned(struct regcache *regcache, int regnum, ULONGEST *val)
Definition: regcache.c:777
safe_frame_unwind_memory
int safe_frame_unwind_memory(struct frame_info *this_frame, CORE_ADDR addr, gdb_byte *buf, int len)
Definition: frame.c:2681
osabi.h
reg_mode_test_op
static void reg_mode_test_op(unsigned short inst, inst_env_type *inst_env)
Definition: cris-tdep.c:2686
S15_REGNUM
Definition: cris-tdep.c:141
cris_frame_unwind
static const struct frame_unwind cris_frame_unwind
Definition: cris-tdep.c:920
regcache.h
set_gdbarch_sp_regnum
void set_gdbarch_sp_regnum(struct gdbarch *gdbarch, int sp_regnum)
Definition: gdbarch.c:2156
cris_unwind_cache::r8_offset
LONGEST r8_offset
Definition: cris-tdep.c:299
gdbarch_info::abfd
bfd * abfd
Definition: gdbarch.h:1637
cris_dwarf2_frame_init_reg
static void cris_dwarf2_frame_init_reg(struct gdbarch *gdbarch, int regnum, struct dwarf2_frame_state_reg *reg, struct frame_info *this_frame)
Definition: cris-tdep.c:1791
EDA_REGNUM
Definition: cris-tdep.c:116
RET_REGNUM
Definition: cris-tdep.c:86
set_gdbarch_dummy_id
void set_gdbarch_dummy_id(struct gdbarch *gdbarch, gdbarch_dummy_id_ftype dummy_id)
Definition: gdbarch.c:2340
push_stack_item
static struct stack_item * push_stack_item(struct stack_item *prev, const gdb_byte *contents, int len)
Definition: cris-tdep.c:672
fprintf_unfiltered
void fprintf_unfiltered(struct ui_file *stream, const char *format,...)
Definition: utils.c:2018
DWARF2_FRAME_REG_CFA
Definition: dwarf2-frame.h:64
CCS_REGNUM
Definition: cris-tdep.c:121
showlist
struct cmd_list_element * showlist
Definition: cli-cmds.c:119
struct_return
struct_return
Definition: arm-tdep.h:88
cris_get_quick_value
static int cris_get_quick_value(unsigned short insn)
Definition: cris-tdep.c:573
frame.h
cris_cannot_store_register
static int cris_cannot_store_register(struct gdbarch *gdbarch, int regno)
Definition: cris-tdep.c:1518
reg_mode_move_from_preg_op
static void reg_mode_move_from_preg_op(unsigned short inst, inst_env_type *inst_env)
Definition: cris-tdep.c:2966
SIGNED_QUICK_VALUE_MASK
Definition: cris-tdep.c:529
gdbarch_byte_order
enum bfd_endian gdbarch_byte_order(struct gdbarch *gdbarch)
Definition: gdbarch.c:1509
cris_gdbarch_init
static struct gdbarch * cris_gdbarch_init(struct gdbarch_info, struct gdbarch_list *)
Definition: cris-tdep.c:3970
inferior.h
S6_REGNUM
Definition: cris-tdep.c:132
none_reg_mode_jump_op
static void none_reg_mode_jump_op(unsigned short inst, inst_env_type *inst_env)
Definition: cris-tdep.c:2808
TYPE_CODE_UNION
Definition: gdbtypes.h:107
set_gdbarch_cannot_store_register
void set_gdbarch_cannot_store_register(struct gdbarch *gdbarch, gdbarch_cannot_store_register_ftype cannot_store_register)
Definition: gdbarch.c:2548
version
const char version[]
Definition: version.c:2
gdbarch_tdep::cris_mode
const char * cris_mode
Definition: cris-tdep.h:30
handle_inc_and_index_mode_for_aritm_op
static void handle_inc_and_index_mode_for_aritm_op(unsigned short inst, inst_env_type *inst_env)
Definition: cris-tdep.c:3467
cris_is_signed_extend_bit_on
static int cris_is_signed_extend_bit_on(unsigned short insn)
Definition: cris-tdep.c:603
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static struct cris_unwind_cache * cris_sigtramp_frame_unwind_cache(struct frame_info *this_frame, void **this_cache)
Definition: cris-tdep.c:311
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Definition: gdbtypes.h:749
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int find_pc_partial_function(CORE_ADDR pc, const char **name, CORE_ADDR *address, CORE_ADDR *endaddr)
Definition: blockframe.c:320
BAR_REGNUM
Definition: cris-tdep.c:104
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static struct value * cris_sigtramp_frame_prev_register(struct frame_info *this_frame, void **this_cache, int regnum)
Definition: cris-tdep.c:418
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static const unsigned short rt_sigtramp_code[]
Definition: cris-tdep.c:185
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struct type * builtin_int0
Definition: gdbtypes.h:1533
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struct trad_frame_saved_reg * saved_regs
Definition: cris-tdep.c:307
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struct type * builtin_uint32
Definition: gdbtypes.h:1539
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int default_frame_sniffer(const struct frame_unwind *self, struct frame_info *this_frame, void **this_prologue_cache)
Definition: frame-unwind.c:174
DCCR_REGNUM
Definition: cris-tdep.c:105
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static void bdap_prefix(unsigned short inst, inst_env_type *inst_env)
Definition: cris-tdep.c:2165
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unsigned long preg[NUM_SPECREGS]
Definition: cris-tdep.c:477
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Definition: cris-tdep.c:2705
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mach_port_t mach_port_t name mach_port_t mach_port_t name kern_return_t int status
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cris_prefix_addressing_modes
Definition: cris-tdep.c:510
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int invalid
Definition: cris-tdep.c:483
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Definition: cris-tdep.c:2476
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long
Definition: bound_registers.py:24
ACR_REGNUM
Definition: cris-tdep.c:110
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void deprecated_add_core_fns(struct core_fns *cf)
Definition: corelow.c:102
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int cris_dwarf2_cfi
Definition: cris-tdep.h:31
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Definition: cris-tdep.c:2562
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Definition: cris-tdep.c:3792
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Definition: cris-tdep.c:181
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struct gdbarch * gdbarch
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Definition: cris-tdep.c:736
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Definition: cris-tdep.c:98
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Definition: aarch64-tdep.c:77
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Definition: frame-base.h:58
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static int cris_dwarf2_reg_to_regnum(struct gdbarch *gdbarch, int reg)
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unsigned int cris_version
Definition: cris-tdep.h:29
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ULONGEST get_frame_register_unsigned(struct frame_info *frame, int regnum)
Definition: frame.c:1308
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Definition: cris-tdep.c:107
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TYPE_CODE_STRUCT
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int delay_slot_pc_active
Definition: cris-tdep.c:485
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static void cris_supply_gregset(struct regcache *regcache, cris_elf_gregset_t *gregsetp)
Definition: cris-tdep.c:3801
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void set_gdbarch_breakpoint_kind_from_pc(struct gdbarch *gdbarch, gdbarch_breakpoint_kind_from_pc_ftype breakpoint_kind_from_pc)
Definition: gdbarch.c:2871
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struct trad_frame_saved_reg * trad_frame_alloc_saved_regs(struct gdbarch *gdbarch)
Definition: trad-frame.c:47
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static const char * cris_special_register_name(struct gdbarch *gdbarch, int regno)
Definition: cris-tdep.c:1673
INDIRECT_MODE
Definition: cris-tdep.c:505
NUM_FREGS
Definition: cris-tdep.c:52
reg
Definition: regdef.h:22
CRISV32_ELF_NGREG
#define CRISV32_ELF_NGREG
Definition: cris-tdep.c:3795
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static void scc_op(unsigned short inst, inst_env_type *inst_env)
Definition: cris-tdep.c:2768
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Definition: value.c:169
STR_REGNUM
Definition: cris-tdep.c:85
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void set_gdbarch_software_single_step(struct gdbarch *gdbarch, gdbarch_software_single_step_ftype software_single_step)
Definition: gdbarch.c:3258
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static void none_reg_mode_move_from_preg_op(struct gdbarch *gdbarch, unsigned short inst, inst_env_type *inst_env)
Definition: cris-tdep.c:2910
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LONGEST addr
Definition: trad-frame.h:83
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static int cris_cannot_fetch_register(struct gdbarch *gdbarch, int regno)
Definition: cris-tdep.c:1508
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void set_gdbarch_push_dummy_code(struct gdbarch *gdbarch, gdbarch_push_dummy_code_ftype push_dummy_code)
Definition: gdbarch.c:2422
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Definition: symtab.h:1746
SRS_REGNUM
Definition: cris-tdep.c:113
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int prefix_found
Definition: cris-tdep.c:482
S2_REGNUM
Definition: cris-tdep.c:128
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static int cris_get_mode(unsigned short insn)
Definition: cris-tdep.c:547
quick_mode_and_cmp_move_or_op
static void quick_mode_and_cmp_move_or_op(unsigned short inst, inst_env_type *inst_env)
Definition: cris-tdep.c:3587
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int core_addr_lessthan(CORE_ADDR lhs, CORE_ADDR rhs)
Definition: arch-utils.c:117
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bfd_byte gdb_byte
Definition: common-types.h:38
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int xflag_found
Definition: cris-tdep.c:486
MOF_REGNUM
Definition: cris-tdep.c:94
three_operand_bound_op
static void three_operand_bound_op(unsigned short inst, inst_env_type *inst_env)
Definition: cris-tdep.c:2595
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static void cris_sigtramp_frame_this_id(struct frame_info *this_frame, void **this_cache, struct frame_id *this_id)
Definition: cris-tdep.c:405
reg_mode_jump_op
static void reg_mode_jump_op(unsigned short inst, inst_env_type *inst_env)
Definition: cris-tdep.c:2787
constraint
static int constraint(unsigned int insn, const char *inst_args, inst_env_type *inst_env)
Definition: cris-tdep.c:1863
cris_unwind_cache
Definition: cris-tdep.c:287
muls_op
static void muls_op(unsigned short inst, inst_env_type *inst_env)
Definition: cris-tdep.c:3137
three_operand_add_sub_cmp_and_or_op
static void three_operand_add_sub_cmp_and_or_op(unsigned short inst, inst_env_type *inst_env)
Definition: cris-tdep.c:3410
S3_REGNUM
Definition: cris-tdep.c:129
S0_REGNUM
Definition: cris-tdep.c:126
dwarf2-frame.h
quick_mode_bdap_prefix
static void quick_mode_bdap_prefix(unsigned short inst, inst_env_type *inst_env)
Definition: cris-tdep.c:2103
S10_REGNUM
Definition: cris-tdep.c:136
cris_spec_regs
const struct cris_spec_reg cris_spec_regs[]
cris_get_size
static int cris_get_size(unsigned short insn)
Definition: cris-tdep.c:559
gdb_stderr
#define gdb_stderr
Definition: utils.h:344
PID_REGNUM
Definition: cris-tdep.c:112
XCNEW
#define XCNEW(T)
Definition: poison.h:121
crisv32_cannot_store_register
static int crisv32_cannot_store_register(struct gdbarch *gdbarch, int regno)
Definition: cris-tdep.c:1559
gdbcore.h
cris_is_xflag_bit_on
static int cris_is_xflag_bit_on(unsigned short insn)
Definition: cris-tdep.c:609
TYPE_CODE
#define TYPE_CODE(thistype)
Definition: gdbtypes.h:1238
regcache_cooked_write_unsigned
void regcache_cooked_write_unsigned(struct regcache *regcache, int regnum, ULONGEST val)
Definition: regcache.c:806
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void gdbarch_info_init(struct gdbarch_info *info)
Definition: arch-utils.c:725
crisv32_scan_prologue
static CORE_ADDR crisv32_scan_prologue(CORE_ADDR pc, struct frame_info *this_frame, struct cris_unwind_cache *info)
Definition: cris-tdep.c:1307
builtin_type::builtin_data_ptr
struct type * builtin_data_ptr
Definition: gdbtypes.h:1554
CRIS_FP_REGNUM
Definition: cris-tdep.c:83
handle_prefix_index_mode_for_aritm_op
static void handle_prefix_index_mode_for_aritm_op(unsigned short inst, inst_env_type *inst_env)
Definition: cris-tdep.c:3439
EXS_REGNUM
Definition: cris-tdep.c:115
S5_REGNUM
Definition: cris-tdep.c:131
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static void abs_op(unsigned short inst, inst_env_type *inst_env)
Definition: cris-tdep.c:2337
SIGTRAMP_OFFSET1
#define SIGTRAMP_OFFSET1
Definition: cris-tdep.c:173
offset
int offset
Definition: agent.c:65
CRISV32PC_REGNUM
Definition: cris-tdep.c:124
add_setshow_boolean_cmd
void add_setshow_boolean_cmd(const char *name, enum command_class theclass, int *var, const char *set_doc, const char *show_doc, const char *help_doc, cmd_const_sfunc_ftype *set_func, show_value_ftype *show_func, struct cmd_list_element **set_list, struct cmd_list_element **show_list)
Definition: cli-decode.c:569
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int uses_frame
Definition: cris-tdep.c:300
get_frame_register
void get_frame_register(struct frame_info *frame, int regnum, gdb_byte *buf)
Definition: frame.c:1165
BRP_REGNUM
Definition: cris-tdep.c:106
regcache::arch
gdbarch * arch() const
Definition: regcache.c:221
dwarf2_append_unwinders
void dwarf2_append_unwinders(struct gdbarch *gdbarch)
Definition: dwarf2-frame.c:1384
SIGNED_EXTEND_BIT_MASK
Definition: cris-tdep.c:523
symtab_and_line::pc
CORE_ADDR pc
Definition: symtab.h:1759
PREFIX_OFFSET_MODE
Definition: cris-tdep.c:516
target.h
cris_elf_core_fns
static struct core_fns cris_elf_core_fns
Definition: cris-tdep.c:3860
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static CORE_ADDR cris_unwind_pc(struct gdbarch *gdbarch, struct frame_info *next_frame)
Definition: cris-tdep.c:1377
value.h
frame_unwind
Definition: frame-unwind.h:144
cris_frame_unwind_cache
static struct cris_unwind_cache * cris_frame_unwind_cache(struct frame_info *this_frame, void **this_prologue_cache)
Definition: cris-tdep.c:699
cris_regnums
cris_regnums
Definition: cris-tdep.c:79
process_autoincrement
static void process_autoincrement(int size, unsigned short inst, inst_env_type *inst_env)
Definition: cris-tdep.c:2127
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static const struct frame_unwind cris_sigtramp_frame_unwind
Definition: cris-tdep.c:438
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static int find_step_target(struct regcache *regcache, inst_env_type *inst_env)
Definition: cris-tdep.c:1992
PREFIX_ASSIGN_MODE
Definition: cris-tdep.c:513
DWARF2_FRAME_REG_RA
Definition: dwarf2-frame.h:62
regcache_raw_supply
void regcache_raw_supply(struct regcache *regcache, int regnum, const void *buf)
Definition: regcache.c:1004
CCR_REGNUM
Definition: cris-tdep.c:100
SPC_REGNUM
Definition: cris-tdep.c:123
gdbtypes.h
VR_REGNUM
Definition: cris-tdep.c:93
S14_REGNUM
Definition: cris-tdep.c:140
btst_nop_op
static void btst_nop_op(unsigned short inst, inst_env_type *inst_env)
Definition: cris-tdep.c:2613
ULONGEST
unsigned long long ULONGEST
Definition: common-types.h:53
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enum unwind_stop_reason default_frame_unwind_stop_reason(struct frame_info *this_frame, void **this_cache)
Definition: frame-unwind.c:184
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int disable_interrupt
Definition: cris-tdep.c:487
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void _initialize_cris_tdep(void)
Definition: cris-tdep.c:3870
cris_push_dummy_call
static CORE_ADDR cris_push_dummy_call(struct gdbarch *gdbarch, struct value *function, struct regcache *regcache, CORE_ADDR bp_addr, int nargs, struct value **args, CORE_ADDR sp, int struct_return, CORE_ADDR struct_addr)
Definition: cris-tdep.c:808
crisv32_cannot_fetch_register
static int crisv32_cannot_fetch_register(struct gdbarch *gdbarch, int regno)
Definition: cris-tdep.c:1549
ARG2_REGNUM
Definition: cris-tdep.c:88
regcache
Definition: regcache.h:232
usr_cmd_cris_version_valid
static int usr_cmd_cris_version_valid
Definition: cris-tdep.c:151
S11_REGNUM
Definition: cris-tdep.c:137
gdbarch_info
Definition: gdbarch.h:1626
set_gdbarch_long_double_bit
void set_gdbarch_long_double_bit(struct gdbarch *gdbarch, int long_double_bit)
Definition: gdbarch.c:1756
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static int cris_get_operand2(unsigned short insn)
Definition: cris-tdep.c:541
value_type
struct type * value_type(const struct value *value)
Definition: value.c:1095
cris_sigcontext_addr
static CORE_ADDR cris_sigcontext_addr(struct frame_info *this_frame)
Definition: cris-tdep.c:251
SRP_REGNUM
Definition: cris-tdep.c:95
move_mem_to_reg_movem_op
static void move_mem_to_reg_movem_op(unsigned short inst, inst_env_type *inst_env)
Definition: cris-tdep.c:3001
NRP_REGNUM
Definition: cris-tdep.c:120
set_gdbarch_return_value
void set_gdbarch_return_value(struct gdbarch *gdbarch, gdbarch_return_value_ftype return_value)
Definition: gdbarch.c:2738
dwarf2_frame_set_init_reg
void dwarf2_frame_set_init_reg(struct gdbarch *gdbarch, void(*init_reg)(struct gdbarch *, int, struct dwarf2_frame_state_reg *, struct frame_info *))
Definition: dwarf2-frame.c:743
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static CORE_ADDR cris_scan_prologue(CORE_ADDR pc, struct frame_info *this_frame, struct cris_unwind_cache *info)
Definition: cris-tdep.c:1023
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int gdbarch_pc_regnum(struct gdbarch *gdbarch)
Definition: gdbarch.c:2163
SIGTRAMP_INSN1
#define SIGTRAMP_INSN1
Definition: cris-tdep.c:172
instruction_environment::branch_break_address
unsigned long branch_break_address
Definition: cris-tdep.c:478
S7_REGNUM
Definition: cris-tdep.c:133
cris_unwind_cache::prev_sp
CORE_ADDR prev_sp
Definition: cris-tdep.c:291
add_sub_cmp_and_or_move_action
static void add_sub_cmp_and_or_move_action(unsigned short inst, inst_env_type *inst_env, unsigned long source1, unsigned long source2)
Definition: cris-tdep.c:3186
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#define TYPE_LENGTH(thistype)
Definition: gdbtypes.h:1235
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cris_addressing_modes
Definition: cris-tdep.c:502
set_gdbarch_push_dummy_call
void set_gdbarch_push_dummy_call(struct gdbarch *gdbarch, gdbarch_push_dummy_call_ftype push_dummy_call)
Definition: gdbarch.c:2381
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static int cris_sigtramp_frame_sniffer(const struct frame_unwind *self, struct frame_info *this_frame, void **this_cache)
Definition: cris-tdep.c:427
BRANCH_SIGNED_SHORT_OFFSET_MASK
Definition: cris-tdep.c:522
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ULONGEST read_memory_unsigned_integer(CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
Definition: corefile.c:326
in_inclusive_range
static bool in_inclusive_range(T value, T low, T high)
Definition: common-utils.h:144
set_cris_dwarf2_cfi
static void set_cris_dwarf2_cfi(const char *ignore_args, int from_tty, struct cmd_list_element *c)
Definition: cris-tdep.c:3957
cris_software_single_step
static std::vector< CORE_ADDR > cris_software_single_step(struct regcache *regcache)
Definition: cris-tdep.c:2064
clearf_di_op
static void clearf_di_op(unsigned short inst, inst_env_type *inst_env)
Definition: cris-tdep.c:2631
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static void mulu_op(unsigned short inst, inst_env_type *inst_env)
Definition: cris-tdep.c:3161
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static void cris_dump_tdep(struct gdbarch *, struct ui_file *)
Definition: cris-tdep.c:3914
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void set_gdbarch_sw_breakpoint_from_kind(struct gdbarch *gdbarch, gdbarch_sw_breakpoint_from_kind_ftype sw_breakpoint_from_kind)
Definition: gdbarch.c:2888
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void write_memory(CORE_ADDR memaddr, const bfd_byte *myaddr, ssize_t len)
Definition: corefile.c:394
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void set_gdbarch_skip_prologue(struct gdbarch *gdbarch, gdbarch_skip_prologue_ftype skip_prologue)
Definition: gdbarch.c:2772
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static void xor_op(unsigned short inst, inst_env_type *inst_env)
Definition: cris-tdep.c:3108
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static void not_implemented_op(unsigned short inst, inst_env_type *inst_env)
Definition: cris-tdep.c:3100
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unsigned long reg[NUM_GENREGS]
Definition: cris-tdep.c:476
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static void asr_op(unsigned short inst, inst_env_type *inst_env)
Definition: cris-tdep.c:2398
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enum bfd_endian byte_order
Definition: gdbarch.h:1632
cris_skip_prologue
static CORE_ADDR cris_skip_prologue(struct gdbarch *gdbarch, CORE_ADDR pc)
Definition: cris-tdep.c:1352
RETURN_VALUE_REGISTER_CONVENTION
Definition: defs.h:251
gdbarch::byte_order
enum bfd_endian byte_order
Definition: gdbarch.c:137
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void set_gdbarch_pc_regnum(struct gdbarch *gdbarch, int pc_regnum)
Definition: gdbarch.c:2173
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static CORE_ADDR cris_unwind_sp(struct gdbarch *gdbarch, struct frame_info *next_frame)
Definition: cris-tdep.c:1386
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trad_frame_saved_reg
Definition: trad-frame.h:81
set_gdbarch_register_name
void set_gdbarch_register_name(struct gdbarch *gdbarch, gdbarch_register_name_ftype register_name)
Definition: gdbarch.c:2292
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static struct type * cris_register_type(struct gdbarch *gdbarch, int regno)
Definition: cris-tdep.c:1590
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Definition: frame.c:1001
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Definition: corelow.c:113
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Definition: cris-tdep.c:139
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static const char cris_mode_guru[]
Definition: cris-tdep.c:154
INST_WORD_SIZE
Definition: cris-tdep.c:497
error
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Definition: errors.c:38
SIGNED_DWORD_MASK
Definition: cris-tdep.c:528
size
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Definition: go32-nat.c:242
S12_REGNUM
Definition: cris-tdep.c:138
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struct gdbarch * gdbarch_alloc(const struct gdbarch_info *info, struct gdbarch_tdep *tdep)
Definition: gdbarch.c:361
set_gdbarch_inner_than
void set_gdbarch_inner_than(struct gdbarch *gdbarch, gdbarch_inner_than_ftype inner_than)
Definition: gdbarch.c:2837
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static signed char cris_get_signed_offset(unsigned short insn)
Definition: cris-tdep.c:622
frame_id
Definition: frame.h:111
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struct gdbarch * get_frame_arch(struct frame_info *this_frame)
Definition: frame.c:2691
LONGEST
long long LONGEST
Definition: common-types.h:52
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int leaf_function
Definition: cris-tdep.c:304
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static int crisv32_single_step_through_delay(struct gdbarch *gdbarch, struct frame_info *this_frame)
Definition: cris-tdep.c:449
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void regcache_cooked_write(struct regcache *regcache, int regnum, const gdb_byte *buf)
Definition: regcache.c:873
REGISTER_MODE
Definition: cris-tdep.c:504
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static const struct frame_base cris_frame_base
Definition: cris-tdep.c:938
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static void store_unsigned_integer(gdb_byte *addr, int len, enum bfd_endian byte_order, ULONGEST val)
Definition: defs.h:604
SIGNED_BYTE_MASK
Definition: cris-tdep.c:524
number_of_bits
static int number_of_bits(unsigned int value)
Definition: cris-tdep.c:1937
DZ_REGNUM
Definition: cris-tdep.c:117
INST_DWORD_SIZE
Definition: cris-tdep.c:498
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Definition: gdbarch.h:1620