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/tmp/gdb-8.1/gdb/i386-tdep.c
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1 /* Intel 386 target-dependent stuff.
2
3 Copyright (C) 1988-2018 Free Software Foundation, Inc.
4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19
20 #include "defs.h"
21 #include "opcode/i386.h"
22 #include "arch-utils.h"
23 #include "command.h"
24 #include "dummy-frame.h"
25 #include "dwarf2-frame.h"
26 #include "frame.h"
27 #include "frame-base.h"
28 #include "frame-unwind.h"
29 #include "inferior.h"
30 #include "infrun.h"
31 #include "gdbcmd.h"
32 #include "gdbcore.h"
33 #include "gdbtypes.h"
34 #include "objfiles.h"
35 #include "osabi.h"
36 #include "regcache.h"
37 #include "reggroups.h"
38 #include "regset.h"
39 #include "symfile.h"
40 #include "symtab.h"
41 #include "target.h"
42 #include "target-float.h"
43 #include "value.h"
44 #include "dis-asm.h"
45 #include "disasm.h"
46 #include "remote.h"
47 #include "i386-tdep.h"
48 #include "i387-tdep.h"
49 #include "x86-xstate.h"
50
51 #include "record.h"
52 #include "record-full.h"
53 #include "target-descriptions.h"
54 #include "arch/i386.h"
55
56 #include "ax.h"
57 #include "ax-gdb.h"
58
59 #include "stap-probe.h"
60 #include "user-regs.h"
61 #include "cli/cli-utils.h"
62 #include "expression.h"
63 #include "parser-defs.h"
64 #include <ctype.h>
65 #include <algorithm>
66
67 /* Register names. */
68
69 static const char *i386_register_names[] =
70 {
71 "eax", "ecx", "edx", "ebx",
72 "esp", "ebp", "esi", "edi",
73 "eip", "eflags", "cs", "ss",
74 "ds", "es", "fs", "gs",
75 "st0", "st1", "st2", "st3",
76 "st4", "st5", "st6", "st7",
77 "fctrl", "fstat", "ftag", "fiseg",
78 "fioff", "foseg", "fooff", "fop",
79 "xmm0", "xmm1", "xmm2", "xmm3",
80 "xmm4", "xmm5", "xmm6", "xmm7",
81 "mxcsr"
82 };
83
84 static const char *i386_zmm_names[] =
85 {
86 "zmm0", "zmm1", "zmm2", "zmm3",
87 "zmm4", "zmm5", "zmm6", "zmm7"
88 };
89
90 static const char *i386_zmmh_names[] =
91 {
92 "zmm0h", "zmm1h", "zmm2h", "zmm3h",
93 "zmm4h", "zmm5h", "zmm6h", "zmm7h"
94 };
95
96 static const char *i386_k_names[] =
97 {
98 "k0", "k1", "k2", "k3",
99 "k4", "k5", "k6", "k7"
100 };
101
102 static const char *i386_ymm_names[] =
103 {
104 "ymm0", "ymm1", "ymm2", "ymm3",
105 "ymm4", "ymm5", "ymm6", "ymm7",
106 };
107
108 static const char *i386_ymmh_names[] =
109 {
110 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
111 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
112 };
113
114 static const char *i386_mpx_names[] =
115 {
116 "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus"
117 };
118
119 static const char* i386_pkeys_names[] =
120 {
121 "pkru"
122 };
123
124 /* Register names for MPX pseudo-registers. */
125
126 static const char *i386_bnd_names[] =
127 {
128 "bnd0", "bnd1", "bnd2", "bnd3"
129 };
130
131 /* Register names for MMX pseudo-registers. */
132
133 static const char *i386_mmx_names[] =
134 {
135 "mm0", "mm1", "mm2", "mm3",
136 "mm4", "mm5", "mm6", "mm7"
137 };
138
139 /* Register names for byte pseudo-registers. */
140
141 static const char *i386_byte_names[] =
142 {
143 "al", "cl", "dl", "bl",
144 "ah", "ch", "dh", "bh"
145 };
146
147 /* Register names for word pseudo-registers. */
148
149 static const char *i386_word_names[] =
150 {
151 "ax", "cx", "dx", "bx",
152 "", "bp", "si", "di"
153 };
154
155 /* Constant used for reading/writing pseudo registers. In 64-bit mode, we have
156 16 lower ZMM regs that extend corresponding xmm/ymm registers. In addition,
157 we have 16 upper ZMM regs that have to be handled differently. */
158
159 const int num_lower_zmm_regs = 16;
160
161 /* MMX register? */
162
163 static int
164 i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum)
165 {
166 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
167 int mm0_regnum = tdep->mm0_regnum;
168
169 if (mm0_regnum < 0)
170 return 0;
171
172 regnum -= mm0_regnum;
173 return regnum >= 0 && regnum < tdep->num_mmx_regs;
174 }
175
176 /* Byte register? */
177
178 int
179 i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum)
180 {
181 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
182
183 regnum -= tdep->al_regnum;
184 return regnum >= 0 && regnum < tdep->num_byte_regs;
185 }
186
187 /* Word register? */
188
189 int
190 i386_word_regnum_p (struct gdbarch *gdbarch, int regnum)
191 {
192 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
193
194 regnum -= tdep->ax_regnum;
195 return regnum >= 0 && regnum < tdep->num_word_regs;
196 }
197
198 /* Dword register? */
199
200 int
201 i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum)
202 {
203 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
204 int eax_regnum = tdep->eax_regnum;
205
206 if (eax_regnum < 0)
207 return 0;
208
209 regnum -= eax_regnum;
210 return regnum >= 0 && regnum < tdep->num_dword_regs;
211 }
212
213 /* AVX512 register? */
214
215 int
216 i386_zmmh_regnum_p (struct gdbarch *gdbarch, int regnum)
217 {
218 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
219 int zmm0h_regnum = tdep->zmm0h_regnum;
220
221 if (zmm0h_regnum < 0)
222 return 0;
223
224 regnum -= zmm0h_regnum;
225 return regnum >= 0 && regnum < tdep->num_zmm_regs;
226 }
227
228 int
229 i386_zmm_regnum_p (struct gdbarch *gdbarch, int regnum)
230 {
231 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
232 int zmm0_regnum = tdep->zmm0_regnum;
233
234 if (zmm0_regnum < 0)
235 return 0;
236
237 regnum -= zmm0_regnum;
238 return regnum >= 0 && regnum < tdep->num_zmm_regs;
239 }
240
241 int
242 i386_k_regnum_p (struct gdbarch *gdbarch, int regnum)
243 {
244 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
245 int k0_regnum = tdep->k0_regnum;
246
247 if (k0_regnum < 0)
248 return 0;
249
250 regnum -= k0_regnum;
251 return regnum >= 0 && regnum < I387_NUM_K_REGS;
252 }
253
254 static int
255 i386_ymmh_regnum_p (struct gdbarch *gdbarch, int regnum)
256 {
257 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
258 int ymm0h_regnum = tdep->ymm0h_regnum;
259
260 if (ymm0h_regnum < 0)
261 return 0;
262
263 regnum -= ymm0h_regnum;
264 return regnum >= 0 && regnum < tdep->num_ymm_regs;
265 }
266
267 /* AVX register? */
268
269 int
270 i386_ymm_regnum_p (struct gdbarch *gdbarch, int regnum)
271 {
272 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
273 int ymm0_regnum = tdep->ymm0_regnum;
274
275 if (ymm0_regnum < 0)
276 return 0;
277
278 regnum -= ymm0_regnum;
279 return regnum >= 0 && regnum < tdep->num_ymm_regs;
280 }
281
282 static int
283 i386_ymmh_avx512_regnum_p (struct gdbarch *gdbarch, int regnum)
284 {
285 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
286 int ymm16h_regnum = tdep->ymm16h_regnum;
287
288 if (ymm16h_regnum < 0)
289 return 0;
290
291 regnum -= ymm16h_regnum;
292 return regnum >= 0 && regnum < tdep->num_ymm_avx512_regs;
293 }
294
295 int
296 i386_ymm_avx512_regnum_p (struct gdbarch *gdbarch, int regnum)
297 {
298 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
299 int ymm16_regnum = tdep->ymm16_regnum;
300
301 if (ymm16_regnum < 0)
302 return 0;
303
304 regnum -= ymm16_regnum;
305 return regnum >= 0 && regnum < tdep->num_ymm_avx512_regs;
306 }
307
308 /* BND register? */
309
310 int
311 i386_bnd_regnum_p (struct gdbarch *gdbarch, int regnum)
312 {
313 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
314 int bnd0_regnum = tdep->bnd0_regnum;
315
316 if (bnd0_regnum < 0)
317 return 0;
318
319 regnum -= bnd0_regnum;
320 return regnum >= 0 && regnum < I387_NUM_BND_REGS;
321 }
322
323 /* SSE register? */
324
325 int
326 i386_xmm_regnum_p (struct gdbarch *gdbarch, int regnum)
327 {
328 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
329 int num_xmm_regs = I387_NUM_XMM_REGS (tdep);
330
331 if (num_xmm_regs == 0)
332 return 0;
333
334 regnum -= I387_XMM0_REGNUM (tdep);
335 return regnum >= 0 && regnum < num_xmm_regs;
336 }
337
338 /* XMM_512 register? */
339
340 int
341 i386_xmm_avx512_regnum_p (struct gdbarch *gdbarch, int regnum)
342 {
343 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
344 int num_xmm_avx512_regs = I387_NUM_XMM_AVX512_REGS (tdep);
345
346 if (num_xmm_avx512_regs == 0)
347 return 0;
348
349 regnum -= I387_XMM16_REGNUM (tdep);
350 return regnum >= 0 && regnum < num_xmm_avx512_regs;
351 }
352
353 static int
354 i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum)
355 {
356 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
357
358 if (I387_NUM_XMM_REGS (tdep) == 0)
359 return 0;
360
361 return (regnum == I387_MXCSR_REGNUM (tdep));
362 }
363
364 /* FP register? */
365
366 int
367 i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum)
368 {
369 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
370
371 if (I387_ST0_REGNUM (tdep) < 0)
372 return 0;
373
374 return (I387_ST0_REGNUM (tdep) <= regnum
375 && regnum < I387_FCTRL_REGNUM (tdep));
376 }
377
378 int
379 i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum)
380 {
381 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
382
383 if (I387_ST0_REGNUM (tdep) < 0)
384 return 0;
385
386 return (I387_FCTRL_REGNUM (tdep) <= regnum
387 && regnum < I387_XMM0_REGNUM (tdep));
388 }
389
390 /* BNDr (raw) register? */
391
392 static int
393 i386_bndr_regnum_p (struct gdbarch *gdbarch, int regnum)
394 {
395 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
396
397 if (I387_BND0R_REGNUM (tdep) < 0)
398 return 0;
399
400 regnum -= tdep->bnd0r_regnum;
401 return regnum >= 0 && regnum < I387_NUM_BND_REGS;
402 }
403
404 /* BND control register? */
405
406 static int
407 i386_mpx_ctrl_regnum_p (struct gdbarch *gdbarch, int regnum)
408 {
409 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
410
411 if (I387_BNDCFGU_REGNUM (tdep) < 0)
412 return 0;
413
414 regnum -= I387_BNDCFGU_REGNUM (tdep);
415 return regnum >= 0 && regnum < I387_NUM_MPX_CTRL_REGS;
416 }
417
418 /* PKRU register? */
419
420 bool
421 i386_pkru_regnum_p (struct gdbarch *gdbarch, int regnum)
422 {
423 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
424 int pkru_regnum = tdep->pkru_regnum;
425
426 if (pkru_regnum < 0)
427 return false;
428
429 regnum -= pkru_regnum;
430 return regnum >= 0 && regnum < I387_NUM_PKEYS_REGS;
431 }
432
433 /* Return the name of register REGNUM, or the empty string if it is
434 an anonymous register. */
435
436 static const char *
437 i386_register_name (struct gdbarch *gdbarch, int regnum)
438 {
439 /* Hide the upper YMM registers. */
440 if (i386_ymmh_regnum_p (gdbarch, regnum))
441 return "";
442
443 /* Hide the upper YMM16-31 registers. */
444 if (i386_ymmh_avx512_regnum_p (gdbarch, regnum))
445 return "";
446
447 /* Hide the upper ZMM registers. */
448 if (i386_zmmh_regnum_p (gdbarch, regnum))
449 return "";
450
451 return tdesc_register_name (gdbarch, regnum);
452 }
453
454 /* Return the name of register REGNUM. */
455
456 const char *
457 i386_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
458 {
459 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
460 if (i386_bnd_regnum_p (gdbarch, regnum))
461 return i386_bnd_names[regnum - tdep->bnd0_regnum];
462 if (i386_mmx_regnum_p (gdbarch, regnum))
463 return i386_mmx_names[regnum - I387_MM0_REGNUM (tdep)];
464 else if (i386_ymm_regnum_p (gdbarch, regnum))
465 return i386_ymm_names[regnum - tdep->ymm0_regnum];
466 else if (i386_zmm_regnum_p (gdbarch, regnum))
467 return i386_zmm_names[regnum - tdep->zmm0_regnum];
468 else if (i386_byte_regnum_p (gdbarch, regnum))
469 return i386_byte_names[regnum - tdep->al_regnum];
470 else if (i386_word_regnum_p (gdbarch, regnum))
471 return i386_word_names[regnum - tdep->ax_regnum];
472
473 internal_error (__FILE__, __LINE__, _("invalid regnum"));
474 }
475
476 /* Convert a dbx register number REG to the appropriate register
477 number used by GDB. */
478
479 static int
480 i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg)
481 {
482 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
483
484 /* This implements what GCC calls the "default" register map
485 (dbx_register_map[]). */
486
487 if (reg >= 0 && reg <= 7)
488 {
489 /* General-purpose registers. The debug info calls %ebp
490 register 4, and %esp register 5. */
491 if (reg == 4)
492 return 5;
493 else if (reg == 5)
494 return 4;
495 else return reg;
496 }
497 else if (reg >= 12 && reg <= 19)
498 {
499 /* Floating-point registers. */
500 return reg - 12 + I387_ST0_REGNUM (tdep);
501 }
502 else if (reg >= 21 && reg <= 28)
503 {
504 /* SSE registers. */
505 int ymm0_regnum = tdep->ymm0_regnum;
506
507 if (ymm0_regnum >= 0
508 && i386_xmm_regnum_p (gdbarch, reg))
509 return reg - 21 + ymm0_regnum;
510 else
511 return reg - 21 + I387_XMM0_REGNUM (tdep);
512 }
513 else if (reg >= 29 && reg <= 36)
514 {
515 /* MMX registers. */
516 return reg - 29 + I387_MM0_REGNUM (tdep);
517 }
518
519 /* This will hopefully provoke a warning. */
520 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
521 }
522
523 /* Convert SVR4 DWARF register number REG to the appropriate register number
524 used by GDB. */
525
526 static int
527 i386_svr4_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
528 {
529 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
530
531 /* This implements the GCC register map that tries to be compatible
532 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
533
534 /* The SVR4 register numbering includes %eip and %eflags, and
535 numbers the floating point registers differently. */
536 if (reg >= 0 && reg <= 9)
537 {
538 /* General-purpose registers. */
539 return reg;
540 }
541 else if (reg >= 11 && reg <= 18)
542 {
543 /* Floating-point registers. */
544 return reg - 11 + I387_ST0_REGNUM (tdep);
545 }
546 else if (reg >= 21 && reg <= 36)
547 {
548 /* The SSE and MMX registers have the same numbers as with dbx. */
549 return i386_dbx_reg_to_regnum (gdbarch, reg);
550 }
551
552 switch (reg)
553 {
554 case 37: return I387_FCTRL_REGNUM (tdep);
555 case 38: return I387_FSTAT_REGNUM (tdep);
556 case 39: return I387_MXCSR_REGNUM (tdep);
557 case 40: return I386_ES_REGNUM;
558 case 41: return I386_CS_REGNUM;
559 case 42: return I386_SS_REGNUM;
560 case 43: return I386_DS_REGNUM;
561 case 44: return I386_FS_REGNUM;
562 case 45: return I386_GS_REGNUM;
563 }
564
565 return -1;
566 }
567
568 /* Wrapper on i386_svr4_dwarf_reg_to_regnum to return
569 num_regs + num_pseudo_regs for other debug formats. */
570
571 int
572 i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg)
573 {
574 int regnum = i386_svr4_dwarf_reg_to_regnum (gdbarch, reg);
575
576 if (regnum == -1)
577 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
578 return regnum;
579 }
580
581
582
583 /* This is the variable that is set with "set disassembly-flavor", and
584 its legitimate values. */
585 static const char att_flavor[] = "att";
586 static const char intel_flavor[] = "intel";
587 static const char *const valid_flavors[] =
588 {
589 att_flavor,
590 intel_flavor,
591 NULL
592 };
593 static const char *disassembly_flavor = att_flavor;
594
595
596 /* Use the program counter to determine the contents and size of a
597 breakpoint instruction. Return a pointer to a string of bytes that
598 encode a breakpoint instruction, store the length of the string in
599 *LEN and optionally adjust *PC to point to the correct memory
600 location for inserting the breakpoint.
601
602 On the i386 we have a single breakpoint that fits in a single byte
603 and can be inserted anywhere.
604
605 This function is 64-bit safe. */
606
607 constexpr gdb_byte i386_break_insn[] = { 0xcc }; /* int 3 */
608
609 typedef BP_MANIPULATION (i386_break_insn) i386_breakpoint;
610
611
612 /* Displaced instruction handling. */
613
614 /* Skip the legacy instruction prefixes in INSN.
615 Not all prefixes are valid for any particular insn
616 but we needn't care, the insn will fault if it's invalid.
617 The result is a pointer to the first opcode byte,
618 or NULL if we run off the end of the buffer. */
619
620 static gdb_byte *
621 i386_skip_prefixes (gdb_byte *insn, size_t max_len)
622 {
623 gdb_byte *end = insn + max_len;
624
625 while (insn < end)
626 {
627 switch (*insn)
628 {
629 case DATA_PREFIX_OPCODE:
630 case ADDR_PREFIX_OPCODE:
631 case CS_PREFIX_OPCODE:
632 case DS_PREFIX_OPCODE:
633 case ES_PREFIX_OPCODE:
634 case FS_PREFIX_OPCODE:
635 case GS_PREFIX_OPCODE:
636 case SS_PREFIX_OPCODE:
637 case LOCK_PREFIX_OPCODE:
638 case REPE_PREFIX_OPCODE:
639 case REPNE_PREFIX_OPCODE:
640 ++insn;
641 continue;
642 default:
643 return insn;
644 }
645 }
646
647 return NULL;
648 }
649
650 static int
651 i386_absolute_jmp_p (const gdb_byte *insn)
652 {
653 /* jmp far (absolute address in operand). */
654 if (insn[0] == 0xea)
655 return 1;
656
657 if (insn[0] == 0xff)
658 {
659 /* jump near, absolute indirect (/4). */
660 if ((insn[1] & 0x38) == 0x20)
661 return 1;
662
663 /* jump far, absolute indirect (/5). */
664 if ((insn[1] & 0x38) == 0x28)
665 return 1;
666 }
667
668 return 0;
669 }
670
671 /* Return non-zero if INSN is a jump, zero otherwise. */
672
673 static int
674 i386_jmp_p (const gdb_byte *insn)
675 {
676 /* jump short, relative. */
677 if (insn[0] == 0xeb)
678 return 1;
679
680 /* jump near, relative. */
681 if (insn[0] == 0xe9)
682 return 1;
683
684 return i386_absolute_jmp_p (insn);
685 }
686
687 static int
688 i386_absolute_call_p (const gdb_byte *insn)
689 {
690 /* call far, absolute. */
691 if (insn[0] == 0x9a)
692 return 1;
693
694 if (insn[0] == 0xff)
695 {
696 /* Call near, absolute indirect (/2). */
697 if ((insn[1] & 0x38) == 0x10)
698 return 1;
699
700 /* Call far, absolute indirect (/3). */
701 if ((insn[1] & 0x38) == 0x18)
702 return 1;
703 }
704
705 return 0;
706 }
707
708 static int
709 i386_ret_p (const gdb_byte *insn)
710 {
711 switch (insn[0])
712 {
713 case 0xc2: /* ret near, pop N bytes. */
714 case 0xc3: /* ret near */
715 case 0xca: /* ret far, pop N bytes. */
716 case 0xcb: /* ret far */
717 case 0xcf: /* iret */
718 return 1;
719
720 default:
721 return 0;
722 }
723 }
724
725 static int
726 i386_call_p (const gdb_byte *insn)
727 {
728 if (i386_absolute_call_p (insn))
729 return 1;
730
731 /* call near, relative. */
732 if (insn[0] == 0xe8)
733 return 1;
734
735 return 0;
736 }
737
738 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
739 length in bytes. Otherwise, return zero. */
740
741 static int
742 i386_syscall_p (const gdb_byte *insn, int *lengthp)
743 {
744 /* Is it 'int $0x80'? */
745 if ((insn[0] == 0xcd && insn[1] == 0x80)
746 /* Or is it 'sysenter'? */
747 || (insn[0] == 0x0f && insn[1] == 0x34)
748 /* Or is it 'syscall'? */
749 || (insn[0] == 0x0f && insn[1] == 0x05))
750 {
751 *lengthp = 2;
752 return 1;
753 }
754
755 return 0;
756 }
757
758 /* The gdbarch insn_is_call method. */
759
760 static int
761 i386_insn_is_call (struct gdbarch *gdbarch, CORE_ADDR addr)
762 {
763 gdb_byte buf[I386_MAX_INSN_LEN], *insn;
764
765 read_code (addr, buf, I386_MAX_INSN_LEN);
766 insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN);
767
768 return i386_call_p (insn);
769 }
770
771 /* The gdbarch insn_is_ret method. */
772
773 static int
774 i386_insn_is_ret (struct gdbarch *gdbarch, CORE_ADDR addr)
775 {
776 gdb_byte buf[I386_MAX_INSN_LEN], *insn;
777
778 read_code (addr, buf, I386_MAX_INSN_LEN);
779 insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN);
780
781 return i386_ret_p (insn);
782 }
783
784 /* The gdbarch insn_is_jump method. */
785
786 static int
787 i386_insn_is_jump (struct gdbarch *gdbarch, CORE_ADDR addr)
788 {
789 gdb_byte buf[I386_MAX_INSN_LEN], *insn;
790
791 read_code (addr, buf, I386_MAX_INSN_LEN);
792 insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN);
793
794 return i386_jmp_p (insn);
795 }
796
797 /* Some kernels may run one past a syscall insn, so we have to cope. */
798
799 struct displaced_step_closure *
800 i386_displaced_step_copy_insn (struct gdbarch *gdbarch,
801 CORE_ADDR from, CORE_ADDR to,
802 struct regcache *regs)
803 {
804 size_t len = gdbarch_max_insn_length (gdbarch);
805 i386_displaced_step_closure *closure = new i386_displaced_step_closure (len);
806 gdb_byte *buf = closure->buf.data ();
807
808 read_memory (from, buf, len);
809
810 /* GDB may get control back after the insn after the syscall.
811 Presumably this is a kernel bug.
812 If this is a syscall, make sure there's a nop afterwards. */
813 {
814 int syscall_length;
815 gdb_byte *insn;
816
817 insn = i386_skip_prefixes (buf, len);
818 if (insn != NULL && i386_syscall_p (insn, &syscall_length))
819 insn[syscall_length] = NOP_OPCODE;
820 }
821
822 write_memory (to, buf, len);
823
824 if (debug_displaced)
825 {
826 fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ",
827 paddress (gdbarch, from), paddress (gdbarch, to));
828 displaced_step_dump_bytes (gdb_stdlog, buf, len);
829 }
830
831 return closure;
832 }
833
834 /* Fix up the state of registers and memory after having single-stepped
835 a displaced instruction. */
836
837 void
838 i386_displaced_step_fixup (struct gdbarch *gdbarch,
839 struct displaced_step_closure *closure_,
840 CORE_ADDR from, CORE_ADDR to,
841 struct regcache *regs)
842 {
843 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
844
845 /* The offset we applied to the instruction's address.
846 This could well be negative (when viewed as a signed 32-bit
847 value), but ULONGEST won't reflect that, so take care when
848 applying it. */
849 ULONGEST insn_offset = to - from;
850
851 i386_displaced_step_closure *closure
852 = (i386_displaced_step_closure *) closure_;
853 gdb_byte *insn = closure->buf.data ();
854 /* The start of the insn, needed in case we see some prefixes. */
855 gdb_byte *insn_start = insn;
856
857 if (debug_displaced)
858 fprintf_unfiltered (gdb_stdlog,
859 "displaced: fixup (%s, %s), "
860 "insn = 0x%02x 0x%02x ...\n",
861 paddress (gdbarch, from), paddress (gdbarch, to),
862 insn[0], insn[1]);
863
864 /* The list of issues to contend with here is taken from
865 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
866 Yay for Free Software! */
867
868 /* Relocate the %eip, if necessary. */
869
870 /* The instruction recognizers we use assume any leading prefixes
871 have been skipped. */
872 {
873 /* This is the size of the buffer in closure. */
874 size_t max_insn_len = gdbarch_max_insn_length (gdbarch);
875 gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len);
876 /* If there are too many prefixes, just ignore the insn.
877 It will fault when run. */
878 if (opcode != NULL)
879 insn = opcode;
880 }
881
882 /* Except in the case of absolute or indirect jump or call
883 instructions, or a return instruction, the new eip is relative to
884 the displaced instruction; make it relative. Well, signal
885 handler returns don't need relocation either, but we use the
886 value of %eip to recognize those; see below. */
887 if (! i386_absolute_jmp_p (insn)
888 && ! i386_absolute_call_p (insn)
889 && ! i386_ret_p (insn))
890 {
891 ULONGEST orig_eip;
892 int insn_len;
893
894 regcache_cooked_read_unsigned (regs, I386_EIP_REGNUM, &orig_eip);
895
896 /* A signal trampoline system call changes the %eip, resuming
897 execution of the main program after the signal handler has
898 returned. That makes them like 'return' instructions; we
899 shouldn't relocate %eip.
900
901 But most system calls don't, and we do need to relocate %eip.
902
903 Our heuristic for distinguishing these cases: if stepping
904 over the system call instruction left control directly after
905 the instruction, the we relocate --- control almost certainly
906 doesn't belong in the displaced copy. Otherwise, we assume
907 the instruction has put control where it belongs, and leave
908 it unrelocated. Goodness help us if there are PC-relative
909 system calls. */
910 if (i386_syscall_p (insn, &insn_len)
911 && orig_eip != to + (insn - insn_start) + insn_len
912 /* GDB can get control back after the insn after the syscall.
913 Presumably this is a kernel bug.
914 i386_displaced_step_copy_insn ensures its a nop,
915 we add one to the length for it. */
916 && orig_eip != to + (insn - insn_start) + insn_len + 1)
917 {
918 if (debug_displaced)
919 fprintf_unfiltered (gdb_stdlog,
920 "displaced: syscall changed %%eip; "
921 "not relocating\n");
922 }
923 else
924 {
925 ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL;
926
927 /* If we just stepped over a breakpoint insn, we don't backup
928 the pc on purpose; this is to match behaviour without
929 stepping. */
930
931 regcache_cooked_write_unsigned (regs, I386_EIP_REGNUM, eip);
932
933 if (debug_displaced)
934 fprintf_unfiltered (gdb_stdlog,
935 "displaced: "
936 "relocated %%eip from %s to %s\n",
937 paddress (gdbarch, orig_eip),
938 paddress (gdbarch, eip));
939 }
940 }
941
942 /* If the instruction was PUSHFL, then the TF bit will be set in the
943 pushed value, and should be cleared. We'll leave this for later,
944 since GDB already messes up the TF flag when stepping over a
945 pushfl. */
946
947 /* If the instruction was a call, the return address now atop the
948 stack is the address following the copied instruction. We need
949 to make it the address following the original instruction. */
950 if (i386_call_p (insn))
951 {
952 ULONGEST esp;
953 ULONGEST retaddr;
954 const ULONGEST retaddr_len = 4;
955
956 regcache_cooked_read_unsigned (regs, I386_ESP_REGNUM, &esp);
957 retaddr = read_memory_unsigned_integer (esp, retaddr_len, byte_order);
958 retaddr = (retaddr - insn_offset) & 0xffffffffUL;
959 write_memory_unsigned_integer (esp, retaddr_len, byte_order, retaddr);
960
961 if (debug_displaced)
962 fprintf_unfiltered (gdb_stdlog,
963 "displaced: relocated return addr at %s to %s\n",
964 paddress (gdbarch, esp),
965 paddress (gdbarch, retaddr));
966 }
967 }
968
969 static void
970 append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf)
971 {
972 target_write_memory (*to, buf, len);
973 *to += len;
974 }
975
976 static void
977 i386_relocate_instruction (struct gdbarch *gdbarch,
978 CORE_ADDR *to, CORE_ADDR oldloc)
979 {
980 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
981 gdb_byte buf[I386_MAX_INSN_LEN];
982 int offset = 0, rel32, newrel;
983 int insn_length;
984 gdb_byte *insn = buf;
985
986 read_memory (oldloc, buf, I386_MAX_INSN_LEN);
987
988 insn_length = gdb_buffered_insn_length (gdbarch, insn,
989 I386_MAX_INSN_LEN, oldloc);
990
991 /* Get past the prefixes. */
992 insn = i386_skip_prefixes (insn, I386_MAX_INSN_LEN);
993
994 /* Adjust calls with 32-bit relative addresses as push/jump, with
995 the address pushed being the location where the original call in
996 the user program would return to. */
997 if (insn[0] == 0xe8)
998 {
999 gdb_byte push_buf[16];
1000 unsigned int ret_addr;
1001
1002 /* Where "ret" in the original code will return to. */
1003 ret_addr = oldloc + insn_length;
1004 push_buf[0] = 0x68; /* pushq $... */
1005 store_unsigned_integer (&push_buf[1], 4, byte_order, ret_addr);
1006 /* Push the push. */
1007 append_insns (to, 5, push_buf);
1008
1009 /* Convert the relative call to a relative jump. */
1010 insn[0] = 0xe9;
1011
1012 /* Adjust the destination offset. */
1013 rel32 = extract_signed_integer (insn + 1, 4, byte_order);
1014 newrel = (oldloc - *to) + rel32;
1015 store_signed_integer (insn + 1, 4, byte_order, newrel);
1016
1017 if (debug_displaced)
1018 fprintf_unfiltered (gdb_stdlog,
1019 "Adjusted insn rel32=%s at %s to"
1020 " rel32=%s at %s\n",
1021 hex_string (rel32), paddress (gdbarch, oldloc),
1022 hex_string (newrel), paddress (gdbarch, *to));
1023
1024 /* Write the adjusted jump into its displaced location. */
1025 append_insns (to, 5, insn);
1026 return;
1027 }
1028
1029 /* Adjust jumps with 32-bit relative addresses. Calls are already
1030 handled above. */
1031 if (insn[0] == 0xe9)
1032 offset = 1;
1033 /* Adjust conditional jumps. */
1034 else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80)
1035 offset = 2;
1036
1037 if (offset)
1038 {
1039 rel32 = extract_signed_integer (insn + offset, 4, byte_order);
1040 newrel = (oldloc - *to) + rel32;
1041 store_signed_integer (insn + offset, 4, byte_order, newrel);
1042 if (debug_displaced)
1043 fprintf_unfiltered (gdb_stdlog,
1044 "Adjusted insn rel32=%s at %s to"
1045 " rel32=%s at %s\n",
1046 hex_string (rel32), paddress (gdbarch, oldloc),
1047 hex_string (newrel), paddress (gdbarch, *to));
1048 }
1049
1050 /* Write the adjusted instructions into their displaced
1051 location. */
1052 append_insns (to, insn_length, buf);
1053 }
1054
1055
1056 #ifdef I386_REGNO_TO_SYMMETRY
1057 #error "The Sequent Symmetry is no longer supported."
1058 #endif
1059
1060 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
1061 and %esp "belong" to the calling function. Therefore these
1062 registers should be saved if they're going to be modified. */
1063
1064 /* The maximum number of saved registers. This should include all
1065 registers mentioned above, and %eip. */
1066 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
1067
1068 struct i386_frame_cache
1069 {
1070 /* Base address. */
1071 CORE_ADDR base;
1072 int base_p;
1073 LONGEST sp_offset;
1074 CORE_ADDR pc;
1075
1076 /* Saved registers. */
1077 CORE_ADDR saved_regs[I386_NUM_SAVED_REGS];
1078 CORE_ADDR saved_sp;
1079 int saved_sp_reg;
1080 int pc_in_eax;
1081
1082 /* Stack space reserved for local variables. */
1083 long locals;
1084 };
1085
1086 /* Allocate and initialize a frame cache. */
1087
1088 static struct i386_frame_cache *
1089 i386_alloc_frame_cache (void)
1090 {
1091 struct i386_frame_cache *cache;
1092 int i;
1093
1094 cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache);
1095
1096 /* Base address. */
1097 cache->base_p = 0;
1098 cache->base = 0;
1099 cache->sp_offset = -4;
1100 cache->pc = 0;
1101
1102 /* Saved registers. We initialize these to -1 since zero is a valid
1103 offset (that's where %ebp is supposed to be stored). */
1104 for (i = 0; i < I386_NUM_SAVED_REGS; i++)
1105 cache->saved_regs[i] = -1;
1106 cache->saved_sp = 0;
1107 cache->saved_sp_reg = -1;
1108 cache->pc_in_eax = 0;
1109
1110 /* Frameless until proven otherwise. */
1111 cache->locals = -1;
1112
1113 return cache;
1114 }
1115
1116 /* If the instruction at PC is a jump, return the address of its
1117 target. Otherwise, return PC. */
1118
1119 static CORE_ADDR
1120 i386_follow_jump (struct gdbarch *gdbarch, CORE_ADDR pc)
1121 {
1122 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1123 gdb_byte op;
1124 long delta = 0;
1125 int data16 = 0;
1126
1127 if (target_read_code (pc, &op, 1))
1128 return pc;
1129
1130 if (op == 0x66)
1131 {
1132 data16 = 1;
1133
1134 op = read_code_unsigned_integer (pc + 1, 1, byte_order);
1135 }
1136
1137 switch (op)
1138 {
1139 case 0xe9:
1140 /* Relative jump: if data16 == 0, disp32, else disp16. */
1141 if (data16)
1142 {
1143 delta = read_memory_integer (pc + 2, 2, byte_order);
1144
1145 /* Include the size of the jmp instruction (including the
1146 0x66 prefix). */
1147 delta += 4;
1148 }
1149 else
1150 {
1151 delta = read_memory_integer (pc + 1, 4, byte_order);
1152
1153 /* Include the size of the jmp instruction. */
1154 delta += 5;
1155 }
1156 break;
1157 case 0xeb:
1158 /* Relative jump, disp8 (ignore data16). */
1159 delta = read_memory_integer (pc + data16 + 1, 1, byte_order);
1160
1161 delta += data16 + 2;
1162 break;
1163 }
1164
1165 return pc + delta;
1166 }
1167
1168 /* Check whether PC points at a prologue for a function returning a
1169 structure or union. If so, it updates CACHE and returns the
1170 address of the first instruction after the code sequence that
1171 removes the "hidden" argument from the stack or CURRENT_PC,
1172 whichever is smaller. Otherwise, return PC. */
1173
1174 static CORE_ADDR
1175 i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc,
1176 struct i386_frame_cache *cache)
1177 {
1178 /* Functions that return a structure or union start with:
1179
1180 popl %eax 0x58
1181 xchgl %eax, (%esp) 0x87 0x04 0x24
1182 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
1183
1184 (the System V compiler puts out the second `xchg' instruction,
1185 and the assembler doesn't try to optimize it, so the 'sib' form
1186 gets generated). This sequence is used to get the address of the
1187 return buffer for a function that returns a structure. */
1188 static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 };
1189 static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 };
1190 gdb_byte buf[4];
1191 gdb_byte op;
1192
1193 if (current_pc <= pc)
1194 return pc;
1195
1196 if (target_read_code (pc, &op, 1))
1197 return pc;
1198
1199 if (op != 0x58) /* popl %eax */
1200 return pc;
1201
1202 if (target_read_code (pc + 1, buf, 4))
1203 return pc;
1204
1205 if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0)
1206 return pc;
1207
1208 if (current_pc == pc)
1209 {
1210 cache->sp_offset += 4;
1211 return current_pc;
1212 }
1213
1214 if (current_pc == pc + 1)
1215 {
1216 cache->pc_in_eax = 1;
1217 return current_pc;
1218 }
1219
1220 if (buf[1] == proto1[1])
1221 return pc + 4;
1222 else
1223 return pc + 5;
1224 }
1225
1226 static CORE_ADDR
1227 i386_skip_probe (CORE_ADDR pc)
1228 {
1229 /* A function may start with
1230
1231 pushl constant
1232 call _probe
1233 addl $4, %esp
1234
1235 followed by
1236
1237 pushl %ebp
1238
1239 etc. */
1240 gdb_byte buf[8];
1241 gdb_byte op;
1242
1243 if (target_read_code (pc, &op, 1))
1244 return pc;
1245
1246 if (op == 0x68 || op == 0x6a)
1247 {
1248 int delta;
1249
1250 /* Skip past the `pushl' instruction; it has either a one-byte or a
1251 four-byte operand, depending on the opcode. */
1252 if (op == 0x68)
1253 delta = 5;
1254 else
1255 delta = 2;
1256
1257 /* Read the following 8 bytes, which should be `call _probe' (6
1258 bytes) followed by `addl $4,%esp' (2 bytes). */
1259 read_memory (pc + delta, buf, sizeof (buf));
1260 if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4)
1261 pc += delta + sizeof (buf);
1262 }
1263
1264 return pc;
1265 }
1266
1267 /* GCC 4.1 and later, can put code in the prologue to realign the
1268 stack pointer. Check whether PC points to such code, and update
1269 CACHE accordingly. Return the first instruction after the code
1270 sequence or CURRENT_PC, whichever is smaller. If we don't
1271 recognize the code, return PC. */
1272
1273 static CORE_ADDR
1274 i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc,
1275 struct i386_frame_cache *cache)
1276 {
1277 /* There are 2 code sequences to re-align stack before the frame
1278 gets set up:
1279
1280 1. Use a caller-saved saved register:
1281
1282 leal 4(%esp), %reg
1283 andl $-XXX, %esp
1284 pushl -4(%reg)
1285
1286 2. Use a callee-saved saved register:
1287
1288 pushl %reg
1289 leal 8(%esp), %reg
1290 andl $-XXX, %esp
1291 pushl -4(%reg)
1292
1293 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
1294
1295 0x83 0xe4 0xf0 andl $-16, %esp
1296 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
1297 */
1298
1299 gdb_byte buf[14];
1300 int reg;
1301 int offset, offset_and;
1302 static int regnums[8] = {
1303 I386_EAX_REGNUM, /* %eax */
1304 I386_ECX_REGNUM, /* %ecx */
1305 I386_EDX_REGNUM, /* %edx */
1306 I386_EBX_REGNUM, /* %ebx */
1307 I386_ESP_REGNUM, /* %esp */
1308 I386_EBP_REGNUM, /* %ebp */
1309 I386_ESI_REGNUM, /* %esi */
1310 I386_EDI_REGNUM /* %edi */
1311 };
1312
1313 if (target_read_code (pc, buf, sizeof buf))
1314 return pc;
1315
1316 /* Check caller-saved saved register. The first instruction has
1317 to be "leal 4(%esp), %reg". */
1318 if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4)
1319 {
1320 /* MOD must be binary 10 and R/M must be binary 100. */
1321 if ((buf[1] & 0xc7) != 0x44)
1322 return pc;
1323
1324 /* REG has register number. */
1325 reg = (buf[1] >> 3) & 7;
1326 offset = 4;
1327 }
1328 else
1329 {
1330 /* Check callee-saved saved register. The first instruction
1331 has to be "pushl %reg". */
1332 if ((buf[0] & 0xf8) != 0x50)
1333 return pc;
1334
1335 /* Get register. */
1336 reg = buf[0] & 0x7;
1337
1338 /* The next instruction has to be "leal 8(%esp), %reg". */
1339 if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8)
1340 return pc;
1341
1342 /* MOD must be binary 10 and R/M must be binary 100. */
1343 if ((buf[2] & 0xc7) != 0x44)
1344 return pc;
1345
1346 /* REG has register number. Registers in pushl and leal have to
1347 be the same. */
1348 if (reg != ((buf[2] >> 3) & 7))
1349 return pc;
1350
1351 offset = 5;
1352 }
1353
1354 /* Rigister can't be %esp nor %ebp. */
1355 if (reg == 4 || reg == 5)
1356 return pc;
1357
1358 /* The next instruction has to be "andl $-XXX, %esp". */
1359 if (buf[offset + 1] != 0xe4
1360 || (buf[offset] != 0x81 && buf[offset] != 0x83))
1361 return pc;
1362
1363 offset_and = offset;
1364 offset += buf[offset] == 0x81 ? 6 : 3;
1365
1366 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
1367 0xfc. REG must be binary 110 and MOD must be binary 01. */
1368 if (buf[offset] != 0xff
1369 || buf[offset + 2] != 0xfc
1370 || (buf[offset + 1] & 0xf8) != 0x70)
1371 return pc;
1372
1373 /* R/M has register. Registers in leal and pushl have to be the
1374 same. */
1375 if (reg != (buf[offset + 1] & 7))
1376 return pc;
1377
1378 if (current_pc > pc + offset_and)
1379 cache->saved_sp_reg = regnums[reg];
1380
1381 return std::min (pc + offset + 3, current_pc);
1382 }
1383
1384 /* Maximum instruction length we need to handle. */
1385 #define I386_MAX_MATCHED_INSN_LEN 6
1386
1387 /* Instruction description. */
1388 struct i386_insn
1389 {
1390 size_t len;
1391 gdb_byte insn[I386_MAX_MATCHED_INSN_LEN];
1392 gdb_byte mask[I386_MAX_MATCHED_INSN_LEN];
1393 };
1394
1395 /* Return whether instruction at PC matches PATTERN. */
1396
1397 static int
1398 i386_match_pattern (CORE_ADDR pc, struct i386_insn pattern)
1399 {
1400 gdb_byte op;
1401
1402 if (target_read_code (pc, &op, 1))
1403 return 0;
1404
1405 if ((op & pattern.mask[0]) == pattern.insn[0])
1406 {
1407 gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1];
1408 int insn_matched = 1;
1409 size_t i;
1410
1411 gdb_assert (pattern.len > 1);
1412 gdb_assert (pattern.len <= I386_MAX_MATCHED_INSN_LEN);
1413
1414 if (target_read_code (pc + 1, buf, pattern.len - 1))
1415 return 0;
1416
1417 for (i = 1; i < pattern.len; i++)
1418 {
1419 if ((buf[i - 1] & pattern.mask[i]) != pattern.insn[i])
1420 insn_matched = 0;
1421 }
1422 return insn_matched;
1423 }
1424 return 0;
1425 }
1426
1427 /* Search for the instruction at PC in the list INSN_PATTERNS. Return
1428 the first instruction description that matches. Otherwise, return
1429 NULL. */
1430
1431 static struct i386_insn *
1432 i386_match_insn (CORE_ADDR pc, struct i386_insn *insn_patterns)
1433 {
1434 struct i386_insn *pattern;
1435
1436 for (pattern = insn_patterns; pattern->len > 0; pattern++)
1437 {
1438 if (i386_match_pattern (pc, *pattern))
1439 return pattern;
1440 }
1441
1442 return NULL;
1443 }
1444
1445 /* Return whether PC points inside a sequence of instructions that
1446 matches INSN_PATTERNS. */
1447
1448 static int
1449 i386_match_insn_block (CORE_ADDR pc, struct i386_insn *insn_patterns)
1450 {
1451 CORE_ADDR current_pc;
1452 int ix, i;
1453 struct i386_insn *insn;
1454
1455 insn = i386_match_insn (pc, insn_patterns);
1456 if (insn == NULL)
1457 return 0;
1458
1459 current_pc = pc;
1460 ix = insn - insn_patterns;
1461 for (i = ix - 1; i >= 0; i--)
1462 {
1463 current_pc -= insn_patterns[i].len;
1464
1465 if (!i386_match_pattern (current_pc, insn_patterns[i]))
1466 return 0;
1467 }
1468
1469 current_pc = pc + insn->len;
1470 for (insn = insn_patterns + ix + 1; insn->len > 0; insn++)
1471 {
1472 if (!i386_match_pattern (current_pc, *insn))
1473 return 0;
1474
1475 current_pc += insn->len;
1476 }
1477
1478 return 1;
1479 }
1480
1481 /* Some special instructions that might be migrated by GCC into the
1482 part of the prologue that sets up the new stack frame. Because the
1483 stack frame hasn't been setup yet, no registers have been saved
1484 yet, and only the scratch registers %eax, %ecx and %edx can be
1485 touched. */
1486
1487 struct i386_insn i386_frame_setup_skip_insns[] =
1488 {
1489 /* Check for `movb imm8, r' and `movl imm32, r'.
1490
1491 ??? Should we handle 16-bit operand-sizes here? */
1492
1493 /* `movb imm8, %al' and `movb imm8, %ah' */
1494 /* `movb imm8, %cl' and `movb imm8, %ch' */
1495 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
1496 /* `movb imm8, %dl' and `movb imm8, %dh' */
1497 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
1498 /* `movl imm32, %eax' and `movl imm32, %ecx' */
1499 { 5, { 0xb8 }, { 0xfe } },
1500 /* `movl imm32, %edx' */
1501 { 5, { 0xba }, { 0xff } },
1502
1503 /* Check for `mov imm32, r32'. Note that there is an alternative
1504 encoding for `mov m32, %eax'.
1505
1506 ??? Should we handle SIB adressing here?
1507 ??? Should we handle 16-bit operand-sizes here? */
1508
1509 /* `movl m32, %eax' */
1510 { 5, { 0xa1 }, { 0xff } },
1511 /* `movl m32, %eax' and `mov; m32, %ecx' */
1512 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
1513 /* `movl m32, %edx' */
1514 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
1515
1516 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
1517 Because of the symmetry, there are actually two ways to encode
1518 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
1519 opcode bytes 0x31 and 0x33 for `xorl'. */
1520
1521 /* `subl %eax, %eax' */
1522 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
1523 /* `subl %ecx, %ecx' */
1524 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
1525 /* `subl %edx, %edx' */
1526 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
1527 /* `xorl %eax, %eax' */
1528 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
1529 /* `xorl %ecx, %ecx' */
1530 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
1531 /* `xorl %edx, %edx' */
1532 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
1533 { 0 }
1534 };
1535
1536
1537 /* Check whether PC points to a no-op instruction. */
1538 static CORE_ADDR
1539 i386_skip_noop (CORE_ADDR pc)
1540 {
1541 gdb_byte op;
1542 int check = 1;
1543
1544 if (target_read_code (pc, &op, 1))
1545 return pc;
1546
1547 while (check)
1548 {
1549 check = 0;
1550 /* Ignore `nop' instruction. */
1551 if (op == 0x90)
1552 {
1553 pc += 1;
1554 if (target_read_code (pc, &op, 1))
1555 return pc;
1556 check = 1;
1557 }
1558 /* Ignore no-op instruction `mov %edi, %edi'.
1559 Microsoft system dlls often start with
1560 a `mov %edi,%edi' instruction.
1561 The 5 bytes before the function start are
1562 filled with `nop' instructions.
1563 This pattern can be used for hot-patching:
1564 The `mov %edi, %edi' instruction can be replaced by a
1565 near jump to the location of the 5 `nop' instructions
1566 which can be replaced by a 32-bit jump to anywhere
1567 in the 32-bit address space. */
1568
1569 else if (op == 0x8b)
1570 {
1571 if (target_read_code (pc + 1, &op, 1))
1572 return pc;
1573
1574 if (op == 0xff)
1575 {
1576 pc += 2;
1577 if (target_read_code (pc, &op, 1))
1578 return pc;
1579
1580 check = 1;
1581 }
1582 }
1583 }
1584 return pc;
1585 }
1586
1587 /* Check whether PC points at a code that sets up a new stack frame.
1588 If so, it updates CACHE and returns the address of the first
1589 instruction after the sequence that sets up the frame or LIMIT,
1590 whichever is smaller. If we don't recognize the code, return PC. */
1591
1592 static CORE_ADDR
1593 i386_analyze_frame_setup (struct gdbarch *gdbarch,
1594 CORE_ADDR pc, CORE_ADDR limit,
1595 struct i386_frame_cache *cache)
1596 {
1597 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1598 struct i386_insn *insn;
1599 gdb_byte op;
1600 int skip = 0;
1601
1602 if (limit <= pc)
1603 return limit;
1604
1605 if (target_read_code (pc, &op, 1))
1606 return pc;
1607
1608 if (op == 0x55) /* pushl %ebp */
1609 {
1610 /* Take into account that we've executed the `pushl %ebp' that
1611 starts this instruction sequence. */
1612 cache->saved_regs[I386_EBP_REGNUM] = 0;
1613 cache->sp_offset += 4;
1614 pc++;
1615
1616 /* If that's all, return now. */
1617 if (limit <= pc)
1618 return limit;
1619
1620 /* Check for some special instructions that might be migrated by
1621 GCC into the prologue and skip them. At this point in the
1622 prologue, code should only touch the scratch registers %eax,
1623 %ecx and %edx, so while the number of posibilities is sheer,
1624 it is limited.
1625
1626 Make sure we only skip these instructions if we later see the
1627 `movl %esp, %ebp' that actually sets up the frame. */
1628 while (pc + skip < limit)
1629 {
1630 insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns);
1631 if (insn == NULL)
1632 break;
1633
1634 skip += insn->len;
1635 }
1636
1637 /* If that's all, return now. */
1638 if (limit <= pc + skip)
1639 return limit;
1640
1641 if (target_read_code (pc + skip, &op, 1))
1642 return pc + skip;
1643
1644 /* The i386 prologue looks like
1645
1646 push %ebp
1647 mov %esp,%ebp
1648 sub $0x10,%esp
1649
1650 and a different prologue can be generated for atom.
1651
1652 push %ebp
1653 lea (%esp),%ebp
1654 lea -0x10(%esp),%esp
1655
1656 We handle both of them here. */
1657
1658 switch (op)
1659 {
1660 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1661 case 0x8b:
1662 if (read_code_unsigned_integer (pc + skip + 1, 1, byte_order)
1663 != 0xec)
1664 return pc;
1665 pc += (skip + 2);
1666 break;
1667 case 0x89:
1668 if (read_code_unsigned_integer (pc + skip + 1, 1, byte_order)
1669 != 0xe5)
1670 return pc;
1671 pc += (skip + 2);
1672 break;
1673 case 0x8d: /* Check for 'lea (%ebp), %ebp'. */
1674 if (read_code_unsigned_integer (pc + skip + 1, 2, byte_order)
1675 != 0x242c)
1676 return pc;
1677 pc += (skip + 3);
1678 break;
1679 default:
1680 return pc;
1681 }
1682
1683 /* OK, we actually have a frame. We just don't know how large
1684 it is yet. Set its size to zero. We'll adjust it if
1685 necessary. We also now commit to skipping the special
1686 instructions mentioned before. */
1687 cache->locals = 0;
1688
1689 /* If that's all, return now. */
1690 if (limit <= pc)
1691 return limit;
1692
1693 /* Check for stack adjustment
1694
1695 subl $XXX, %esp
1696 or
1697 lea -XXX(%esp),%esp
1698
1699 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1700 reg, so we don't have to worry about a data16 prefix. */
1701 if (target_read_code (pc, &op, 1))
1702 return pc;
1703 if (op == 0x83)
1704 {
1705 /* `subl' with 8-bit immediate. */
1706 if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0xec)
1707 /* Some instruction starting with 0x83 other than `subl'. */
1708 return pc;
1709
1710 /* `subl' with signed 8-bit immediate (though it wouldn't
1711 make sense to be negative). */
1712 cache->locals = read_code_integer (pc + 2, 1, byte_order);
1713 return pc + 3;
1714 }
1715 else if (op == 0x81)
1716 {
1717 /* Maybe it is `subl' with a 32-bit immediate. */
1718 if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0xec)
1719 /* Some instruction starting with 0x81 other than `subl'. */
1720 return pc;
1721
1722 /* It is `subl' with a 32-bit immediate. */
1723 cache->locals = read_code_integer (pc + 2, 4, byte_order);
1724 return pc + 6;
1725 }
1726 else if (op == 0x8d)
1727 {
1728 /* The ModR/M byte is 0x64. */
1729 if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0x64)
1730 return pc;
1731 /* 'lea' with 8-bit displacement. */
1732 cache->locals = -1 * read_code_integer (pc + 3, 1, byte_order);
1733 return pc + 4;
1734 }
1735 else
1736 {
1737 /* Some instruction other than `subl' nor 'lea'. */
1738 return pc;
1739 }
1740 }
1741 else if (op == 0xc8) /* enter */
1742 {
1743 cache->locals = read_code_unsigned_integer (pc + 1, 2, byte_order);
1744 return pc + 4;
1745 }
1746
1747 return pc;
1748 }
1749
1750 /* Check whether PC points at code that saves registers on the stack.
1751 If so, it updates CACHE and returns the address of the first
1752 instruction after the register saves or CURRENT_PC, whichever is
1753 smaller. Otherwise, return PC. */
1754
1755 static CORE_ADDR
1756 i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc,
1757 struct i386_frame_cache *cache)
1758 {
1759 CORE_ADDR offset = 0;
1760 gdb_byte op;
1761 int i;
1762
1763 if (cache->locals > 0)
1764 offset -= cache->locals;
1765 for (i = 0; i < 8 && pc < current_pc; i++)
1766 {
1767 if (target_read_code (pc, &op, 1))
1768 return pc;
1769 if (op < 0x50 || op > 0x57)
1770 break;
1771
1772 offset -= 4;
1773 cache->saved_regs[op - 0x50] = offset;
1774 cache->sp_offset += 4;
1775 pc++;
1776 }
1777
1778 return pc;
1779 }
1780
1781 /* Do a full analysis of the prologue at PC and update CACHE
1782 accordingly. Bail out early if CURRENT_PC is reached. Return the
1783 address where the analysis stopped.
1784
1785 We handle these cases:
1786
1787 The startup sequence can be at the start of the function, or the
1788 function can start with a branch to startup code at the end.
1789
1790 %ebp can be set up with either the 'enter' instruction, or "pushl
1791 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1792 once used in the System V compiler).
1793
1794 Local space is allocated just below the saved %ebp by either the
1795 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1796 16-bit unsigned argument for space to allocate, and the 'addl'
1797 instruction could have either a signed byte, or 32-bit immediate.
1798
1799 Next, the registers used by this function are pushed. With the
1800 System V compiler they will always be in the order: %edi, %esi,
1801 %ebx (and sometimes a harmless bug causes it to also save but not
1802 restore %eax); however, the code below is willing to see the pushes
1803 in any order, and will handle up to 8 of them.
1804
1805 If the setup sequence is at the end of the function, then the next
1806 instruction will be a branch back to the start. */
1807
1808 static CORE_ADDR
1809 i386_analyze_prologue (struct gdbarch *gdbarch,
1810 CORE_ADDR pc, CORE_ADDR current_pc,
1811 struct i386_frame_cache *cache)
1812 {
1813 pc = i386_skip_noop (pc);
1814 pc = i386_follow_jump (gdbarch, pc);
1815 pc = i386_analyze_struct_return (pc, current_pc, cache);
1816 pc = i386_skip_probe (pc);
1817 pc = i386_analyze_stack_align (pc, current_pc, cache);
1818 pc = i386_analyze_frame_setup (gdbarch, pc, current_pc, cache);
1819 return i386_analyze_register_saves (pc, current_pc, cache);
1820 }
1821
1822 /* Return PC of first real instruction. */
1823
1824 static CORE_ADDR
1825 i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
1826 {
1827 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1828
1829 static gdb_byte pic_pat[6] =
1830 {
1831 0xe8, 0, 0, 0, 0, /* call 0x0 */
1832 0x5b, /* popl %ebx */
1833 };
1834 struct i386_frame_cache cache;
1835 CORE_ADDR pc;
1836 gdb_byte op;
1837 int i;
1838 CORE_ADDR func_addr;
1839
1840 if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL))
1841 {
1842 CORE_ADDR post_prologue_pc
1843 = skip_prologue_using_sal (gdbarch, func_addr);
1844 struct compunit_symtab *cust = find_pc_compunit_symtab (func_addr);
1845
1846 /* Clang always emits a line note before the prologue and another
1847 one after. We trust clang to emit usable line notes. */
1848 if (post_prologue_pc
1849 && (cust != NULL
1850 && COMPUNIT_PRODUCER (cust) != NULL
1851 && startswith (COMPUNIT_PRODUCER (cust), "clang ")))
1852 return std::max (start_pc, post_prologue_pc);
1853 }
1854
1855 cache.locals = -1;
1856 pc = i386_analyze_prologue (gdbarch, start_pc, 0xffffffff, &cache);
1857 if (cache.locals < 0)
1858 return start_pc;
1859
1860 /* Found valid frame setup. */
1861
1862 /* The native cc on SVR4 in -K PIC mode inserts the following code
1863 to get the address of the global offset table (GOT) into register
1864 %ebx:
1865
1866 call 0x0
1867 popl %ebx
1868 movl %ebx,x(%ebp) (optional)
1869 addl y,%ebx
1870
1871 This code is with the rest of the prologue (at the end of the
1872 function), so we have to skip it to get to the first real
1873 instruction at the start of the function. */
1874
1875 for (i = 0; i < 6; i++)
1876 {
1877 if (target_read_code (pc + i, &op, 1))
1878 return pc;
1879
1880 if (pic_pat[i] != op)
1881 break;
1882 }
1883 if (i == 6)
1884 {
1885 int delta = 6;
1886
1887 if (target_read_code (pc + delta, &op, 1))
1888 return pc;
1889
1890 if (op == 0x89) /* movl %ebx, x(%ebp) */
1891 {
1892 op = read_code_unsigned_integer (pc + delta + 1, 1, byte_order);
1893
1894 if (op == 0x5d) /* One byte offset from %ebp. */
1895 delta += 3;
1896 else if (op == 0x9d) /* Four byte offset from %ebp. */
1897 delta += 6;
1898 else /* Unexpected instruction. */
1899 delta = 0;
1900
1901 if (target_read_code (pc + delta, &op, 1))
1902 return pc;
1903 }
1904
1905 /* addl y,%ebx */
1906 if (delta > 0 && op == 0x81
1907 && read_code_unsigned_integer (pc + delta + 1, 1, byte_order)
1908 == 0xc3)
1909 {
1910 pc += delta + 6;
1911 }
1912 }
1913
1914 /* If the function starts with a branch (to startup code at the end)
1915 the last instruction should bring us back to the first
1916 instruction of the real code. */
1917 if (i386_follow_jump (gdbarch, start_pc) != start_pc)
1918 pc = i386_follow_jump (gdbarch, pc);
1919
1920 return pc;
1921 }
1922
1923 /* Check that the code pointed to by PC corresponds to a call to
1924 __main, skip it if so. Return PC otherwise. */
1925
1926 CORE_ADDR
1927 i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1928 {
1929 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1930 gdb_byte op;
1931
1932 if (target_read_code (pc, &op, 1))
1933 return pc;
1934 if (op == 0xe8)
1935 {
1936 gdb_byte buf[4];
1937
1938 if (target_read_code (pc + 1, buf, sizeof buf) == 0)
1939 {
1940 /* Make sure address is computed correctly as a 32bit
1941 integer even if CORE_ADDR is 64 bit wide. */
1942 struct bound_minimal_symbol s;
1943 CORE_ADDR call_dest;
1944
1945 call_dest = pc + 5 + extract_signed_integer (buf, 4, byte_order);
1946 call_dest = call_dest & 0xffffffffU;
1947 s = lookup_minimal_symbol_by_pc (call_dest);
1948 if (s.minsym != NULL
1949 && MSYMBOL_LINKAGE_NAME (s.minsym) != NULL
1950 && strcmp (MSYMBOL_LINKAGE_NAME (s.minsym), "__main") == 0)
1951 pc += 5;
1952 }
1953 }
1954
1955 return pc;
1956 }
1957
1958 /* This function is 64-bit safe. */
1959
1960 static CORE_ADDR
1961 i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1962 {
1963 gdb_byte buf[8];
1964
1965 frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf);
1966 return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
1967 }
1968
1969
1970 /* Normal frames. */
1971
1972 static void
1973 i386_frame_cache_1 (struct frame_info *this_frame,
1974 struct i386_frame_cache *cache)
1975 {
1976 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1977 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1978 gdb_byte buf[4];
1979 int i;
1980
1981 cache->pc = get_frame_func (this_frame);
1982
1983 /* In principle, for normal frames, %ebp holds the frame pointer,
1984 which holds the base address for the current stack frame.
1985 However, for functions that don't need it, the frame pointer is
1986 optional. For these "frameless" functions the frame pointer is
1987 actually the frame pointer of the calling frame. Signal
1988 trampolines are just a special case of a "frameless" function.
1989 They (usually) share their frame pointer with the frame that was
1990 in progress when the signal occurred. */
1991
1992 get_frame_register (this_frame, I386_EBP_REGNUM, buf);
1993 cache->base = extract_unsigned_integer (buf, 4, byte_order);
1994 if (cache->base == 0)
1995 {
1996 cache->base_p = 1;
1997 return;
1998 }
1999
2000 /* For normal frames, %eip is stored at 4(%ebp). */
2001 cache->saved_regs[I386_EIP_REGNUM] = 4;
2002
2003 if (cache->pc != 0)
2004 i386_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame),
2005 cache);
2006
2007 if (cache->locals < 0)
2008 {
2009 /* We didn't find a valid frame, which means that CACHE->base
2010 currently holds the frame pointer for our calling frame. If
2011 we're at the start of a function, or somewhere half-way its
2012 prologue, the function's frame probably hasn't been fully
2013 setup yet. Try to reconstruct the base address for the stack
2014 frame by looking at the stack pointer. For truly "frameless"
2015 functions this might work too. */
2016
2017 if (cache->saved_sp_reg != -1)
2018 {
2019 /* Saved stack pointer has been saved. */
2020 get_frame_register (this_frame, cache->saved_sp_reg, buf);
2021 cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order);
2022
2023 /* We're halfway aligning the stack. */
2024 cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4;
2025 cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4;
2026
2027 /* This will be added back below. */
2028 cache->saved_regs[I386_EIP_REGNUM] -= cache->base;
2029 }
2030 else if (cache->pc != 0
2031 || target_read_code (get_frame_pc (this_frame), buf, 1))
2032 {
2033 /* We're in a known function, but did not find a frame
2034 setup. Assume that the function does not use %ebp.
2035 Alternatively, we may have jumped to an invalid
2036 address; in that case there is definitely no new
2037 frame in %ebp. */
2038 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
2039 cache->base = extract_unsigned_integer (buf, 4, byte_order)
2040 + cache->sp_offset;
2041 }
2042 else
2043 /* We're in an unknown function. We could not find the start
2044 of the function to analyze the prologue; our best option is
2045 to assume a typical frame layout with the caller's %ebp
2046 saved. */
2047 cache->saved_regs[I386_EBP_REGNUM] = 0;
2048 }
2049
2050 if (cache->saved_sp_reg != -1)
2051 {
2052 /* Saved stack pointer has been saved (but the SAVED_SP_REG
2053 register may be unavailable). */
2054 if (cache->saved_sp == 0
2055 && deprecated_frame_register_read (this_frame,
2056 cache->saved_sp_reg, buf))
2057 cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order);
2058 }
2059 /* Now that we have the base address for the stack frame we can
2060 calculate the value of %esp in the calling frame. */
2061 else if (cache->saved_sp == 0)
2062 cache->saved_sp = cache->base + 8;
2063
2064 /* Adjust all the saved registers such that they contain addresses
2065 instead of offsets. */
2066 for (i = 0; i < I386_NUM_SAVED_REGS; i++)
2067 if (cache->saved_regs[i] != -1)
2068 cache->saved_regs[i] += cache->base;
2069
2070 cache->base_p = 1;
2071 }
2072
2073 static struct i386_frame_cache *
2074 i386_frame_cache (struct frame_info *this_frame, void **this_cache)
2075 {
2076 struct i386_frame_cache *cache;
2077
2078 if (*this_cache)
2079 return (struct i386_frame_cache *) *this_cache;
2080
2081 cache = i386_alloc_frame_cache ();
2082 *this_cache = cache;
2083
2084 TRY
2085 {
2086 i386_frame_cache_1 (this_frame, cache);
2087 }
2088 CATCH (ex, RETURN_MASK_ERROR)
2089 {
2090 if (ex.error != NOT_AVAILABLE_ERROR)
2091 throw_exception (ex);
2092 }
2093 END_CATCH
2094
2095 return cache;
2096 }
2097
2098 static void
2099 i386_frame_this_id (struct frame_info *this_frame, void **this_cache,
2100 struct frame_id *this_id)
2101 {
2102 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2103
2104 if (!cache->base_p)
2105 (*this_id) = frame_id_build_unavailable_stack (cache->pc);
2106 else if (cache->base == 0)
2107 {
2108 /* This marks the outermost frame. */
2109 }
2110 else
2111 {
2112 /* See the end of i386_push_dummy_call. */
2113 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
2114 }
2115 }
2116
2117 static enum unwind_stop_reason
2118 i386_frame_unwind_stop_reason (struct frame_info *this_frame,
2119 void **this_cache)
2120 {
2121 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2122
2123 if (!cache->base_p)
2124 return UNWIND_UNAVAILABLE;
2125
2126 /* This marks the outermost frame. */
2127 if (cache->base == 0)
2128 return UNWIND_OUTERMOST;
2129
2130 return UNWIND_NO_REASON;
2131 }
2132
2133 static struct value *
2134 i386_frame_prev_register (struct frame_info *this_frame, void **this_cache,
2135 int regnum)
2136 {
2137 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2138
2139 gdb_assert (regnum >= 0);
2140
2141 /* The System V ABI says that:
2142
2143 "The flags register contains the system flags, such as the
2144 direction flag and the carry flag. The direction flag must be
2145 set to the forward (that is, zero) direction before entry and
2146 upon exit from a function. Other user flags have no specified
2147 role in the standard calling sequence and are not preserved."
2148
2149 To guarantee the "upon exit" part of that statement we fake a
2150 saved flags register that has its direction flag cleared.
2151
2152 Note that GCC doesn't seem to rely on the fact that the direction
2153 flag is cleared after a function return; it always explicitly
2154 clears the flag before operations where it matters.
2155
2156 FIXME: kettenis/20030316: I'm not quite sure whether this is the
2157 right thing to do. The way we fake the flags register here makes
2158 it impossible to change it. */
2159
2160 if (regnum == I386_EFLAGS_REGNUM)
2161 {
2162 ULONGEST val;
2163
2164 val = get_frame_register_unsigned (this_frame, regnum);
2165 val &= ~(1 << 10);
2166 return frame_unwind_got_constant (this_frame, regnum, val);
2167 }
2168
2169 if (regnum == I386_EIP_REGNUM && cache->pc_in_eax)
2170 return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM);
2171
2172 if (regnum == I386_ESP_REGNUM
2173 && (cache->saved_sp != 0 || cache->saved_sp_reg != -1))
2174 {
2175 /* If the SP has been saved, but we don't know where, then this
2176 means that SAVED_SP_REG register was found unavailable back
2177 when we built the cache. */
2178 if (cache->saved_sp == 0)
2179 return frame_unwind_got_register (this_frame, regnum,
2180 cache->saved_sp_reg);
2181 else
2182 return frame_unwind_got_constant (this_frame, regnum,
2183 cache->saved_sp);
2184 }
2185
2186 if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
2187 return frame_unwind_got_memory (this_frame, regnum,
2188 cache->saved_regs[regnum]);
2189
2190 return frame_unwind_got_register (this_frame, regnum, regnum);
2191 }
2192
2193 static const struct frame_unwind i386_frame_unwind =
2194 {
2195 NORMAL_FRAME,
2196 i386_frame_unwind_stop_reason,
2197 i386_frame_this_id,
2198 i386_frame_prev_register,
2199 NULL,
2200 default_frame_sniffer
2201 };
2202
2203 /* Normal frames, but in a function epilogue. */
2204
2205 /* Implement the stack_frame_destroyed_p gdbarch method.
2206
2207 The epilogue is defined here as the 'ret' instruction, which will
2208 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2209 the function's stack frame. */
2210
2211 static int
2212 i386_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
2213 {
2214 gdb_byte insn;
2215 struct compunit_symtab *cust;
2216
2217 cust = find_pc_compunit_symtab (pc);
2218 if (cust != NULL && COMPUNIT_EPILOGUE_UNWIND_VALID (cust))
2219 return 0;
2220
2221 if (target_read_memory (pc, &insn, 1))
2222 return 0; /* Can't read memory at pc. */
2223
2224 if (insn != 0xc3) /* 'ret' instruction. */
2225 return 0;
2226
2227 return 1;
2228 }
2229
2230 static int
2231 i386_epilogue_frame_sniffer (const struct frame_unwind *self,
2232 struct frame_info *this_frame,
2233 void **this_prologue_cache)
2234 {
2235 if (frame_relative_level (this_frame) == 0)
2236 return i386_stack_frame_destroyed_p (get_frame_arch (this_frame),
2237 get_frame_pc (this_frame));
2238 else
2239 return 0;
2240 }
2241
2242 static struct i386_frame_cache *
2243 i386_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache)
2244 {
2245 struct i386_frame_cache *cache;
2246 CORE_ADDR sp;
2247
2248 if (*this_cache)
2249 return (struct i386_frame_cache *) *this_cache;
2250
2251 cache = i386_alloc_frame_cache ();
2252 *this_cache = cache;
2253
2254 TRY
2255 {
2256 cache->pc = get_frame_func (this_frame);
2257
2258 /* At this point the stack looks as if we just entered the
2259 function, with the return address at the top of the
2260 stack. */
2261 sp = get_frame_register_unsigned (this_frame, I386_ESP_REGNUM);
2262 cache->base = sp + cache->sp_offset;
2263 cache->saved_sp = cache->base + 8;
2264 cache->saved_regs[I386_EIP_REGNUM] = cache->base + 4;
2265
2266 cache->base_p = 1;
2267 }
2268 CATCH (ex, RETURN_MASK_ERROR)
2269 {
2270 if (ex.error != NOT_AVAILABLE_ERROR)
2271 throw_exception (ex);
2272 }
2273 END_CATCH
2274
2275 return cache;
2276 }
2277
2278 static enum unwind_stop_reason
2279 i386_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame,
2280 void **this_cache)
2281 {
2282 struct i386_frame_cache *cache =
2283 i386_epilogue_frame_cache (this_frame, this_cache);
2284
2285 if (!cache->base_p)
2286 return UNWIND_UNAVAILABLE;
2287
2288 return UNWIND_NO_REASON;
2289 }
2290
2291 static void
2292 i386_epilogue_frame_this_id (struct frame_info *this_frame,
2293 void **this_cache,
2294 struct frame_id *this_id)
2295 {
2296 struct i386_frame_cache *cache =
2297 i386_epilogue_frame_cache (this_frame, this_cache);
2298
2299 if (!cache->base_p)
2300 (*this_id) = frame_id_build_unavailable_stack (cache->pc);
2301 else
2302 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
2303 }
2304
2305 static struct value *
2306 i386_epilogue_frame_prev_register (struct frame_info *this_frame,
2307 void **this_cache, int regnum)
2308 {
2309 /* Make sure we've initialized the cache. */
2310 i386_epilogue_frame_cache (this_frame, this_cache);
2311
2312 return i386_frame_prev_register (this_frame, this_cache, regnum);
2313 }
2314
2315 static const struct frame_unwind i386_epilogue_frame_unwind =
2316 {
2317 NORMAL_FRAME,
2318 i386_epilogue_frame_unwind_stop_reason,
2319 i386_epilogue_frame_this_id,
2320 i386_epilogue_frame_prev_register,
2321 NULL,
2322 i386_epilogue_frame_sniffer
2323 };
2324
2325
2326 /* Stack-based trampolines. */
2327
2328 /* These trampolines are used on cross x86 targets, when taking the
2329 address of a nested function. When executing these trampolines,
2330 no stack frame is set up, so we are in a similar situation as in
2331 epilogues and i386_epilogue_frame_this_id can be re-used. */
2332
2333 /* Static chain passed in register. */
2334
2335 struct i386_insn i386_tramp_chain_in_reg_insns[] =
2336 {
2337 /* `movl imm32, %eax' and `movl imm32, %ecx' */
2338 { 5, { 0xb8 }, { 0xfe } },
2339
2340 /* `jmp imm32' */
2341 { 5, { 0xe9 }, { 0xff } },
2342
2343 {0}
2344 };
2345
2346 /* Static chain passed on stack (when regparm=3). */
2347
2348 struct i386_insn i386_tramp_chain_on_stack_insns[] =
2349 {
2350 /* `push imm32' */
2351 { 5, { 0x68 }, { 0xff } },
2352
2353 /* `jmp imm32' */
2354 { 5, { 0xe9 }, { 0xff } },
2355
2356 {0}
2357 };
2358
2359 /* Return whether PC points inside a stack trampoline. */
2360
2361 static int
2362 i386_in_stack_tramp_p (CORE_ADDR pc)
2363 {
2364 gdb_byte insn;
2365 const char *name;
2366
2367 /* A stack trampoline is detected if no name is associated
2368 to the current pc and if it points inside a trampoline
2369 sequence. */
2370
2371 find_pc_partial_function (pc, &name, NULL, NULL);
2372 if (name)
2373 return 0;
2374
2375 if (target_read_memory (pc, &insn, 1))
2376 return 0;
2377
2378 if (!i386_match_insn_block (pc, i386_tramp_chain_in_reg_insns)
2379 && !i386_match_insn_block (pc, i386_tramp_chain_on_stack_insns))
2380 return 0;
2381
2382 return 1;
2383 }
2384
2385 static int
2386 i386_stack_tramp_frame_sniffer (const struct frame_unwind *self,
2387 struct frame_info *this_frame,
2388 void **this_cache)
2389 {
2390 if (frame_relative_level (this_frame) == 0)
2391 return i386_in_stack_tramp_p (get_frame_pc (this_frame));
2392 else
2393 return 0;
2394 }
2395
2396 static const struct frame_unwind i386_stack_tramp_frame_unwind =
2397 {
2398 NORMAL_FRAME,
2399 i386_epilogue_frame_unwind_stop_reason,
2400 i386_epilogue_frame_this_id,
2401 i386_epilogue_frame_prev_register,
2402 NULL,
2403 i386_stack_tramp_frame_sniffer
2404 };
2405
2406 /* Generate a bytecode expression to get the value of the saved PC. */
2407
2408 static void
2409 i386_gen_return_address (struct gdbarch *gdbarch,
2410 struct agent_expr *ax, struct axs_value *value,
2411 CORE_ADDR scope)
2412 {
2413 /* The following sequence assumes the traditional use of the base
2414 register. */
2415 ax_reg (ax, I386_EBP_REGNUM);
2416 ax_const_l (ax, 4);
2417 ax_simple (ax, aop_add);
2418 value->type = register_type (gdbarch, I386_EIP_REGNUM);
2419 value->kind = axs_lvalue_memory;
2420 }
2421
2422
2423 /* Signal trampolines. */
2424
2425 static struct i386_frame_cache *
2426 i386_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache)
2427 {
2428 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2429 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2430 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2431 struct i386_frame_cache *cache;
2432 CORE_ADDR addr;
2433 gdb_byte buf[4];
2434
2435 if (*this_cache)
2436 return (struct i386_frame_cache *) *this_cache;
2437
2438 cache = i386_alloc_frame_cache ();
2439
2440 TRY
2441 {
2442 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
2443 cache->base = extract_unsigned_integer (buf, 4, byte_order) - 4;
2444
2445 addr = tdep->sigcontext_addr (this_frame);
2446 if (tdep->sc_reg_offset)
2447 {
2448 int i;
2449
2450 gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS);
2451
2452 for (i = 0; i < tdep->sc_num_regs; i++)
2453 if (tdep->sc_reg_offset[i] != -1)
2454 cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];
2455 }
2456 else
2457 {
2458 cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset;
2459 cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset;
2460 }
2461
2462 cache->base_p = 1;
2463 }
2464 CATCH (ex, RETURN_MASK_ERROR)
2465 {
2466 if (ex.error != NOT_AVAILABLE_ERROR)
2467 throw_exception (ex);
2468 }
2469 END_CATCH
2470
2471 *this_cache = cache;
2472 return cache;
2473 }
2474
2475 static enum unwind_stop_reason
2476 i386_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame,
2477 void **this_cache)
2478 {
2479 struct i386_frame_cache *cache =
2480 i386_sigtramp_frame_cache (this_frame, this_cache);
2481
2482 if (!cache->base_p)
2483 return UNWIND_UNAVAILABLE;
2484
2485 return UNWIND_NO_REASON;
2486 }
2487
2488 static void
2489 i386_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache,
2490 struct frame_id *this_id)
2491 {
2492 struct i386_frame_cache *cache =
2493 i386_sigtramp_frame_cache (this_frame, this_cache);
2494
2495 if (!cache->base_p)
2496 (*this_id) = frame_id_build_unavailable_stack (get_frame_pc (this_frame));
2497 else
2498 {
2499 /* See the end of i386_push_dummy_call. */
2500 (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame));
2501 }
2502 }
2503
2504 static struct value *
2505 i386_sigtramp_frame_prev_register (struct frame_info *this_frame,
2506 void **this_cache, int regnum)
2507 {
2508 /* Make sure we've initialized the cache. */
2509 i386_sigtramp_frame_cache (this_frame, this_cache);
2510
2511 return i386_frame_prev_register (this_frame, this_cache, regnum);
2512 }
2513
2514 static int
2515 i386_sigtramp_frame_sniffer (const struct frame_unwind *self,
2516 struct frame_info *this_frame,
2517 void **this_prologue_cache)
2518 {
2519 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
2520
2521 /* We shouldn't even bother if we don't have a sigcontext_addr
2522 handler. */
2523 if (tdep->sigcontext_addr == NULL)
2524 return 0;
2525
2526 if (tdep->sigtramp_p != NULL)
2527 {
2528 if (tdep->sigtramp_p (this_frame))
2529 return 1;
2530 }
2531
2532 if (tdep->sigtramp_start != 0)
2533 {
2534 CORE_ADDR pc = get_frame_pc (this_frame);
2535
2536 gdb_assert (tdep->sigtramp_end != 0);
2537 if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end)
2538 return 1;
2539 }
2540
2541 return 0;
2542 }
2543
2544 static const struct frame_unwind i386_sigtramp_frame_unwind =
2545 {
2546 SIGTRAMP_FRAME,
2547 i386_sigtramp_frame_unwind_stop_reason,
2548 i386_sigtramp_frame_this_id,
2549 i386_sigtramp_frame_prev_register,
2550 NULL,
2551 i386_sigtramp_frame_sniffer
2552 };
2553
2554
2555 static CORE_ADDR
2556 i386_frame_base_address (struct frame_info *this_frame, void **this_cache)
2557 {
2558 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2559
2560 return cache->base;
2561 }
2562
2563 static const struct frame_base i386_frame_base =
2564 {
2565 &i386_frame_unwind,
2566 i386_frame_base_address,
2567 i386_frame_base_address,
2568 i386_frame_base_address
2569 };
2570
2571 static struct frame_id
2572 i386_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2573 {
2574 CORE_ADDR fp;
2575
2576 fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM);
2577
2578 /* See the end of i386_push_dummy_call. */
2579 return frame_id_build (fp + 8, get_frame_pc (this_frame));
2580 }
2581
2582 /* _Decimal128 function return values need 16-byte alignment on the
2583 stack. */
2584
2585 static CORE_ADDR
2586 i386_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
2587 {
2588 return sp & -(CORE_ADDR)16;
2589 }
2590
2591
2592 /* Figure out where the longjmp will land. Slurp the args out of the
2593 stack. We expect the first arg to be a pointer to the jmp_buf
2594 structure from which we extract the address that we will land at.
2595 This address is copied into PC. This routine returns non-zero on
2596 success. */
2597
2598 static int
2599 i386_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
2600 {
2601 gdb_byte buf[4];
2602 CORE_ADDR sp, jb_addr;
2603 struct gdbarch *gdbarch = get_frame_arch (frame);
2604 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2605 int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset;
2606
2607 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2608 longjmp will land. */
2609 if (jb_pc_offset == -1)
2610 return 0;
2611
2612 get_frame_register (frame, I386_ESP_REGNUM, buf);
2613 sp = extract_unsigned_integer (buf, 4, byte_order);
2614 if (target_read_memory (sp + 4, buf, 4))
2615 return 0;
2616
2617 jb_addr = extract_unsigned_integer (buf, 4, byte_order);
2618 if (target_read_memory (jb_addr + jb_pc_offset, buf, 4))
2619 return 0;
2620
2621 *pc = extract_unsigned_integer (buf, 4, byte_order);
2622 return 1;
2623 }
2624
2625
2626 /* Check whether TYPE must be 16-byte-aligned when passed as a
2627 function argument. 16-byte vectors, _Decimal128 and structures or
2628 unions containing such types must be 16-byte-aligned; other
2629 arguments are 4-byte-aligned. */
2630
2631 static int
2632 i386_16_byte_align_p (struct type *type)
2633 {
2634 type = check_typedef (type);
2635 if ((TYPE_CODE (type) == TYPE_CODE_DECFLOAT
2636 || (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type)))
2637 && TYPE_LENGTH (type) == 16)
2638 return 1;
2639 if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
2640 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type));
2641 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
2642 || TYPE_CODE (type) == TYPE_CODE_UNION)
2643 {
2644 int i;
2645 for (i = 0; i < TYPE_NFIELDS (type); i++)
2646 {
2647 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type, i)))
2648 return 1;
2649 }
2650 }
2651 return 0;
2652 }
2653
2654 /* Implementation for set_gdbarch_push_dummy_code. */
2655
2656 static CORE_ADDR
2657 i386_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr,
2658 struct value **args, int nargs, struct type *value_type,
2659 CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
2660 struct regcache *regcache)
2661 {
2662 /* Use 0xcc breakpoint - 1 byte. */
2663 *bp_addr = sp - 1;
2664 *real_pc = funaddr;
2665
2666 /* Keep the stack aligned. */
2667 return sp - 16;
2668 }
2669
2670 static CORE_ADDR
2671 i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
2672 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
2673 struct value **args, CORE_ADDR sp, int struct_return,
2674 CORE_ADDR struct_addr)
2675 {
2676 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2677 gdb_byte buf[4];
2678 int i;
2679 int write_pass;
2680 int args_space = 0;
2681
2682 /* BND registers can be in arbitrary values at the moment of the
2683 inferior call. This can cause boundary violations that are not
2684 due to a real bug or even desired by the user. The best to be done
2685 is set the BND registers to allow access to the whole memory, INIT
2686 state, before pushing the inferior call. */
2687 i387_reset_bnd_regs (gdbarch, regcache);
2688
2689 /* Determine the total space required for arguments and struct
2690 return address in a first pass (allowing for 16-byte-aligned
2691 arguments), then push arguments in a second pass. */
2692
2693 for (write_pass = 0; write_pass < 2; write_pass++)
2694 {
2695 int args_space_used = 0;
2696
2697 if (struct_return)
2698 {
2699 if (write_pass)
2700 {
2701 /* Push value address. */
2702 store_unsigned_integer (buf, 4, byte_order, struct_addr);
2703 write_memory (sp, buf, 4);
2704 args_space_used += 4;
2705 }
2706 else
2707 args_space += 4;
2708 }
2709
2710 for (i = 0; i < nargs; i++)
2711 {
2712 int len = TYPE_LENGTH (value_enclosing_type (args[i]));
2713
2714 if (write_pass)
2715 {
2716 if (i386_16_byte_align_p (value_enclosing_type (args[i])))
2717 args_space_used = align_up (args_space_used, 16);
2718
2719 write_memory (sp + args_space_used,
2720 value_contents_all (args[i]), len);
2721 /* The System V ABI says that:
2722
2723 "An argument's size is increased, if necessary, to make it a
2724 multiple of [32-bit] words. This may require tail padding,
2725 depending on the size of the argument."
2726
2727 This makes sure the stack stays word-aligned. */
2728 args_space_used += align_up (len, 4);
2729 }
2730 else
2731 {
2732 if (i386_16_byte_align_p (value_enclosing_type (args[i])))
2733 args_space = align_up (args_space, 16);
2734 args_space += align_up (len, 4);
2735 }
2736 }
2737
2738 if (!write_pass)
2739 {
2740 sp -= args_space;
2741
2742 /* The original System V ABI only requires word alignment,
2743 but modern incarnations need 16-byte alignment in order
2744 to support SSE. Since wasting a few bytes here isn't
2745 harmful we unconditionally enforce 16-byte alignment. */
2746 sp &= ~0xf;
2747 }
2748 }
2749
2750 /* Store return address. */
2751 sp -= 4;
2752 store_unsigned_integer (buf, 4, byte_order, bp_addr);
2753 write_memory (sp, buf, 4);
2754
2755 /* Finally, update the stack pointer... */
2756 store_unsigned_integer (buf, 4, byte_order, sp);
2757 regcache_cooked_write (regcache, I386_ESP_REGNUM, buf);
2758
2759 /* ...and fake a frame pointer. */
2760 regcache_cooked_write (regcache, I386_EBP_REGNUM, buf);
2761
2762 /* MarkK wrote: This "+ 8" is all over the place:
2763 (i386_frame_this_id, i386_sigtramp_frame_this_id,
2764 i386_dummy_id). It's there, since all frame unwinders for
2765 a given target have to agree (within a certain margin) on the
2766 definition of the stack address of a frame. Otherwise frame id
2767 comparison might not work correctly. Since DWARF2/GCC uses the
2768 stack address *before* the function call as a frame's CFA. On
2769 the i386, when %ebp is used as a frame pointer, the offset
2770 between the contents %ebp and the CFA as defined by GCC. */
2771 return sp + 8;
2772 }
2773
2774 /* These registers are used for returning integers (and on some
2775 targets also for returning `struct' and `union' values when their
2776 size and alignment match an integer type). */
2777 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
2778 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
2779
2780 /* Read, for architecture GDBARCH, a function return value of TYPE
2781 from REGCACHE, and copy that into VALBUF. */
2782
2783 static void
2784 i386_extract_return_value (struct gdbarch *gdbarch, struct type *type,
2785 struct regcache *regcache, gdb_byte *valbuf)
2786 {
2787 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2788 int len = TYPE_LENGTH (type);
2789 gdb_byte buf[I386_MAX_REGISTER_SIZE];
2790
2791 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2792 {
2793 if (tdep->st0_regnum < 0)
2794 {
2795 warning (_("Cannot find floating-point return value."));
2796 memset (valbuf, 0, len);
2797 return;
2798 }
2799
2800 /* Floating-point return values can be found in %st(0). Convert
2801 its contents to the desired type. This is probably not
2802 exactly how it would happen on the target itself, but it is
2803 the best we can do. */
2804 regcache_raw_read (regcache, I386_ST0_REGNUM, buf);
2805 target_float_convert (buf, i387_ext_type (gdbarch), valbuf, type);
2806 }
2807 else
2808 {
2809 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM);
2810 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM);
2811
2812 if (len <= low_size)
2813 {
2814 regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf);
2815 memcpy (valbuf, buf, len);
2816 }
2817 else if (len <= (low_size + high_size))
2818 {
2819 regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf);
2820 memcpy (valbuf, buf, low_size);
2821 regcache_raw_read (regcache, HIGH_RETURN_REGNUM, buf);
2822 memcpy (valbuf + low_size, buf, len - low_size);
2823 }
2824 else
2825 internal_error (__FILE__, __LINE__,
2826 _("Cannot extract return value of %d bytes long."),
2827 len);
2828 }
2829 }
2830
2831 /* Write, for architecture GDBARCH, a function return value of TYPE
2832 from VALBUF into REGCACHE. */
2833
2834 static void
2835 i386_store_return_value (struct gdbarch *gdbarch, struct type *type,
2836 struct regcache *regcache, const gdb_byte *valbuf)
2837 {
2838 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2839 int len = TYPE_LENGTH (type);
2840
2841 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2842 {
2843 ULONGEST fstat;
2844 gdb_byte buf[I386_MAX_REGISTER_SIZE];
2845
2846 if (tdep->st0_regnum < 0)
2847 {
2848 warning (_("Cannot set floating-point return value."));
2849 return;
2850 }
2851
2852 /* Returning floating-point values is a bit tricky. Apart from
2853 storing the return value in %st(0), we have to simulate the
2854 state of the FPU at function return point. */
2855
2856 /* Convert the value found in VALBUF to the extended
2857 floating-point format used by the FPU. This is probably
2858 not exactly how it would happen on the target itself, but
2859 it is the best we can do. */
2860 target_float_convert (valbuf, type, buf, i387_ext_type (gdbarch));
2861 regcache_raw_write (regcache, I386_ST0_REGNUM, buf);
2862
2863 /* Set the top of the floating-point register stack to 7. The
2864 actual value doesn't really matter, but 7 is what a normal
2865 function return would end up with if the program started out
2866 with a freshly initialized FPU. */
2867 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
2868 fstat |= (7 << 11);
2869 regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat);
2870
2871 /* Mark %st(1) through %st(7) as empty. Since we set the top of
2872 the floating-point register stack to 7, the appropriate value
2873 for the tag word is 0x3fff. */
2874 regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff);
2875 }
2876 else
2877 {
2878 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM);
2879 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM);
2880
2881 if (len <= low_size)
2882 regcache_raw_write_part (regcache, LOW_RETURN_REGNUM, 0, len, valbuf);
2883 else if (len <= (low_size + high_size))
2884 {
2885 regcache_raw_write (regcache, LOW_RETURN_REGNUM, valbuf);
2886 regcache_raw_write_part (regcache, HIGH_RETURN_REGNUM, 0,
2887 len - low_size, valbuf + low_size);
2888 }
2889 else
2890 internal_error (__FILE__, __LINE__,
2891 _("Cannot store return value of %d bytes long."), len);
2892 }
2893 }
2894
2895
2896 /* This is the variable that is set with "set struct-convention", and
2897 its legitimate values. */
2898 static const char default_struct_convention[] = "default";
2899 static const char pcc_struct_convention[] = "pcc";
2900 static const char reg_struct_convention[] = "reg";
2901 static const char *const valid_conventions[] =
2902 {
2903 default_struct_convention,
2904 pcc_struct_convention,
2905 reg_struct_convention,
2906 NULL
2907 };
2908 static const char *struct_convention = default_struct_convention;
2909
2910 /* Return non-zero if TYPE, which is assumed to be a structure,
2911 a union type, or an array type, should be returned in registers
2912 for architecture GDBARCH. */
2913
2914 static int
2915 i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type)
2916 {
2917 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2918 enum type_code code = TYPE_CODE (type);
2919 int len = TYPE_LENGTH (type);
2920
2921 gdb_assert (code == TYPE_CODE_STRUCT
2922 || code == TYPE_CODE_UNION
2923 || code == TYPE_CODE_ARRAY);
2924
2925 if (struct_convention == pcc_struct_convention
2926 || (struct_convention == default_struct_convention
2927 && tdep->struct_return == pcc_struct_return))
2928 return 0;
2929
2930 /* Structures consisting of a single `float', `double' or 'long
2931 double' member are returned in %st(0). */
2932 if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1)
2933 {
2934 type = check_typedef (TYPE_FIELD_TYPE (type, 0));
2935 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2936 return (len == 4 || len == 8 || len == 12);
2937 }
2938
2939 return (len == 1 || len == 2 || len == 4 || len == 8);
2940 }
2941
2942 /* Determine, for architecture GDBARCH, how a return value of TYPE
2943 should be returned. If it is supposed to be returned in registers,
2944 and READBUF is non-zero, read the appropriate value from REGCACHE,
2945 and copy it into READBUF. If WRITEBUF is non-zero, write the value
2946 from WRITEBUF into REGCACHE. */
2947
2948 static enum return_value_convention
2949 i386_return_value (struct gdbarch *gdbarch, struct value *function,
2950 struct type *type, struct regcache *regcache,
2951 gdb_byte *readbuf, const gdb_byte *writebuf)
2952 {
2953 enum type_code code = TYPE_CODE (type);
2954
2955 if (((code == TYPE_CODE_STRUCT
2956 || code == TYPE_CODE_UNION
2957 || code == TYPE_CODE_ARRAY)
2958 && !i386_reg_struct_return_p (gdbarch, type))
2959 /* Complex double and long double uses the struct return covention. */
2960 || (code == TYPE_CODE_COMPLEX && TYPE_LENGTH (type) == 16)
2961 || (code == TYPE_CODE_COMPLEX && TYPE_LENGTH (type) == 24)
2962 /* 128-bit decimal float uses the struct return convention. */
2963 || (code == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) == 16))
2964 {
2965 /* The System V ABI says that:
2966
2967 "A function that returns a structure or union also sets %eax
2968 to the value of the original address of the caller's area
2969 before it returns. Thus when the caller receives control
2970 again, the address of the returned object resides in register
2971 %eax and can be used to access the object."
2972
2973 So the ABI guarantees that we can always find the return
2974 value just after the function has returned. */
2975
2976 /* Note that the ABI doesn't mention functions returning arrays,
2977 which is something possible in certain languages such as Ada.
2978 In this case, the value is returned as if it was wrapped in
2979 a record, so the convention applied to records also applies
2980 to arrays. */
2981
2982 if (readbuf)
2983 {
2984 ULONGEST addr;
2985
2986 regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr);
2987 read_memory (addr, readbuf, TYPE_LENGTH (type));
2988 }
2989
2990 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
2991 }
2992
2993 /* This special case is for structures consisting of a single
2994 `float', `double' or 'long double' member. These structures are
2995 returned in %st(0). For these structures, we call ourselves
2996 recursively, changing TYPE into the type of the first member of
2997 the structure. Since that should work for all structures that
2998 have only one member, we don't bother to check the member's type
2999 here. */
3000 if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1)
3001 {
3002 type = check_typedef (TYPE_FIELD_TYPE (type, 0));
3003 return i386_return_value (gdbarch, function, type, regcache,
3004 readbuf, writebuf);
3005 }
3006
3007 if (readbuf)
3008 i386_extract_return_value (gdbarch, type, regcache, readbuf);
3009 if (writebuf)
3010 i386_store_return_value (gdbarch, type, regcache, writebuf);
3011
3012 return RETURN_VALUE_REGISTER_CONVENTION;
3013 }
3014
3015
3016 struct type *
3017 i387_ext_type (struct gdbarch *gdbarch)
3018 {
3019 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3020
3021 if (!tdep->i387_ext_type)
3022 {
3023 tdep->i387_ext_type = tdesc_find_type (gdbarch, "i387_ext");
3024 gdb_assert (tdep->i387_ext_type != NULL);
3025 }
3026
3027 return tdep->i387_ext_type;
3028 }
3029
3030 /* Construct type for pseudo BND registers. We can't use
3031 tdesc_find_type since a complement of one value has to be used
3032 to describe the upper bound. */
3033
3034 static struct type *
3035 i386_bnd_type (struct gdbarch *gdbarch)
3036 {
3037 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3038
3039
3040 if (!tdep->i386_bnd_type)
3041 {
3042 struct type *t;
3043 const struct builtin_type *bt = builtin_type (gdbarch);
3044
3045 /* The type we're building is described bellow: */
3046 #if 0
3047 struct __bound128
3048 {
3049 void *lbound;
3050 void *ubound; /* One complement of raw ubound field. */
3051 };
3052 #endif
3053
3054 t = arch_composite_type (gdbarch,
3055 "__gdb_builtin_type_bound128", TYPE_CODE_STRUCT);
3056
3057 append_composite_type_field (t, "lbound", bt->builtin_data_ptr);
3058 append_composite_type_field (t, "ubound", bt->builtin_data_ptr);
3059
3060 TYPE_NAME (t) = "builtin_type_bound128";
3061 tdep->i386_bnd_type = t;
3062 }
3063
3064 return tdep->i386_bnd_type;
3065 }
3066
3067 /* Construct vector type for pseudo ZMM registers. We can't use
3068 tdesc_find_type since ZMM isn't described in target description. */
3069
3070 static struct type *
3071 i386_zmm_type (struct gdbarch *gdbarch)
3072 {
3073 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3074
3075 if (!tdep->i386_zmm_type)
3076 {
3077 const struct builtin_type *bt = builtin_type (gdbarch);
3078
3079 /* The type we're building is this: */
3080 #if 0
3081 union __gdb_builtin_type_vec512i
3082 {
3083 int128_t uint128[4];
3084 int64_t v4_int64[8];
3085 int32_t v8_int32[16];
3086 int16_t v16_int16[32];
3087 int8_t v32_int8[64];
3088 double v4_double[8];
3089 float v8_float[16];
3090 };
3091 #endif
3092
3093 struct type *t;
3094
3095 t = arch_composite_type (gdbarch,
3096 "__gdb_builtin_type_vec512i", TYPE_CODE_UNION);
3097 append_composite_type_field (t, "v16_float",
3098 init_vector_type (bt->builtin_float, 16));
3099 append_composite_type_field (t, "v8_double",
3100 init_vector_type (bt->builtin_double, 8));
3101 append_composite_type_field (t, "v64_int8",
3102 init_vector_type (bt->builtin_int8, 64));
3103 append_composite_type_field (t, "v32_int16",
3104 init_vector_type (bt->builtin_int16, 32));
3105 append_composite_type_field (t, "v16_int32",
3106 init_vector_type (bt->builtin_int32, 16));
3107 append_composite_type_field (t, "v8_int64",
3108 init_vector_type (bt->builtin_int64, 8));
3109 append_composite_type_field (t, "v4_int128",
3110 init_vector_type (bt->builtin_int128, 4));
3111
3112 TYPE_VECTOR (t) = 1;
3113 TYPE_NAME (t) = "builtin_type_vec512i";
3114 tdep->i386_zmm_type = t;
3115 }
3116
3117 return tdep->i386_zmm_type;
3118 }
3119
3120 /* Construct vector type for pseudo YMM registers. We can't use
3121 tdesc_find_type since YMM isn't described in target description. */
3122
3123 static struct type *
3124 i386_ymm_type (struct gdbarch *gdbarch)
3125 {
3126 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3127
3128 if (!tdep->i386_ymm_type)
3129 {
3130 const struct builtin_type *bt = builtin_type (gdbarch);
3131
3132 /* The type we're building is this: */
3133 #if 0
3134 union __gdb_builtin_type_vec256i
3135 {
3136 int128_t uint128[2];
3137 int64_t v2_int64[4];
3138 int32_t v4_int32[8];
3139 int16_t v8_int16[16];
3140 int8_t v16_int8[32];
3141 double v2_double[4];
3142 float v4_float[8];
3143 };
3144 #endif
3145
3146 struct type *t;
3147
3148 t = arch_composite_type (gdbarch,
3149 "__gdb_builtin_type_vec256i", TYPE_CODE_UNION);
3150 append_composite_type_field (t, "v8_float",
3151 init_vector_type (bt->builtin_float, 8));
3152 append_composite_type_field (t, "v4_double",
3153 init_vector_type (bt->builtin_double, 4));
3154 append_composite_type_field (t, "v32_int8",
3155 init_vector_type (bt->builtin_int8, 32));
3156 append_composite_type_field (t, "v16_int16",
3157 init_vector_type (bt->builtin_int16, 16));
3158 append_composite_type_field (t, "v8_int32",
3159 init_vector_type (bt->builtin_int32, 8));
3160 append_composite_type_field (t, "v4_int64",
3161 init_vector_type (bt->builtin_int64, 4));
3162 append_composite_type_field (t, "v2_int128",
3163 init_vector_type (bt->builtin_int128, 2));
3164
3165 TYPE_VECTOR (t) = 1;
3166 TYPE_NAME (t) = "builtin_type_vec256i";
3167 tdep->i386_ymm_type = t;
3168 }
3169
3170 return tdep->i386_ymm_type;
3171 }
3172
3173 /* Construct vector type for MMX registers. */
3174 static struct type *
3175 i386_mmx_type (struct gdbarch *gdbarch)
3176 {
3177 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3178
3179 if (!tdep->i386_mmx_type)
3180 {
3181 const struct builtin_type *bt = builtin_type (gdbarch);
3182
3183 /* The type we're building is this: */
3184 #if 0
3185 union __gdb_builtin_type_vec64i
3186 {
3187 int64_t uint64;
3188 int32_t v2_int32[2];
3189 int16_t v4_int16[4];
3190 int8_t v8_int8[8];
3191 };
3192 #endif
3193
3194 struct type *t;
3195
3196 t = arch_composite_type (gdbarch,
3197 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION);
3198
3199 append_composite_type_field (t, "uint64", bt->builtin_int64);
3200 append_composite_type_field (t, "v2_int32",
3201 init_vector_type (bt->builtin_int32, 2));
3202 append_composite_type_field (t, "v4_int16",
3203 init_vector_type (bt->builtin_int16, 4));
3204 append_composite_type_field (t, "v8_int8",
3205 init_vector_type (bt->builtin_int8, 8));
3206
3207 TYPE_VECTOR (t) = 1;
3208 TYPE_NAME (t) = "builtin_type_vec64i";
3209 tdep->i386_mmx_type = t;
3210 }
3211
3212 return tdep->i386_mmx_type;
3213 }
3214
3215 /* Return the GDB type object for the "standard" data type of data in
3216 register REGNUM. */
3217
3218 struct type *
3219 i386_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
3220 {
3221 if (i386_bnd_regnum_p (gdbarch, regnum))
3222 return i386_bnd_type (gdbarch);
3223 if (i386_mmx_regnum_p (gdbarch, regnum))
3224 return i386_mmx_type (gdbarch);
3225 else if (i386_ymm_regnum_p (gdbarch, regnum))
3226 return i386_ymm_type (gdbarch);
3227 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
3228 return i386_ymm_type (gdbarch);
3229 else if (i386_zmm_regnum_p (gdbarch, regnum))
3230 return i386_zmm_type (gdbarch);
3231 else
3232 {
3233 const struct builtin_type *bt = builtin_type (gdbarch);
3234 if (i386_byte_regnum_p (gdbarch, regnum))
3235 return bt->builtin_int8;
3236 else if (i386_word_regnum_p (gdbarch, regnum))
3237 return bt->builtin_int16;
3238 else if (i386_dword_regnum_p (gdbarch, regnum))
3239 return bt->builtin_int32;
3240 else if (i386_k_regnum_p (gdbarch, regnum))
3241 return bt->builtin_int64;
3242 }
3243
3244 internal_error (__FILE__, __LINE__, _("invalid regnum"));
3245 }
3246
3247 /* Map a cooked register onto a raw register or memory. For the i386,
3248 the MMX registers need to be mapped onto floating point registers. */
3249
3250 static int
3251 i386_mmx_regnum_to_fp_regnum (struct regcache *regcache, int regnum)
3252 {
3253 struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ());
3254 int mmxreg, fpreg;
3255 ULONGEST fstat;
3256 int tos;
3257
3258 mmxreg = regnum - tdep->mm0_regnum;
3259 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
3260 tos = (fstat >> 11) & 0x7;
3261 fpreg = (mmxreg + tos) % 8;
3262
3263 return (I387_ST0_REGNUM (tdep) + fpreg);
3264 }
3265
3266 /* A helper function for us by i386_pseudo_register_read_value and
3267 amd64_pseudo_register_read_value. It does all the work but reads
3268 the data into an already-allocated value. */
3269
3270 void
3271 i386_pseudo_register_read_into_value (struct gdbarch *gdbarch,
3272 struct regcache *regcache,
3273 int regnum,
3274 struct value *result_value)
3275 {
3276 gdb_byte raw_buf[I386_MAX_REGISTER_SIZE];
3277 enum register_status status;
3278 gdb_byte *buf = value_contents_raw (result_value);
3279
3280 if (i386_mmx_regnum_p (gdbarch, regnum))
3281 {
3282 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
3283
3284 /* Extract (always little endian). */
3285 status = regcache_raw_read (regcache, fpnum, raw_buf);
3286 if (status != REG_VALID)
3287 mark_value_bytes_unavailable (result_value, 0,
3288 TYPE_LENGTH (value_type (result_value)));
3289 else
3290 memcpy (buf, raw_buf, register_size (gdbarch, regnum));
3291 }
3292 else
3293 {
3294 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3295 if (i386_bnd_regnum_p (gdbarch, regnum))
3296 {
3297 regnum -= tdep->bnd0_regnum;
3298
3299 /* Extract (always little endian). Read lower 128bits. */
3300 status = regcache_raw_read (regcache,
3301 I387_BND0R_REGNUM (tdep) + regnum,
3302 raw_buf);
3303 if (status != REG_VALID)
3304 mark_value_bytes_unavailable (result_value, 0, 16);
3305 else
3306 {
3307 enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ());
3308 LONGEST upper, lower;
3309 int size = TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr);
3310
3311 lower = extract_unsigned_integer (raw_buf, 8, byte_order);
3312 upper = extract_unsigned_integer (raw_buf + 8, 8, byte_order);
3313 upper = ~upper;
3314
3315 memcpy (buf, &lower, size);
3316 memcpy (buf + size, &upper, size);
3317 }
3318 }
3319 else if (i386_k_regnum_p (gdbarch, regnum))
3320 {
3321 regnum -= tdep->k0_regnum;
3322
3323 /* Extract (always little endian). */
3324 status = regcache_raw_read (regcache,
3325 tdep->k0_regnum + regnum,
3326 raw_buf);
3327 if (status != REG_VALID)
3328 mark_value_bytes_unavailable (result_value, 0, 8);
3329 else
3330 memcpy (buf, raw_buf, 8);
3331 }
3332 else if (i386_zmm_regnum_p (gdbarch, regnum))
3333 {
3334 regnum -= tdep->zmm0_regnum;
3335
3336 if (regnum < num_lower_zmm_regs)
3337 {
3338 /* Extract (always little endian). Read lower 128bits. */
3339 status = regcache_raw_read (regcache,
3340 I387_XMM0_REGNUM (tdep) + regnum,
3341 raw_buf);
3342 if (status != REG_VALID)
3343 mark_value_bytes_unavailable (result_value, 0, 16);
3344 else
3345 memcpy (buf, raw_buf, 16);
3346
3347 /* Extract (always little endian). Read upper 128bits. */
3348 status = regcache_raw_read (regcache,
3349 tdep->ymm0h_regnum + regnum,
3350 raw_buf);
3351 if (status != REG_VALID)
3352 mark_value_bytes_unavailable (result_value, 16, 16);
3353 else
3354 memcpy (buf + 16, raw_buf, 16);
3355 }
3356 else
3357 {
3358 /* Extract (always little endian). Read lower 128bits. */
3359 status = regcache_raw_read (regcache,
3360 I387_XMM16_REGNUM (tdep) + regnum
3361 - num_lower_zmm_regs,
3362 raw_buf);
3363 if (status != REG_VALID)
3364 mark_value_bytes_unavailable (result_value, 0, 16);
3365 else
3366 memcpy (buf, raw_buf, 16);
3367
3368 /* Extract (always little endian). Read upper 128bits. */
3369 status = regcache_raw_read (regcache,
3370 I387_YMM16H_REGNUM (tdep) + regnum
3371 - num_lower_zmm_regs,
3372 raw_buf);
3373 if (status != REG_VALID)
3374 mark_value_bytes_unavailable (result_value, 16, 16);
3375 else
3376 memcpy (buf + 16, raw_buf, 16);
3377 }
3378
3379 /* Read upper 256bits. */
3380 status = regcache_raw_read (regcache,
3381 tdep->zmm0h_regnum + regnum,
3382 raw_buf);
3383 if (status != REG_VALID)
3384 mark_value_bytes_unavailable (result_value, 32, 32);
3385 else
3386 memcpy (buf + 32, raw_buf, 32);
3387 }
3388 else if (i386_ymm_regnum_p (gdbarch, regnum))
3389 {
3390 regnum -= tdep->ymm0_regnum;
3391
3392 /* Extract (always little endian). Read lower 128bits. */
3393 status = regcache_raw_read (regcache,
3394 I387_XMM0_REGNUM (tdep) + regnum,
3395 raw_buf);
3396 if (status != REG_VALID)
3397 mark_value_bytes_unavailable (result_value, 0, 16);
3398 else
3399 memcpy (buf, raw_buf, 16);
3400 /* Read upper 128bits. */
3401 status = regcache_raw_read (regcache,
3402 tdep->ymm0h_regnum + regnum,
3403 raw_buf);
3404 if (status != REG_VALID)
3405 mark_value_bytes_unavailable (result_value, 16, 32);
3406 else
3407 memcpy (buf + 16, raw_buf, 16);
3408 }
3409 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
3410 {
3411 regnum -= tdep->ymm16_regnum;
3412 /* Extract (always little endian). Read lower 128bits. */
3413 status = regcache_raw_read (regcache,
3414 I387_XMM16_REGNUM (tdep) + regnum,
3415 raw_buf);
3416 if (status != REG_VALID)
3417 mark_value_bytes_unavailable (result_value, 0, 16);
3418 else
3419 memcpy (buf, raw_buf, 16);
3420 /* Read upper 128bits. */
3421 status = regcache_raw_read (regcache,
3422 tdep->ymm16h_regnum + regnum,
3423 raw_buf);
3424 if (status != REG_VALID)
3425 mark_value_bytes_unavailable (result_value, 16, 16);
3426 else
3427 memcpy (buf + 16, raw_buf, 16);
3428 }
3429 else if (i386_word_regnum_p (gdbarch, regnum))
3430 {
3431 int gpnum = regnum - tdep->ax_regnum;
3432
3433 /* Extract (always little endian). */
3434 status = regcache_raw_read (regcache, gpnum, raw_buf);
3435 if (status != REG_VALID)
3436 mark_value_bytes_unavailable (result_value, 0,
3437 TYPE_LENGTH (value_type (result_value)));
3438 else
3439 memcpy (buf, raw_buf, 2);
3440 }
3441 else if (i386_byte_regnum_p (gdbarch, regnum))
3442 {
3443 int gpnum = regnum - tdep->al_regnum;
3444
3445 /* Extract (always little endian). We read both lower and
3446 upper registers. */
3447 status = regcache_raw_read (regcache, gpnum % 4, raw_buf);
3448 if (status != REG_VALID)
3449 mark_value_bytes_unavailable (result_value, 0,
3450 TYPE_LENGTH (value_type (result_value)));
3451 else if (gpnum >= 4)
3452 memcpy (buf, raw_buf + 1, 1);
3453 else
3454 memcpy (buf, raw_buf, 1);
3455 }
3456 else
3457 internal_error (__FILE__, __LINE__, _("invalid regnum"));
3458 }
3459 }
3460
3461 static struct value *
3462 i386_pseudo_register_read_value (struct gdbarch *gdbarch,
3463 struct regcache *regcache,
3464 int regnum)
3465 {
3466 struct value *result;
3467
3468 result = allocate_value (register_type (gdbarch, regnum));
3469 VALUE_LVAL (result) = lval_register;
3470 VALUE_REGNUM (result) = regnum;
3471
3472 i386_pseudo_register_read_into_value (gdbarch, regcache, regnum, result);
3473
3474 return result;
3475 }
3476
3477 void
3478 i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
3479 int regnum, const gdb_byte *buf)
3480 {
3481 gdb_byte raw_buf[I386_MAX_REGISTER_SIZE];
3482
3483 if (i386_mmx_regnum_p (gdbarch, regnum))
3484 {
3485 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
3486
3487 /* Read ... */
3488 regcache_raw_read (regcache, fpnum, raw_buf);
3489 /* ... Modify ... (always little endian). */
3490 memcpy (raw_buf, buf, register_size (gdbarch, regnum));
3491 /* ... Write. */
3492 regcache_raw_write (regcache, fpnum, raw_buf);
3493 }
3494 else
3495 {
3496 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3497
3498 if (i386_bnd_regnum_p (gdbarch, regnum))
3499 {
3500 ULONGEST upper, lower;
3501 int size = TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr);
3502 enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ());
3503
3504 /* New values from input value. */
3505 regnum -= tdep->bnd0_regnum;
3506 lower = extract_unsigned_integer (buf, size, byte_order);
3507 upper = extract_unsigned_integer (buf + size, size, byte_order);
3508
3509 /* Fetching register buffer. */
3510 regcache_raw_read (regcache,
3511 I387_BND0R_REGNUM (tdep) + regnum,
3512 raw_buf);
3513
3514 upper = ~upper;
3515
3516 /* Set register bits. */
3517 memcpy (raw_buf, &lower, 8);
3518 memcpy (raw_buf + 8, &upper, 8);
3519
3520
3521 regcache_raw_write (regcache,
3522 I387_BND0R_REGNUM (tdep) + regnum,
3523 raw_buf);
3524 }
3525 else if (i386_k_regnum_p (gdbarch, regnum))
3526 {
3527 regnum -= tdep->k0_regnum;
3528
3529 regcache_raw_write (regcache,
3530 tdep->k0_regnum + regnum,
3531 buf);
3532 }
3533 else if (i386_zmm_regnum_p (gdbarch, regnum))
3534 {
3535 regnum -= tdep->zmm0_regnum;
3536
3537 if (regnum < num_lower_zmm_regs)
3538 {
3539 /* Write lower 128bits. */
3540 regcache_raw_write (regcache,
3541 I387_XMM0_REGNUM (tdep) + regnum,
3542 buf);
3543 /* Write upper 128bits. */
3544 regcache_raw_write (regcache,
3545 I387_YMM0_REGNUM (tdep) + regnum,
3546 buf + 16);
3547 }
3548 else
3549 {
3550 /* Write lower 128bits. */
3551 regcache_raw_write (regcache,
3552 I387_XMM16_REGNUM (tdep) + regnum
3553 - num_lower_zmm_regs,
3554 buf);
3555 /* Write upper 128bits. */
3556 regcache_raw_write (regcache,
3557 I387_YMM16H_REGNUM (tdep) + regnum
3558 - num_lower_zmm_regs,
3559 buf + 16);
3560 }
3561 /* Write upper 256bits. */
3562 regcache_raw_write (regcache,
3563 tdep->zmm0h_regnum + regnum,
3564 buf + 32);
3565 }
3566 else if (i386_ymm_regnum_p (gdbarch, regnum))
3567 {
3568 regnum -= tdep->ymm0_regnum;
3569
3570 /* ... Write lower 128bits. */
3571 regcache_raw_write (regcache,
3572 I387_XMM0_REGNUM (tdep) + regnum,
3573 buf);
3574 /* ... Write upper 128bits. */
3575 regcache_raw_write (regcache,
3576 tdep->ymm0h_regnum + regnum,
3577 buf + 16);
3578 }
3579 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
3580 {
3581 regnum -= tdep->ymm16_regnum;
3582
3583 /* ... Write lower 128bits. */
3584 regcache_raw_write (regcache,
3585 I387_XMM16_REGNUM (tdep) + regnum,
3586 buf);
3587 /* ... Write upper 128bits. */
3588 regcache_raw_write (regcache,
3589 tdep->ymm16h_regnum + regnum,
3590 buf + 16);
3591 }
3592 else if (i386_word_regnum_p (gdbarch, regnum))
3593 {
3594 int gpnum = regnum - tdep->ax_regnum;
3595
3596 /* Read ... */
3597 regcache_raw_read (regcache, gpnum, raw_buf);
3598 /* ... Modify ... (always little endian). */
3599 memcpy (raw_buf, buf, 2);
3600 /* ... Write. */
3601 regcache_raw_write (regcache, gpnum, raw_buf);
3602 }
3603 else if (i386_byte_regnum_p (gdbarch, regnum))
3604 {
3605 int gpnum = regnum - tdep->al_regnum;
3606
3607 /* Read ... We read both lower and upper registers. */
3608 regcache_raw_read (regcache, gpnum % 4, raw_buf);
3609 /* ... Modify ... (always little endian). */
3610 if (gpnum >= 4)
3611 memcpy (raw_buf + 1, buf, 1);
3612 else
3613 memcpy (raw_buf, buf, 1);
3614 /* ... Write. */
3615 regcache_raw_write (regcache, gpnum % 4, raw_buf);
3616 }
3617 else
3618 internal_error (__FILE__, __LINE__, _("invalid regnum"));
3619 }
3620 }
3621
3622 /* Implement the 'ax_pseudo_register_collect' gdbarch method. */
3623
3624 int
3625 i386_ax_pseudo_register_collect (struct gdbarch *gdbarch,
3626 struct agent_expr *ax, int regnum)
3627 {
3628 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3629
3630 if (i386_mmx_regnum_p (gdbarch, regnum))
3631 {
3632 /* MMX to FPU register mapping depends on current TOS. Let's just
3633 not care and collect everything... */
3634 int i;
3635
3636 ax_reg_mask (ax, I387_FSTAT_REGNUM (tdep));
3637 for (i = 0; i < 8; i++)
3638 ax_reg_mask (ax, I387_ST0_REGNUM (tdep) + i);
3639 return 0;
3640 }
3641 else if (i386_bnd_regnum_p (gdbarch, regnum))
3642 {
3643 regnum -= tdep->bnd0_regnum;
3644 ax_reg_mask (ax, I387_BND0R_REGNUM (tdep) + regnum);
3645 return 0;
3646 }
3647 else if (i386_k_regnum_p (gdbarch, regnum))
3648 {
3649 regnum -= tdep->k0_regnum;
3650 ax_reg_mask (ax, tdep->k0_regnum + regnum);
3651 return 0;
3652 }
3653 else if (i386_zmm_regnum_p (gdbarch, regnum))
3654 {
3655 regnum -= tdep->zmm0_regnum;
3656 if (regnum < num_lower_zmm_regs)
3657 {
3658 ax_reg_mask (ax, I387_XMM0_REGNUM (tdep) + regnum);
3659 ax_reg_mask (ax, tdep->ymm0h_regnum + regnum);
3660 }
3661 else
3662 {
3663 ax_reg_mask (ax, I387_XMM16_REGNUM (tdep) + regnum
3664 - num_lower_zmm_regs);
3665 ax_reg_mask (ax, I387_YMM16H_REGNUM (tdep) + regnum
3666 - num_lower_zmm_regs);
3667 }
3668 ax_reg_mask (ax, tdep->zmm0h_regnum + regnum);
3669 return 0;
3670 }
3671 else if (i386_ymm_regnum_p (gdbarch, regnum))
3672 {
3673 regnum -= tdep->ymm0_regnum;
3674 ax_reg_mask (ax, I387_XMM0_REGNUM (tdep) + regnum);
3675 ax_reg_mask (ax, tdep->ymm0h_regnum + regnum);
3676 return 0;
3677 }
3678 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
3679 {
3680 regnum -= tdep->ymm16_regnum;
3681 ax_reg_mask (ax, I387_XMM16_REGNUM (tdep) + regnum);
3682 ax_reg_mask (ax, tdep->ymm16h_regnum + regnum);
3683 return 0;
3684 }
3685 else if (i386_word_regnum_p (gdbarch, regnum))
3686 {
3687 int gpnum = regnum - tdep->ax_regnum;
3688
3689 ax_reg_mask (ax, gpnum);
3690 return 0;
3691 }
3692 else if (i386_byte_regnum_p (gdbarch, regnum))
3693 {
3694 int gpnum = regnum - tdep->al_regnum;
3695
3696 ax_reg_mask (ax, gpnum % 4);
3697 return 0;
3698 }
3699 else
3700 internal_error (__FILE__, __LINE__, _("invalid regnum"));
3701 return 1;
3702 }
3703
3704
3705 /* Return the register number of the register allocated by GCC after
3706 REGNUM, or -1 if there is no such register. */
3707
3708 static int
3709 i386_next_regnum (int regnum)
3710 {
3711 /* GCC allocates the registers in the order:
3712
3713 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
3714
3715 Since storing a variable in %esp doesn't make any sense we return
3716 -1 for %ebp and for %esp itself. */
3717 static int next_regnum[] =
3718 {
3719 I386_EDX_REGNUM, /* Slot for %eax. */
3720 I386_EBX_REGNUM, /* Slot for %ecx. */
3721 I386_ECX_REGNUM, /* Slot for %edx. */
3722 I386_ESI_REGNUM, /* Slot for %ebx. */
3723 -1, -1, /* Slots for %esp and %ebp. */
3724 I386_EDI_REGNUM, /* Slot for %esi. */
3725 I386_EBP_REGNUM /* Slot for %edi. */
3726 };
3727
3728 if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0]))
3729 return next_regnum[regnum];
3730
3731 return -1;
3732 }
3733
3734 /* Return nonzero if a value of type TYPE stored in register REGNUM
3735 needs any special handling. */
3736
3737 static int
3738 i386_convert_register_p (struct gdbarch *gdbarch,
3739 int regnum, struct type *type)
3740 {
3741 int len = TYPE_LENGTH (type);
3742
3743 /* Values may be spread across multiple registers. Most debugging
3744 formats aren't expressive enough to specify the locations, so
3745 some heuristics is involved. Right now we only handle types that
3746 have a length that is a multiple of the word size, since GCC
3747 doesn't seem to put any other types into registers. */
3748 if (len > 4 && len % 4 == 0)
3749 {
3750 int last_regnum = regnum;
3751
3752 while (len > 4)
3753 {
3754 last_regnum = i386_next_regnum (last_regnum);
3755 len -= 4;
3756 }
3757
3758 if (last_regnum != -1)
3759 return 1;
3760 }
3761
3762 return i387_convert_register_p (gdbarch, regnum, type);
3763 }
3764
3765 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
3766 return its contents in TO. */
3767
3768 static int
3769 i386_register_to_value (struct frame_info *frame, int regnum,
3770 struct type *type, gdb_byte *to,
3771 int *optimizedp, int *unavailablep)
3772 {
3773 struct gdbarch *gdbarch = get_frame_arch (frame);
3774 int len = TYPE_LENGTH (type);
3775
3776 if (i386_fp_regnum_p (gdbarch, regnum))
3777 return i387_register_to_value (frame, regnum, type, to,
3778 optimizedp, unavailablep);
3779
3780 /* Read a value spread across multiple registers. */
3781
3782 gdb_assert (len > 4 && len % 4 == 0);
3783
3784 while (len > 0)
3785 {
3786 gdb_assert (regnum != -1);
3787 gdb_assert (register_size (gdbarch, regnum) == 4);
3788
3789 if (!get_frame_register_bytes (frame, regnum, 0,
3790 register_size (gdbarch, regnum),
3791 to, optimizedp, unavailablep))
3792 return 0;
3793
3794 regnum = i386_next_regnum (regnum);
3795 len -= 4;
3796 to += 4;
3797 }
3798
3799 *optimizedp = *unavailablep = 0;
3800 return 1;
3801 }
3802
3803 /* Write the contents FROM of a value of type TYPE into register
3804 REGNUM in frame FRAME. */
3805
3806 static void
3807 i386_value_to_register (struct frame_info *frame, int regnum,
3808 struct type *type, const gdb_byte *from)
3809 {
3810 int len = TYPE_LENGTH (type);
3811
3812 if (i386_fp_regnum_p (get_frame_arch (frame), regnum))
3813 {
3814 i387_value_to_register (frame, regnum, type, from);
3815 return;
3816 }
3817
3818 /* Write a value spread across multiple registers. */
3819
3820 gdb_assert (len > 4 && len % 4 == 0);
3821
3822 while (len > 0)
3823 {
3824 gdb_assert (regnum != -1);
3825 gdb_assert (register_size (get_frame_arch (frame), regnum) == 4);
3826
3827 put_frame_register (frame, regnum, from);
3828 regnum = i386_next_regnum (regnum);
3829 len -= 4;
3830 from += 4;
3831 }
3832 }
3833
3834 /* Supply register REGNUM from the buffer specified by GREGS and LEN
3835 in the general-purpose register set REGSET to register cache
3836 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3837
3838 void
3839 i386_supply_gregset (const struct regset *regset, struct regcache *regcache,
3840 int regnum, const void *gregs, size_t len)
3841 {
3842 struct gdbarch *gdbarch = regcache->arch ();
3843 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3844 const gdb_byte *regs = (const gdb_byte *) gregs;
3845 int i;
3846
3847 gdb_assert (len >= tdep->sizeof_gregset);
3848
3849 for (i = 0; i < tdep->gregset_num_regs; i++)
3850 {
3851 if ((regnum == i || regnum == -1)
3852 && tdep->gregset_reg_offset[i] != -1)
3853 regcache_raw_supply (regcache, i, regs + tdep->gregset_reg_offset[i]);
3854 }
3855 }
3856
3857 /* Collect register REGNUM from the register cache REGCACHE and store
3858 it in the buffer specified by GREGS and LEN as described by the
3859 general-purpose register set REGSET. If REGNUM is -1, do this for
3860 all registers in REGSET. */
3861
3862 static void
3863 i386_collect_gregset (const struct regset *regset,
3864 const struct regcache *regcache,
3865 int regnum, void *gregs, size_t len)
3866 {
3867 struct gdbarch *gdbarch = regcache->arch ();
3868 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3869 gdb_byte *regs = (gdb_byte *) gregs;
3870 int i;
3871
3872 gdb_assert (len >= tdep->sizeof_gregset);
3873
3874 for (i = 0; i < tdep->gregset_num_regs; i++)
3875 {
3876 if ((regnum == i || regnum == -1)
3877 && tdep->gregset_reg_offset[i] != -1)
3878 regcache_raw_collect (regcache, i, regs + tdep->gregset_reg_offset[i]);
3879 }
3880 }
3881
3882 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
3883 in the floating-point register set REGSET to register cache
3884 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3885
3886 static void
3887 i386_supply_fpregset (const struct regset *regset, struct regcache *regcache,
3888 int regnum, const void *fpregs, size_t len)
3889 {
3890 struct gdbarch *gdbarch = regcache->arch ();
3891 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3892
3893 if (len == I387_SIZEOF_FXSAVE)
3894 {
3895 i387_supply_fxsave (regcache, regnum, fpregs);
3896 return;
3897 }
3898
3899 gdb_assert (len >= tdep->sizeof_fpregset);
3900 i387_supply_fsave (regcache, regnum, fpregs);
3901 }
3902
3903 /* Collect register REGNUM from the register cache REGCACHE and store
3904 it in the buffer specified by FPREGS and LEN as described by the
3905 floating-point register set REGSET. If REGNUM is -1, do this for
3906 all registers in REGSET. */
3907
3908 static void
3909 i386_collect_fpregset (const struct regset *regset,
3910 const struct regcache *regcache,
3911 int regnum, void *fpregs, size_t len)
3912 {
3913 struct gdbarch *gdbarch = regcache->arch ();
3914 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3915
3916 if (len == I387_SIZEOF_FXSAVE)
3917 {
3918 i387_collect_fxsave (regcache, regnum, fpregs);
3919 return;
3920 }
3921
3922 gdb_assert (len >= tdep->sizeof_fpregset);
3923 i387_collect_fsave (regcache, regnum, fpregs);
3924 }
3925
3926 /* Register set definitions. */
3927
3928 const struct regset i386_gregset =
3929 {
3930 NULL, i386_supply_gregset, i386_collect_gregset
3931 };
3932
3933 const struct regset i386_fpregset =
3934 {
3935 NULL, i386_supply_fpregset, i386_collect_fpregset
3936 };
3937
3938 /* Default iterator over core file register note sections. */
3939
3940 void
3941 i386_iterate_over_regset_sections (struct gdbarch *gdbarch,
3942 iterate_over_regset_sections_cb *cb,
3943 void *cb_data,
3944 const struct regcache *regcache)
3945 {
3946 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3947
3948 cb (".reg", tdep->sizeof_gregset, &i386_gregset, NULL, cb_data);
3949 if (tdep->sizeof_fpregset)
3950 cb (".reg2", tdep->sizeof_fpregset, tdep->fpregset, NULL, cb_data);
3951 }
3952
3953
3954 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
3955
3956 CORE_ADDR
3957 i386_pe_skip_trampoline_code (struct frame_info *frame,
3958 CORE_ADDR pc, char *name)
3959 {
3960 struct gdbarch *gdbarch = get_frame_arch (frame);
3961 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3962
3963 /* jmp *(dest) */
3964 if (pc && read_memory_unsigned_integer (pc, 2, byte_order) == 0x25ff)
3965 {
3966 unsigned long indirect =
3967 read_memory_unsigned_integer (pc + 2, 4, byte_order);
3968 struct minimal_symbol *indsym =
3969 indirect ? lookup_minimal_symbol_by_pc (indirect).minsym : 0;
3970 const char *symname = indsym ? MSYMBOL_LINKAGE_NAME (indsym) : 0;
3971
3972 if (symname)
3973 {
3974 if (startswith (symname, "__imp_")
3975 || startswith (symname, "_imp_"))
3976 return name ? 1 :
3977 read_memory_unsigned_integer (indirect, 4, byte_order);
3978 }
3979 }
3980 return 0; /* Not a trampoline. */
3981 }
3982
3983
3984 /* Return whether the THIS_FRAME corresponds to a sigtramp
3985 routine. */
3986
3987 int
3988 i386_sigtramp_p (struct frame_info *this_frame)
3989 {
3990 CORE_ADDR pc = get_frame_pc (this_frame);
3991 const char *name;
3992
3993 find_pc_partial_function (pc, &name, NULL, NULL);
3994 return (name && strcmp ("_sigtramp", name) == 0);
3995 }
3996
3997
3998 /* We have two flavours of disassembly. The machinery on this page
3999 deals with switching between those. */
4000
4001 static int
4002 i386_print_insn (bfd_vma pc, struct disassemble_info *info)
4003 {
4004 gdb_assert (disassembly_flavor == att_flavor
4005 || disassembly_flavor == intel_flavor);
4006
4007 info->disassembler_options = disassembly_flavor;
4008
4009 return default_print_insn (pc, info);
4010 }
4011
4012
4013 /* There are a few i386 architecture variants that differ only
4014 slightly from the generic i386 target. For now, we don't give them
4015 their own source file, but include them here. As a consequence,
4016 they'll always be included. */
4017
4018 /* System V Release 4 (SVR4). */
4019
4020 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
4021 routine. */
4022
4023 static int
4024 i386_svr4_sigtramp_p (struct frame_info *this_frame)
4025 {
4026 CORE_ADDR pc = get_frame_pc (this_frame);
4027 const char *name;
4028
4029 /* The origin of these symbols is currently unknown. */
4030 find_pc_partial_function (pc, &name, NULL, NULL);
4031 return (name && (strcmp ("_sigreturn", name) == 0
4032 || strcmp ("sigvechandler", name) == 0));
4033 }
4034
4035 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
4036 address of the associated sigcontext (ucontext) structure. */
4037
4038 static CORE_ADDR
4039 i386_svr4_sigcontext_addr (struct frame_info *this_frame)
4040 {
4041 struct gdbarch *gdbarch = get_frame_arch (this_frame);
4042 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4043 gdb_byte buf[4];
4044 CORE_ADDR sp;
4045
4046 get_frame_register (this_frame, I386_ESP_REGNUM, buf);
4047 sp = extract_unsigned_integer (buf, 4, byte_order);
4048
4049 return read_memory_unsigned_integer (sp + 8, 4, byte_order);
4050 }
4051
4052
4053
4054 /* Implementation of `gdbarch_stap_is_single_operand', as defined in
4055 gdbarch.h. */
4056
4057 int
4058 i386_stap_is_single_operand (struct gdbarch *gdbarch, const char *s)
4059 {
4060 return (*s == '$' /* Literal number. */
4061 || (isdigit (*s) && s[1] == '(' && s[2] == '%') /* Displacement. */
4062 || (*s == '(' && s[1] == '%') /* Register indirection. */
4063 || (*s == '%' && isalpha (s[1]))); /* Register access. */
4064 }
4065
4066 /* Helper function for i386_stap_parse_special_token.
4067
4068 This function parses operands of the form `-8+3+1(%rbp)', which
4069 must be interpreted as `*(-8 + 3 - 1 + (void *) $eax)'.
4070
4071 Return 1 if the operand was parsed successfully, zero
4072 otherwise. */
4073
4074 static int
4075 i386_stap_parse_special_token_triplet (struct gdbarch *gdbarch,
4076 struct stap_parse_info *p)
4077 {
4078 const char *s = p->arg;
4079
4080 if (isdigit (*s) || *s == '-' || *s == '+')
4081 {
4082 int got_minus[3];
4083 int i;
4084 long displacements[3];
4085 const char *start;
4086 char *regname;
4087 int len;
4088 struct stoken str;
4089 char *endp;
4090
4091 got_minus[0] = 0;
4092 if (*s == '+')
4093 ++s;
4094 else if (*s == '-')
4095 {
4096 ++s;
4097 got_minus[0] = 1;
4098 }
4099
4100 if (!isdigit ((unsigned char) *s))
4101 return 0;
4102
4103 displacements[0] = strtol (s, &endp, 10);
4104 s = endp;
4105
4106 if (*s != '+' && *s != '-')
4107 {
4108 /* We are not dealing with a triplet. */
4109 return 0;
4110 }
4111
4112 got_minus[1] = 0;
4113 if (*s == '+')
4114 ++s;
4115 else
4116 {
4117 ++s;
4118 got_minus[1] = 1;
4119 }
4120
4121 if (!isdigit ((unsigned char) *s))
4122 return 0;
4123
4124 displacements[1] = strtol (s, &endp, 10);
4125 s = endp;
4126
4127 if (*s != '+' && *s != '-')
4128 {
4129 /* We are not dealing with a triplet. */
4130 return 0;
4131 }
4132
4133 got_minus[2] = 0;
4134 if (*s == '+')
4135 ++s;
4136 else
4137 {
4138 ++s;
4139 got_minus[2] = 1;
4140 }
4141
4142 if (!isdigit ((unsigned char) *s))
4143 return 0;
4144
4145 displacements[2] = strtol (s, &endp, 10);
4146 s = endp;
4147
4148 if (*s != '(' || s[1] != '%')
4149 return 0;
4150
4151 s += 2;
4152 start = s;
4153
4154 while (isalnum (*s))
4155 ++s;
4156
4157 if (*s++ != ')')
4158 return 0;
4159
4160 len = s - start - 1;
4161 regname = (char *) alloca (len + 1);
4162
4163 strncpy (regname, start, len);
4164 regname[len] = '\0';
4165
4166 if (user_reg_map_name_to_regnum (gdbarch, regname, len) == -1)
4167 error (_("Invalid register name `%s' on expression `%s'."),
4168 regname, p->saved_arg);
4169
4170 for (i = 0; i < 3; i++)
4171 {
4172 write_exp_elt_opcode (&p->pstate, OP_LONG);
4173 write_exp_elt_type
4174 (&p->pstate, builtin_type (gdbarch)->builtin_long);
4175 write_exp_elt_longcst (&p->pstate, displacements[i]);
4176 write_exp_elt_opcode (&p->pstate, OP_LONG);
4177 if (got_minus[i])
4178 write_exp_elt_opcode (&p->pstate, UNOP_NEG);
4179 }
4180
4181 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4182 str.ptr = regname;
4183 str.length = len;
4184 write_exp_string (&p->pstate, str);
4185 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4186
4187 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4188 write_exp_elt_type (&p->pstate,
4189 builtin_type (gdbarch)->builtin_data_ptr);
4190 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4191
4192 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4193 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4194 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4195
4196 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4197 write_exp_elt_type (&p->pstate,
4198 lookup_pointer_type (p->arg_type));
4199 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4200
4201 write_exp_elt_opcode (&p->pstate, UNOP_IND);
4202
4203 p->arg = s;
4204
4205 return 1;
4206 }
4207
4208 return 0;
4209 }
4210
4211 /* Helper function for i386_stap_parse_special_token.
4212
4213 This function parses operands of the form `register base +
4214 (register index * size) + offset', as represented in
4215 `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
4216
4217 Return 1 if the operand was parsed successfully, zero
4218 otherwise. */
4219
4220 static int
4221 i386_stap_parse_special_token_three_arg_disp (struct gdbarch *gdbarch,
4222 struct stap_parse_info *p)
4223 {
4224 const char *s = p->arg;
4225
4226 if (isdigit (*s) || *s == '(' || *s == '-' || *s == '+')
4227 {
4228 int offset_minus = 0;
4229 long offset = 0;
4230 int size_minus = 0;
4231 long size = 0;
4232 const char *start;
4233 char *base;
4234 int len_base;
4235 char *index;
4236 int len_index;
4237 struct stoken base_token, index_token;
4238
4239 if (*s == '+')
4240 ++s;
4241 else if (*s == '-')
4242 {
4243 ++s;
4244 offset_minus = 1;
4245 }
4246
4247 if (offset_minus && !isdigit (*s))
4248 return 0;
4249
4250 if (isdigit (*s))
4251 {
4252 char *endp;
4253
4254 offset = strtol (s, &endp, 10);
4255 s = endp;
4256 }
4257
4258 if (*s != '(' || s[1] != '%')
4259 return 0;
4260
4261 s += 2;
4262 start = s;
4263
4264 while (isalnum (*s))
4265 ++s;
4266
4267 if (*s != ',' || s[1] != '%')
4268 return 0;
4269
4270 len_base = s - start;
4271 base = (char *) alloca (len_base + 1);
4272 strncpy (base, start, len_base);
4273 base[len_base] = '\0';
4274
4275 if (user_reg_map_name_to_regnum (gdbarch, base, len_base) == -1)
4276 error (_("Invalid register name `%s' on expression `%s'."),
4277 base, p->saved_arg);
4278
4279 s += 2;
4280 start = s;
4281
4282 while (isalnum (*s))
4283 ++s;
4284
4285 len_index = s - start;
4286 index = (char *) alloca (len_index + 1);
4287 strncpy (index, start, len_index);
4288 index[len_index] = '\0';
4289
4290 if (user_reg_map_name_to_regnum (gdbarch, index, len_index) == -1)
4291 error (_("Invalid register name `%s' on expression `%s'."),
4292 index, p->saved_arg);
4293
4294 if (*s != ',' && *s != ')')
4295 return 0;
4296
4297 if (*s == ',')
4298 {
4299 char *endp;
4300
4301 ++s;
4302 if (*s == '+')
4303 ++s;
4304 else if (*s == '-')
4305 {
4306 ++s;
4307 size_minus = 1;
4308 }
4309
4310 size = strtol (s, &endp, 10);
4311 s = endp;
4312
4313 if (*s != ')')
4314 return 0;
4315 }
4316
4317 ++s;
4318
4319 if (offset)
4320 {
4321 write_exp_elt_opcode (&p->pstate, OP_LONG);
4322 write_exp_elt_type (&p->pstate,
4323 builtin_type (gdbarch)->builtin_long);
4324 write_exp_elt_longcst (&p->pstate, offset);
4325 write_exp_elt_opcode (&p->pstate, OP_LONG);
4326 if (offset_minus)
4327 write_exp_elt_opcode (&p->pstate, UNOP_NEG);
4328 }
4329
4330 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4331 base_token.ptr = base;
4332 base_token.length = len_base;
4333 write_exp_string (&p->pstate, base_token);
4334 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4335
4336 if (offset)
4337 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4338
4339 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4340 index_token.ptr = index;
4341 index_token.length = len_index;
4342 write_exp_string (&p->pstate, index_token);
4343 write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4344
4345 if (size)
4346 {
4347 write_exp_elt_opcode (&p->pstate, OP_LONG);
4348 write_exp_elt_type (&p->pstate,
4349 builtin_type (gdbarch)->builtin_long);
4350 write_exp_elt_longcst (&p->pstate, size);
4351 write_exp_elt_opcode (&p->pstate, OP_LONG);
4352 if (size_minus)
4353 write_exp_elt_opcode (&p->pstate, UNOP_NEG);
4354 write_exp_elt_opcode (&p->pstate, BINOP_MUL);
4355 }
4356
4357 write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4358
4359 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4360 write_exp_elt_type (&p->pstate,
4361 lookup_pointer_type (p->arg_type));
4362 write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4363
4364 write_exp_elt_opcode (&p->pstate, UNOP_IND);
4365
4366 p->arg = s;
4367
4368 return 1;
4369 }
4370
4371 return 0;
4372 }
4373
4374 /* Implementation of `gdbarch_stap_parse_special_token', as defined in
4375 gdbarch.h. */
4376
4377 int
4378 i386_stap_parse_special_token (struct gdbarch *gdbarch,
4379 struct stap_parse_info *p)
4380 {
4381 /* In order to parse special tokens, we use a state-machine that go
4382 through every known token and try to get a match. */
4383 enum
4384 {
4385 TRIPLET,
4386 THREE_ARG_DISPLACEMENT,
4387 DONE
4388 };
4389 int current_state;
4390
4391 current_state = TRIPLET;
4392
4393 /* The special tokens to be parsed here are:
4394
4395 - `register base + (register index * size) + offset', as represented
4396 in `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
4397
4398 - Operands of the form `-8+3+1(%rbp)', which must be interpreted as
4399 `*(-8 + 3 - 1 + (void *) $eax)'. */
4400
4401 while (current_state != DONE)
4402 {
4403 switch (current_state)
4404 {
4405 case TRIPLET:
4406 if (i386_stap_parse_special_token_triplet (gdbarch, p))
4407 return 1;
4408 break;
4409
4410 case THREE_ARG_DISPLACEMENT:
4411 if (i386_stap_parse_special_token_three_arg_disp (gdbarch, p))
4412 return 1;
4413 break;
4414 }
4415
4416 /* Advancing to the next state. */
4417 ++current_state;
4418 }
4419
4420 return 0;
4421 }
4422
4423
4424
4425 /* gdbarch gnu_triplet_regexp method. Both arches are acceptable as GDB always
4426 also supplies -m64 or -m32 by gdbarch_gcc_target_options. */
4427
4428 static const char *
4429 i386_gnu_triplet_regexp (struct gdbarch *gdbarch)
4430 {
4431 return "(x86_64|i.86)";
4432 }
4433
4434
4435
4436 /* Generic ELF. */
4437
4438 void
4439 i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
4440 {
4441 static const char *const stap_integer_prefixes[] = { "$", NULL };
4442 static const char *const stap_register_prefixes[] = { "%", NULL };
4443 static const char *const stap_register_indirection_prefixes[] = { "(",
4444 NULL };
4445 static const char *const stap_register_indirection_suffixes[] = { ")",
4446 NULL };
4447
4448 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
4449 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum);
4450
4451 /* Registering SystemTap handlers. */
4452 set_gdbarch_stap_integer_prefixes (gdbarch, stap_integer_prefixes);
4453 set_gdbarch_stap_register_prefixes (gdbarch, stap_register_prefixes);
4454 set_gdbarch_stap_register_indirection_prefixes (gdbarch,
4455 stap_register_indirection_prefixes);
4456 set_gdbarch_stap_register_indirection_suffixes (gdbarch,
4457 stap_register_indirection_suffixes);
4458 set_gdbarch_stap_is_single_operand (gdbarch,
4459 i386_stap_is_single_operand);
4460 set_gdbarch_stap_parse_special_token (gdbarch,
4461 i386_stap_parse_special_token);
4462 }
4463
4464 /* System V Release 4 (SVR4). */
4465
4466 void
4467 i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
4468 {
4469 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4470
4471 /* System V Release 4 uses ELF. */
4472 i386_elf_init_abi (info, gdbarch);
4473
4474 /* System V Release 4 has shared libraries. */
4475 set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
4476
4477 tdep->sigtramp_p = i386_svr4_sigtramp_p;
4478 tdep->sigcontext_addr = i386_svr4_sigcontext_addr;
4479 tdep->sc_pc_offset = 36 + 14 * 4;
4480 tdep->sc_sp_offset = 36 + 17 * 4;
4481
4482 tdep->jb_pc_offset = 20;
4483 }
4484
4485
4486
4487 /* i386 register groups. In addition to the normal groups, add "mmx"
4488 and "sse". */
4489
4490 static struct reggroup *i386_sse_reggroup;
4491 static struct reggroup *i386_mmx_reggroup;
4492
4493 static void
4494 i386_init_reggroups (void)
4495 {
4496 i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP);
4497 i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP);
4498 }
4499
4500 static void
4501 i386_add_reggroups (struct gdbarch *gdbarch)
4502 {
4503 reggroup_add (gdbarch, i386_sse_reggroup);
4504 reggroup_add (gdbarch, i386_mmx_reggroup);
4505 reggroup_add (gdbarch, general_reggroup);
4506 reggroup_add (gdbarch, float_reggroup);
4507 reggroup_add (gdbarch, all_reggroup);
4508 reggroup_add (gdbarch, save_reggroup);
4509 reggroup_add (gdbarch, restore_reggroup);
4510 reggroup_add (gdbarch, vector_reggroup);
4511 reggroup_add (gdbarch, system_reggroup);
4512 }
4513
4514 int
4515 i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
4516 struct reggroup *group)
4517 {
4518 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4519 int fp_regnum_p, mmx_regnum_p, xmm_regnum_p, mxcsr_regnum_p,
4520 ymm_regnum_p, ymmh_regnum_p, ymm_avx512_regnum_p, ymmh_avx512_regnum_p,
4521 bndr_regnum_p, bnd_regnum_p, zmm_regnum_p, zmmh_regnum_p,
4522 mpx_ctrl_regnum_p, xmm_avx512_regnum_p,
4523 avx512_p, avx_p, sse_p, pkru_regnum_p;
4524
4525 /* Don't include pseudo registers, except for MMX, in any register
4526 groups. */
4527 if (i386_byte_regnum_p (gdbarch, regnum))
4528 return 0;
4529
4530 if (i386_word_regnum_p (gdbarch, regnum))
4531 return 0;
4532
4533 if (i386_dword_regnum_p (gdbarch, regnum))
4534 return 0;
4535
4536 mmx_regnum_p = i386_mmx_regnum_p (gdbarch, regnum);
4537 if (group == i386_mmx_reggroup)
4538 return mmx_regnum_p;
4539
4540 pkru_regnum_p = i386_pkru_regnum_p(gdbarch, regnum);
4541 xmm_regnum_p = i386_xmm_regnum_p (gdbarch, regnum);
4542 xmm_avx512_regnum_p = i386_xmm_avx512_regnum_p (gdbarch, regnum);
4543 mxcsr_regnum_p = i386_mxcsr_regnum_p (gdbarch, regnum);
4544 if (group == i386_sse_reggroup)
4545 return xmm_regnum_p || xmm_avx512_regnum_p || mxcsr_regnum_p;
4546
4547 ymm_regnum_p = i386_ymm_regnum_p (gdbarch, regnum);
4548 ymm_avx512_regnum_p = i386_ymm_avx512_regnum_p (gdbarch, regnum);
4549 zmm_regnum_p = i386_zmm_regnum_p (gdbarch, regnum);
4550
4551 avx512_p = ((tdep->xcr0 & X86_XSTATE_AVX_AVX512_MASK)
4552 == X86_XSTATE_AVX_AVX512_MASK);
4553 avx_p = ((tdep->xcr0 & X86_XSTATE_AVX_AVX512_MASK)
4554 == X86_XSTATE_AVX_MASK) && !avx512_p;
4555 sse_p = ((tdep->xcr0 & X86_XSTATE_AVX_AVX512_MASK)
4556 == X86_XSTATE_SSE_MASK) && !avx512_p && ! avx_p;
4557
4558 if (group == vector_reggroup)
4559 return (mmx_regnum_p
4560 || (zmm_regnum_p && avx512_p)
4561 || ((ymm_regnum_p || ymm_avx512_regnum_p) && avx_p)
4562 || ((xmm_regnum_p || xmm_avx512_regnum_p) && sse_p)
4563 || mxcsr_regnum_p);
4564
4565 fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum)
4566 || i386_fpc_regnum_p (gdbarch, regnum));
4567 if (group == float_reggroup)
4568 return fp_regnum_p;
4569
4570 /* For "info reg all", don't include upper YMM registers nor XMM
4571 registers when AVX is supported. */
4572 ymmh_regnum_p = i386_ymmh_regnum_p (gdbarch, regnum);
4573 ymmh_avx512_regnum_p = i386_ymmh_avx512_regnum_p (gdbarch, regnum);
4574 zmmh_regnum_p = i386_zmmh_regnum_p (gdbarch, regnum);
4575 if (group == all_reggroup
4576 && (((xmm_regnum_p || xmm_avx512_regnum_p) && !sse_p)
4577 || ((ymm_regnum_p || ymm_avx512_regnum_p) && !avx_p)
4578 || ymmh_regnum_p
4579 || ymmh_avx512_regnum_p
4580 || zmmh_regnum_p))
4581 return 0;
4582
4583 bnd_regnum_p = i386_bnd_regnum_p (gdbarch, regnum);
4584 if (group == all_reggroup
4585 && ((bnd_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK))))
4586 return bnd_regnum_p;
4587
4588 bndr_regnum_p = i386_bndr_regnum_p (gdbarch, regnum);
4589 if (group == all_reggroup
4590 && ((bndr_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK))))
4591 return 0;
4592
4593 mpx_ctrl_regnum_p = i386_mpx_ctrl_regnum_p (gdbarch, regnum);
4594 if (group == all_reggroup
4595 && ((mpx_ctrl_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK))))
4596 return mpx_ctrl_regnum_p;
4597
4598 if (group == general_reggroup)
4599 return (!fp_regnum_p
4600 && !mmx_regnum_p
4601 && !mxcsr_regnum_p
4602 && !xmm_regnum_p
4603 && !xmm_avx512_regnum_p
4604 && !ymm_regnum_p
4605 && !ymmh_regnum_p
4606 && !ymm_avx512_regnum_p
4607 && !ymmh_avx512_regnum_p
4608 && !bndr_regnum_p
4609 && !bnd_regnum_p
4610 && !mpx_ctrl_regnum_p
4611 && !zmm_regnum_p
4612 && !zmmh_regnum_p
4613 && !pkru_regnum_p);
4614
4615 return default_register_reggroup_p (gdbarch, regnum, group);
4616 }
4617
4618
4619 /* Get the ARGIth function argument for the current function. */
4620
4621 static CORE_ADDR
4622 i386_fetch_pointer_argument (struct frame_info *frame, int argi,
4623 struct type *type)
4624 {
4625 struct gdbarch *gdbarch = get_frame_arch (frame);
4626 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4627 CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM);
4628 return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4, byte_order);
4629 }
4630
4631 #define PREFIX_REPZ 0x01
4632 #define PREFIX_REPNZ 0x02
4633 #define PREFIX_LOCK 0x04
4634 #define PREFIX_DATA 0x08
4635 #define PREFIX_ADDR 0x10
4636
4637 /* operand size */
4638 enum
4639 {
4640 OT_BYTE = 0,
4641 OT_WORD,
4642 OT_LONG,
4643 OT_QUAD,
4644 OT_DQUAD,
4645 };
4646
4647 /* i386 arith/logic operations */
4648 enum
4649 {
4650 OP_ADDL,
4651 OP_ORL,
4652 OP_ADCL,
4653 OP_SBBL,
4654 OP_ANDL,
4655 OP_SUBL,
4656 OP_XORL,
4657 OP_CMPL,
4658 };
4659
4660 struct i386_record_s
4661 {
4662 struct gdbarch *gdbarch;
4663 struct regcache *regcache;
4664 CORE_ADDR orig_addr;
4665 CORE_ADDR addr;
4666 int aflag;
4667 int dflag;
4668 int override;
4669 uint8_t modrm;
4670 uint8_t mod, reg, rm;
4671 int ot;
4672 uint8_t rex_x;
4673 uint8_t rex_b;
4674 int rip_offset;
4675 int popl_esp_hack;
4676 const int *regmap;
4677 };
4678
4679 /* Parse the "modrm" part of the memory address irp->addr points at.
4680 Returns -1 if something goes wrong, 0 otherwise. */
4681
4682 static int
4683 i386_record_modrm (struct i386_record_s *irp)
4684 {
4685 struct gdbarch *gdbarch = irp->gdbarch;
4686
4687 if (record_read_memory (gdbarch, irp->addr, &irp->modrm, 1))
4688 return -1;
4689
4690 irp->addr++;
4691 irp->mod = (irp->modrm >> 6) & 3;
4692 irp->reg = (irp->modrm >> 3) & 7;
4693 irp->rm = irp->modrm & 7;
4694
4695 return 0;
4696 }
4697
4698 /* Extract the memory address that the current instruction writes to,
4699 and return it in *ADDR. Return -1 if something goes wrong. */
4700
4701 static int
4702 i386_record_lea_modrm_addr (struct i386_record_s *irp, uint64_t *addr)
4703 {
4704 struct gdbarch *gdbarch = irp->gdbarch;
4705 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4706 gdb_byte buf[4];
4707 ULONGEST offset64;
4708
4709 *addr = 0;
4710 if (irp->aflag || irp->regmap[X86_RECORD_R8_REGNUM])
4711 {
4712 /* 32/64 bits */
4713 int havesib = 0;
4714 uint8_t scale = 0;
4715 uint8_t byte;
4716 uint8_t index = 0;
4717 uint8_t base = irp->rm;
4718
4719 if (base == 4)
4720 {
4721 havesib = 1;
4722 if (record_read_memory (gdbarch, irp->addr, &byte, 1))
4723 return -1;
4724 irp->addr++;
4725 scale = (byte >> 6) & 3;
4726 index = ((byte >> 3) & 7) | irp->rex_x;
4727 base = (byte & 7);
4728 }
4729 base |= irp->rex_b;
4730
4731 switch (irp->mod)
4732 {
4733 case 0:
4734 if ((base & 7) == 5)
4735 {
4736 base = 0xff;
4737 if (record_read_memory (gdbarch, irp->addr, buf, 4))
4738 return -1;
4739 irp->addr += 4;
4740 *addr = extract_signed_integer (buf, 4, byte_order);
4741 if (irp->regmap[X86_RECORD_R8_REGNUM] && !havesib)
4742 *addr += irp->addr + irp->rip_offset;
4743 }
4744 break;
4745 case 1:
4746 if (record_read_memory (gdbarch, irp->addr, buf, 1))
4747 return -1;
4748 irp->addr++;
4749 *addr = (int8_t) buf[0];
4750 break;
4751 case 2:
4752 if (record_read_memory (gdbarch, irp->addr, buf, 4))
4753 return -1;
4754 *addr = extract_signed_integer (buf, 4, byte_order);
4755 irp->addr += 4;
4756 break;
4757 }
4758
4759 offset64 = 0;
4760 if (base != 0xff)
4761 {
4762 if (base == 4 && irp->popl_esp_hack)
4763 *addr += irp->popl_esp_hack;
4764 regcache_raw_read_unsigned (irp->regcache, irp->regmap[base],
4765 &offset64);
4766 }
4767 if (irp->aflag == 2)
4768 {
4769 *addr += offset64;
4770 }
4771 else
4772 *addr = (uint32_t) (offset64 + *addr);
4773
4774 if (havesib && (index != 4 || scale != 0))
4775 {
4776 regcache_raw_read_unsigned (irp->regcache, irp->regmap[index],
4777 &offset64);
4778 if (irp->aflag == 2)
4779 *addr += offset64 << scale;
4780 else
4781 *addr = (uint32_t) (*addr + (offset64 << scale));
4782 }
4783
4784 if (!irp->aflag)
4785 {
4786 /* Since we are in 64-bit mode with ADDR32 prefix, zero-extend
4787 address from 32-bit to 64-bit. */
4788 *addr = (uint32_t) *addr;
4789 }
4790 }
4791 else
4792 {
4793 /* 16 bits */
4794 switch (irp->mod)
4795 {
4796 case 0:
4797 if (irp->rm == 6)
4798 {
4799 if (record_read_memory (gdbarch, irp->addr, buf, 2))
4800 return -1;
4801 irp->addr += 2;
4802 *addr = extract_signed_integer (buf, 2, byte_order);
4803 irp->rm = 0;
4804 goto no_rm;
4805 }
4806 break;
4807 case 1:
4808 if (record_read_memory (gdbarch, irp->addr, buf, 1))
4809 return -1;
4810 irp->addr++;
4811 *addr = (int8_t) buf[0];
4812 break;
4813 case 2:
4814 if (record_read_memory (gdbarch, irp->addr, buf, 2))
4815 return -1;
4816 irp->addr += 2;
4817 *addr = extract_signed_integer (buf, 2, byte_order);
4818 break;
4819 }
4820
4821 switch (irp->rm)
4822 {
4823 case 0:
4824 regcache_raw_read_unsigned (irp->regcache,
4825 irp->regmap[X86_RECORD_REBX_REGNUM],
4826 &offset64);
4827 *addr = (uint32_t) (*addr + offset64);
4828 regcache_raw_read_unsigned (irp->regcache,
4829 irp->regmap[X86_RECORD_RESI_REGNUM],
4830 &offset64);
4831 *addr = (uint32_t) (*addr + offset64);
4832 break;
4833 case 1:
4834 regcache_raw_read_unsigned (irp->regcache,
4835 irp->regmap[X86_RECORD_REBX_REGNUM],
4836 &offset64);
4837 *addr = (uint32_t) (*addr + offset64);
4838 regcache_raw_read_unsigned (irp->regcache,
4839 irp->regmap[X86_RECORD_REDI_REGNUM],
4840 &offset64);
4841 *addr = (uint32_t) (*addr + offset64);
4842 break;
4843 case 2:
4844 regcache_raw_read_unsigned (irp->regcache,
4845 irp->regmap[X86_RECORD_REBP_REGNUM],
4846 &offset64);
4847 *addr = (uint32_t) (*addr + offset64);
4848 regcache_raw_read_unsigned (irp->regcache,
4849 irp->regmap[X86_RECORD_RESI_REGNUM],
4850 &offset64);
4851 *addr = (uint32_t) (*addr + offset64);
4852 break;
4853 case 3:
4854 regcache_raw_read_unsigned (irp->regcache,
4855 irp->regmap[X86_RECORD_REBP_REGNUM],
4856 &offset64);
4857 *addr = (uint32_t) (*addr + offset64);
4858 regcache_raw_read_unsigned (irp->regcache,
4859 irp->regmap[X86_RECORD_REDI_REGNUM],
4860 &offset64);
4861 *addr = (uint32_t) (*addr + offset64);
4862 break;
4863 case 4:
4864 regcache_raw_read_unsigned (irp->regcache,
4865 irp->regmap[X86_RECORD_RESI_REGNUM],
4866 &offset64);
4867 *addr = (uint32_t) (*addr + offset64);
4868 break;
4869 case 5:
4870 regcache_raw_read_unsigned (irp->regcache,
4871 irp->regmap[X86_RECORD_REDI_REGNUM],
4872 &offset64);
4873 *addr = (uint32_t) (*addr + offset64);
4874 break;
4875 case 6:
4876 regcache_raw_read_unsigned (irp->regcache,
4877 irp->regmap[X86_RECORD_REBP_REGNUM],
4878 &offset64);
4879 *addr = (uint32_t) (*addr + offset64);
4880 break;
4881 case 7:
4882 regcache_raw_read_unsigned (irp->regcache,
4883 irp->regmap[X86_RECORD_REBX_REGNUM],
4884 &offset64);
4885 *addr = (uint32_t) (*addr + offset64);
4886 break;
4887 }
4888 *addr &= 0xffff;
4889 }
4890
4891 no_rm:
4892 return 0;
4893 }
4894
4895 /* Record the address and contents of the memory that will be changed
4896 by the current instruction. Return -1 if something goes wrong, 0
4897 otherwise. */
4898
4899 static int
4900 i386_record_lea_modrm (struct i386_record_s *irp)
4901 {
4902 struct gdbarch *gdbarch = irp->gdbarch;
4903 uint64_t addr;
4904
4905 if (irp->override >= 0)
4906 {
4907 if (record_full_memory_query)
4908 {
4909 if (yquery (_("\
4910 Process record ignores the memory change of instruction at address %s\n\
4911 because it can't get the value of the segment register.\n\
4912 Do you want to stop the program?"),
4913 paddress (gdbarch, irp->orig_addr)))
4914 return -1;
4915 }
4916
4917 return 0;
4918 }
4919
4920 if (i386_record_lea_modrm_addr (irp, &addr))
4921 return -1;
4922
4923 if (record_full_arch_list_add_mem (addr, 1 << irp->ot))
4924 return -1;
4925
4926 return 0;
4927 }
4928
4929 /* Record the effects of a push operation. Return -1 if something
4930 goes wrong, 0 otherwise. */
4931
4932 static int
4933 i386_record_push (struct i386_record_s *irp, int size)
4934 {
4935 ULONGEST addr;
4936
4937 if (record_full_arch_list_add_reg (irp->regcache,
4938 irp->regmap[X86_RECORD_RESP_REGNUM]))
4939 return -1;
4940 regcache_raw_read_unsigned (irp->regcache,
4941 irp->regmap[X86_RECORD_RESP_REGNUM],
4942 &addr);
4943 if (record_full_arch_list_add_mem ((CORE_ADDR) addr - size, size))
4944 return -1;
4945
4946 return 0;
4947 }
4948
4949
4950 /* Defines contents to record. */
4951 #define I386_SAVE_FPU_REGS 0xfffd
4952 #define I386_SAVE_FPU_ENV 0xfffe
4953 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff
4954
4955 /* Record the values of the floating point registers which will be
4956 changed by the current instruction. Returns -1 if something is
4957 wrong, 0 otherwise. */
4958
4959 static int i386_record_floats (struct gdbarch *gdbarch,
4960 struct i386_record_s *ir,
4961 uint32_t iregnum)
4962 {
4963 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4964 int i;
4965
4966 /* Oza: Because of floating point insn push/pop of fpu stack is going to
4967 happen. Currently we store st0-st7 registers, but we need not store all
4968 registers all the time, in future we use ftag register and record only
4969 those who are not marked as an empty. */
4970
4971 if (I386_SAVE_FPU_REGS == iregnum)
4972 {
4973 for (i = I387_ST0_REGNUM (tdep); i <= I387_ST0_REGNUM (tdep) + 7; i++)
4974 {
4975 if (record_full_arch_list_add_reg (ir->regcache, i))
4976 return -1;
4977 }
4978 }
4979 else if (I386_SAVE_FPU_ENV == iregnum)
4980 {
4981 for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
4982 {
4983 if (record_full_arch_list_add_reg (ir->regcache, i))
4984 return -1;
4985 }
4986 }
4987 else if (I386_SAVE_FPU_ENV_REG_STACK == iregnum)
4988 {
4989 for (i = I387_ST0_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
4990 {
4991 if (record_full_arch_list_add_reg (ir->regcache, i))
4992 return -1;
4993 }
4994 }
4995 else if ((iregnum >= I387_ST0_REGNUM (tdep)) &&
4996 (iregnum <= I387_FOP_REGNUM (tdep)))
4997 {
4998 if (record_full_arch_list_add_reg (ir->regcache,iregnum))
4999 return -1;
5000 }
5001 else
5002 {
5003 /* Parameter error. */
5004 return -1;
5005 }
5006 if(I386_SAVE_FPU_ENV != iregnum)
5007 {
5008 for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
5009 {
5010 if (record_full_arch_list_add_reg (ir->regcache, i))
5011 return -1;
5012 }
5013 }
5014 return 0;
5015 }
5016
5017 /* Parse the current instruction, and record the values of the
5018 registers and memory that will be changed by the current
5019 instruction. Returns -1 if something goes wrong, 0 otherwise. */
5020
5021 #define I386_RECORD_FULL_ARCH_LIST_ADD_REG(regnum) \
5022 record_full_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
5023
5024 int
5025 i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
5026 CORE_ADDR input_addr)
5027 {
5028 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
5029 int prefixes = 0;
5030 int regnum = 0;
5031 uint32_t opcode;
5032 uint8_t opcode8;
5033 ULONGEST addr;
5034 gdb_byte buf[I386_MAX_REGISTER_SIZE];
5035 struct i386_record_s ir;
5036 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
5037 uint8_t rex_w = -1;
5038 uint8_t rex_r = 0;
5039
5040 memset (&ir, 0, sizeof (struct i386_record_s));
5041 ir.regcache = regcache;
5042 ir.addr = input_addr;
5043 ir.orig_addr = input_addr;
5044 ir.aflag = 1;
5045 ir.dflag = 1;
5046 ir.override = -1;
5047 ir.popl_esp_hack = 0;
5048 ir.regmap = tdep->record_regmap;
5049 ir.gdbarch = gdbarch;
5050
5051 if (record_debug > 1)
5052 fprintf_unfiltered (gdb_stdlog, "Process record: i386_process_record "
5053 "addr = %s\n",
5054 paddress (gdbarch, ir.addr));
5055
5056 /* prefixes */
5057 while (1)
5058 {
5059 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
5060 return -1;
5061 ir.addr++;
5062 switch (opcode8) /* Instruction prefixes */
5063 {
5064 case REPE_PREFIX_OPCODE:
5065 prefixes |= PREFIX_REPZ;
5066 break;
5067 case REPNE_PREFIX_OPCODE:
5068 prefixes |= PREFIX_REPNZ;
5069 break;
5070 case LOCK_PREFIX_OPCODE:
5071 prefixes |= PREFIX_LOCK;
5072 break;
5073 case CS_PREFIX_OPCODE:
5074 ir.override = X86_RECORD_CS_REGNUM;
5075 break;
5076 case SS_PREFIX_OPCODE:
5077 ir.override = X86_RECORD_SS_REGNUM;
5078 break;
5079 case DS_PREFIX_OPCODE:
5080 ir.override = X86_RECORD_DS_REGNUM;
5081 break;
5082 case ES_PREFIX_OPCODE:
5083 ir.override = X86_RECORD_ES_REGNUM;
5084 break;
5085 case FS_PREFIX_OPCODE:
5086 ir.override = X86_RECORD_FS_REGNUM;
5087 break;
5088 case GS_PREFIX_OPCODE:
5089 ir.override = X86_RECORD_GS_REGNUM;
5090 break;
5091 case DATA_PREFIX_OPCODE:
5092 prefixes |= PREFIX_DATA;
5093 break;
5094 case ADDR_PREFIX_OPCODE:
5095 prefixes |= PREFIX_ADDR;
5096 break;
5097 case 0x40: /* i386 inc %eax */
5098 case 0x41: /* i386 inc %ecx */
5099 case 0x42: /* i386 inc %edx */
5100 case 0x43: /* i386 inc %ebx */
5101 case 0x44: /* i386 inc %esp */
5102 case 0x45: /* i386 inc %ebp */
5103 case 0x46: /* i386 inc %esi */
5104 case 0x47: /* i386 inc %edi */
5105 case 0x48: /* i386 dec %eax */
5106 case 0x49: /* i386 dec %ecx */
5107 case 0x4a: /* i386 dec %edx */
5108 case 0x4b: /* i386 dec %ebx */
5109 case 0x4c: /* i386 dec %esp */
5110 case 0x4d: /* i386 dec %ebp */
5111 case 0x4e: /* i386 dec %esi */
5112 case 0x4f: /* i386 dec %edi */
5113 if (ir.regmap[X86_RECORD_R8_REGNUM]) /* 64 bit target */
5114 {
5115 /* REX */
5116 rex_w = (opcode8 >> 3) & 1;
5117 rex_r = (opcode8 & 0x4) << 1;
5118 ir.rex_x = (opcode8 & 0x2) << 2;
5119 ir.rex_b = (opcode8 & 0x1) << 3;
5120 }
5121 else /* 32 bit target */
5122 goto out_prefixes;
5123 break;
5124 default:
5125 goto out_prefixes;
5126 break;
5127 }
5128 }
5129 out_prefixes:
5130 if (ir.regmap[X86_RECORD_R8_REGNUM] && rex_w == 1)
5131 {
5132 ir.dflag = 2;
5133 }
5134 else
5135 {
5136 if (prefixes & PREFIX_DATA)
5137 ir.dflag ^= 1;
5138 }
5139 if (prefixes & PREFIX_ADDR)
5140 ir.aflag ^= 1;
5141 else if (ir.regmap[X86_RECORD_R8_REGNUM])
5142 ir.aflag = 2;
5143
5144 /* Now check op code. */
5145 opcode = (uint32_t) opcode8;
5146 reswitch:
5147 switch (opcode)
5148 {
5149 case 0x0f:
5150 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
5151 return -1;
5152 ir.addr++;
5153 opcode = (uint32_t) opcode8 | 0x0f00;
5154 goto reswitch;
5155 break;
5156
5157 case 0x00: /* arith & logic */
5158 case 0x01:
5159 case 0x02:
5160 case 0x03:
5161 case 0x04:
5162 case 0x05:
5163 case 0x08:
5164 case 0x09:
5165 case 0x0a:
5166 case 0x0b:
5167 case 0x0c:
5168 case 0x0d:
5169 case 0x10:
5170 case 0x11:
5171 case 0x12:
5172 case 0x13:
5173 case 0x14:
5174 case 0x15:
5175 case 0x18:
5176 case 0x19:
5177 case 0x1a:
5178 case 0x1b:
5179 case 0x1c:
5180 case 0x1d:
5181 case 0x20:
5182 case 0x21:
5183 case 0x22:
5184 case 0x23:
5185 case 0x24:
5186 case 0x25:
5187 case 0x28:
5188 case 0x29:
5189 case 0x2a:
5190 case 0x2b:
5191 case 0x2c:
5192 case 0x2d:
5193 case 0x30:
5194 case 0x31:
5195 case 0x32:
5196 case 0x33:
5197 case 0x34:
5198 case 0x35:
5199 case 0x38:
5200 case 0x39:
5201 case 0x3a:
5202 case 0x3b:
5203 case 0x3c:
5204 case 0x3d:
5205 if (((opcode >> 3) & 7) != OP_CMPL)
5206 {
5207 if ((opcode & 1) == 0)
5208 ir.ot = OT_BYTE;
5209 else
5210 ir.ot = ir.dflag + OT_WORD;
5211
5212 switch ((opcode >> 1) & 3)
5213 {
5214 case 0: /* OP Ev, Gv */
5215 if (i386_record_modrm (&ir))
5216 return -1;
5217 if (ir.mod != 3)
5218 {
5219 if (i386_record_lea_modrm (&ir))
5220 return -1;
5221 }
5222 else
5223 {
5224 ir.rm |= ir.rex_b;
5225 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5226 ir.rm &= 0x3;
5227 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5228 }
5229 break;
5230 case 1: /* OP Gv, Ev */
5231 if (i386_record_modrm (&ir))
5232 return -1;
5233 ir.reg |= rex_r;
5234 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5235 ir.reg &= 0x3;
5236 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5237 break;
5238 case 2: /* OP A, Iv */
5239 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5240 break;
5241 }
5242 }
5243 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5244 break;
5245
5246 case 0x80: /* GRP1 */
5247 case 0x81:
5248 case 0x82:
5249 case 0x83:
5250 if (i386_record_modrm (&ir))
5251 return -1;
5252
5253 if (ir.reg != OP_CMPL)
5254 {
5255 if ((opcode & 1) == 0)
5256 ir.ot = OT_BYTE;
5257 else
5258 ir.ot = ir.dflag + OT_WORD;
5259
5260 if (ir.mod != 3)
5261 {
5262 if (opcode == 0x83)
5263 ir.rip_offset = 1;
5264 else
5265 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5266 if (i386_record_lea_modrm (&ir))
5267 return -1;
5268 }
5269 else
5270 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
5271 }
5272 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5273 break;
5274
5275 case 0x40: /* inc */
5276 case 0x41:
5277 case 0x42:
5278 case 0x43:
5279 case 0x44:
5280 case 0x45:
5281 case 0x46:
5282 case 0x47:
5283
5284 case 0x48: /* dec */
5285 case 0x49:
5286 case 0x4a:
5287 case 0x4b:
5288 case 0x4c:
5289 case 0x4d:
5290 case 0x4e:
5291 case 0x4f:
5292
5293 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode & 7);
5294 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5295 break;
5296
5297 case 0xf6: /* GRP3 */
5298 case 0xf7:
5299 if ((opcode & 1) == 0)
5300 ir.ot = OT_BYTE;
5301 else
5302 ir.ot = ir.dflag + OT_WORD;
5303 if (i386_record_modrm (&ir))
5304 return -1;
5305
5306 if (ir.mod != 3 && ir.reg == 0)
5307 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5308
5309 switch (ir.reg)
5310 {
5311 case 0: /* test */
5312 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5313 break;
5314 case 2: /* not */
5315 case 3: /* neg */
5316 if (ir.mod != 3)
5317 {
5318 if (i386_record_lea_modrm (&ir))
5319 return -1;
5320 }
5321 else
5322 {
5323 ir.rm |= ir.rex_b;
5324 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5325 ir.rm &= 0x3;
5326 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5327 }
5328 if (ir.reg == 3) /* neg */
5329 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5330 break;
5331 case 4: /* mul */
5332 case 5: /* imul */
5333 case 6: /* div */
5334 case 7: /* idiv */
5335 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5336 if (ir.ot != OT_BYTE)
5337 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5338 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5339 break;
5340 default:
5341 ir.addr -= 2;
5342 opcode = opcode << 8 | ir.modrm;
5343 goto no_support;
5344 break;
5345 }
5346 break;
5347
5348 case 0xfe: /* GRP4 */
5349 case 0xff: /* GRP5 */
5350 if (i386_record_modrm (&ir))
5351 return -1;
5352 if (ir.reg >= 2 && opcode == 0xfe)
5353 {
5354 ir.addr -= 2;
5355 opcode = opcode << 8 | ir.modrm;
5356 goto no_support;
5357 }
5358 switch (ir.reg)
5359 {
5360 case 0: /* inc */
5361 case 1: /* dec */
5362 if ((opcode & 1) == 0)
5363 ir.ot = OT_BYTE;
5364 else
5365 ir.ot = ir.dflag + OT_WORD;
5366 if (ir.mod != 3)
5367 {
5368 if (i386_record_lea_modrm (&ir))
5369 return -1;
5370 }
5371 else
5372 {
5373 ir.rm |= ir.rex_b;
5374 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5375 ir.rm &= 0x3;
5376 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5377 }
5378 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5379 break;
5380 case 2: /* call */
5381 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5382 ir.dflag = 2;
5383 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5384 return -1;
5385 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5386 break;
5387 case 3: /* lcall */
5388 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
5389 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5390 return -1;
5391 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5392 break;
5393 case 4: /* jmp */
5394 case 5: /* ljmp */
5395 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5396 break;
5397 case 6: /* push */
5398 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5399 ir.dflag = 2;
5400 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5401 return -1;
5402 break;
5403 default:
5404 ir.addr -= 2;
5405 opcode = opcode << 8 | ir.modrm;
5406 goto no_support;
5407 break;
5408 }
5409 break;
5410
5411 case 0x84: /* test */
5412 case 0x85:
5413 case 0xa8:
5414 case 0xa9:
5415 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5416 break;
5417
5418 case 0x98: /* CWDE/CBW */
5419 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5420 break;
5421
5422 case 0x99: /* CDQ/CWD */
5423 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5424 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5425 break;
5426
5427 case 0x0faf: /* imul */
5428 case 0x69:
5429 case 0x6b:
5430 ir.ot = ir.dflag + OT_WORD;
5431 if (i386_record_modrm (&ir))
5432 return -1;
5433 if (opcode == 0x69)
5434 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5435 else if (opcode == 0x6b)
5436 ir.rip_offset = 1;
5437 ir.reg |= rex_r;
5438 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5439 ir.reg &= 0x3;
5440 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5441 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5442 break;
5443
5444 case 0x0fc0: /* xadd */
5445 case 0x0fc1:
5446 if ((opcode & 1) == 0)
5447 ir.ot = OT_BYTE;
5448 else
5449 ir.ot = ir.dflag + OT_WORD;
5450 if (i386_record_modrm (&ir))
5451 return -1;
5452 ir.reg |= rex_r;
5453 if (ir.mod == 3)
5454 {
5455 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5456 ir.reg &= 0x3;
5457 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5458 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5459 ir.rm &= 0x3;
5460 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5461 }
5462 else
5463 {
5464 if (i386_record_lea_modrm (&ir))
5465 return -1;
5466 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5467 ir.reg &= 0x3;
5468 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5469 }
5470 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5471 break;
5472
5473 case 0x0fb0: /* cmpxchg */
5474 case 0x0fb1:
5475 if ((opcode & 1) == 0)
5476 ir.ot = OT_BYTE;
5477 else
5478 ir.ot = ir.dflag + OT_WORD;
5479 if (i386_record_modrm (&ir))
5480 return -1;
5481 if (ir.mod == 3)
5482 {
5483 ir.reg |= rex_r;
5484 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5485 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5486 ir.reg &= 0x3;
5487 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5488 }
5489 else
5490 {
5491 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5492 if (i386_record_lea_modrm (&ir))
5493 return -1;
5494 }
5495 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5496 break;
5497
5498 case 0x0fc7: /* cmpxchg8b / rdrand / rdseed */
5499 if (i386_record_modrm (&ir))
5500 return -1;
5501 if (ir.mod == 3)
5502 {
5503 /* rdrand and rdseed use the 3 bits of the REG field of ModR/M as
5504 an extended opcode. rdrand has bits 110 (/6) and rdseed
5505 has bits 111 (/7). */
5506 if (ir.reg == 6 || ir.reg == 7)
5507 {
5508 /* The storage register is described by the 3 R/M bits, but the
5509 REX.B prefix may be used to give access to registers
5510 R8~R15. In this case ir.rex_b + R/M will give us the register
5511 in the range R8~R15.
5512
5513 REX.W may also be used to access 64-bit registers, but we
5514 already record entire registers and not just partial bits
5515 of them. */
5516 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rex_b + ir.rm);
5517 /* These instructions also set conditional bits. */
5518 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5519 break;
5520 }
5521 else
5522 {
5523 /* We don't handle this particular instruction yet. */
5524 ir.addr -= 2;
5525 opcode = opcode << 8 | ir.modrm;
5526 goto no_support;
5527 }
5528 }
5529 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5530 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
5531 if (i386_record_lea_modrm (&ir))
5532 return -1;
5533 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5534 break;
5535
5536 case 0x50: /* push */
5537 case 0x51:
5538 case 0x52:
5539 case 0x53:
5540 case 0x54:
5541 case 0x55:
5542 case 0x56:
5543 case 0x57:
5544 case 0x68:
5545 case 0x6a:
5546 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5547 ir.dflag = 2;
5548 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5549 return -1;
5550 break;
5551
5552 case 0x06: /* push es */
5553 case 0x0e: /* push cs */
5554 case 0x16: /* push ss */
5555 case 0x1e: /* push ds */
5556 if (ir.regmap[X86_RECORD_R8_REGNUM])
5557 {
5558 ir.addr -= 1;
5559 goto no_support;
5560 }
5561 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5562 return -1;
5563 break;
5564
5565 case 0x0fa0: /* push fs */
5566 case 0x0fa8: /* push gs */
5567 if (ir.regmap[X86_RECORD_R8_REGNUM])
5568 {
5569 ir.addr -= 2;
5570 goto no_support;
5571 }
5572 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5573 return -1;
5574 break;
5575
5576 case 0x60: /* pusha */
5577 if (ir.regmap[X86_RECORD_R8_REGNUM])
5578 {
5579 ir.addr -= 1;
5580 goto no_support;
5581 }
5582 if (i386_record_push (&ir, 1 << (ir.dflag + 4)))
5583 return -1;
5584 break;
5585
5586 case 0x58: /* pop */
5587 case 0x59:
5588 case 0x5a:
5589 case 0x5b:
5590 case 0x5c:
5591 case 0x5d:
5592 case 0x5e:
5593 case 0x5f:
5594 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5595 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b);
5596 break;
5597
5598 case 0x61: /* popa */
5599 if (ir.regmap[X86_RECORD_R8_REGNUM])
5600 {
5601 ir.addr -= 1;
5602 goto no_support;
5603 }
5604 for (regnum = X86_RECORD_REAX_REGNUM;
5605 regnum <= X86_RECORD_REDI_REGNUM;
5606 regnum++)
5607 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum);
5608 break;
5609
5610 case 0x8f: /* pop */
5611 if (ir.regmap[X86_RECORD_R8_REGNUM])
5612 ir.ot = ir.dflag ? OT_QUAD : OT_WORD;
5613 else
5614 ir.ot = ir.dflag + OT_WORD;
5615 if (i386_record_modrm (&ir))
5616 return -1;
5617 if (ir.mod == 3)
5618 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
5619 else
5620 {
5621 ir.popl_esp_hack = 1 << ir.ot;
5622 if (i386_record_lea_modrm (&ir))
5623 return -1;
5624 }
5625 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5626 break;
5627
5628 case 0xc8: /* enter */
5629 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
5630 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5631 ir.dflag = 2;
5632 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5633 return -1;
5634 break;
5635
5636 case 0xc9: /* leave */
5637 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5638 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
5639 break;
5640
5641 case 0x07: /* pop es */
5642 if (ir.regmap[X86_RECORD_R8_REGNUM])
5643 {
5644 ir.addr -= 1;
5645 goto no_support;
5646 }
5647 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5648 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM);
5649 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5650 break;
5651
5652 case 0x17: /* pop ss */
5653 if (ir.regmap[X86_RECORD_R8_REGNUM])
5654 {
5655 ir.addr -= 1;
5656 goto no_support;
5657 }
5658 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5659 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM);
5660 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5661 break;
5662
5663 case 0x1f: /* pop ds */
5664 if (ir.regmap[X86_RECORD_R8_REGNUM])
5665 {
5666 ir.addr -= 1;
5667 goto no_support;
5668 }
5669 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5670 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM);
5671 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5672 break;
5673
5674 case 0x0fa1: /* pop fs */
5675 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5676 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM);
5677 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5678 break;
5679
5680 case 0x0fa9: /* pop gs */
5681 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
5682 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM);
5683 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5684 break;
5685
5686 case 0x88: /* mov */
5687 case 0x89:
5688 case 0xc6:
5689 case 0xc7:
5690 if ((opcode & 1) == 0)
5691 ir.ot = OT_BYTE;
5692 else
5693 ir.ot = ir.dflag + OT_WORD;
5694
5695 if (i386_record_modrm (&ir))
5696 return -1;
5697
5698 if (ir.mod != 3)
5699 {
5700 if (opcode == 0xc6 || opcode == 0xc7)
5701 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5702 if (i386_record_lea_modrm (&ir))
5703 return -1;
5704 }
5705 else
5706 {
5707 if (opcode == 0xc6 || opcode == 0xc7)
5708 ir.rm |= ir.rex_b;
5709 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5710 ir.rm &= 0x3;
5711 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5712 }
5713 break;
5714
5715 case 0x8a: /* mov */
5716 case 0x8b:
5717 if ((opcode & 1) == 0)
5718 ir.ot = OT_BYTE;
5719 else
5720 ir.ot = ir.dflag + OT_WORD;
5721 if (i386_record_modrm (&ir))
5722 return -1;
5723 ir.reg |= rex_r;
5724 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5725 ir.reg &= 0x3;
5726 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5727 break;
5728
5729 case 0x8c: /* mov seg */
5730 if (i386_record_modrm (&ir))
5731 return -1;
5732 if (ir.reg > 5)
5733 {
5734 ir.addr -= 2;
5735 opcode = opcode << 8 | ir.modrm;
5736 goto no_support;
5737 }
5738
5739 if (ir.mod == 3)
5740 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5741 else
5742 {
5743 ir.ot = OT_WORD;
5744 if (i386_record_lea_modrm (&ir))
5745 return -1;
5746 }
5747 break;
5748
5749 case 0x8e: /* mov seg */
5750 if (i386_record_modrm (&ir))
5751 return -1;
5752 switch (ir.reg)
5753 {
5754 case 0:
5755 regnum = X86_RECORD_ES_REGNUM;
5756 break;
5757 case 2:
5758 regnum = X86_RECORD_SS_REGNUM;
5759 break;
5760 case 3:
5761 regnum = X86_RECORD_DS_REGNUM;
5762 break;
5763 case 4:
5764 regnum = X86_RECORD_FS_REGNUM;
5765 break;
5766 case 5:
5767 regnum = X86_RECORD_GS_REGNUM;
5768 break;
5769 default:
5770 ir.addr -= 2;
5771 opcode = opcode << 8 | ir.modrm;
5772 goto no_support;
5773 break;
5774 }
5775 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum);
5776 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5777 break;
5778
5779 case 0x0fb6: /* movzbS */
5780 case 0x0fb7: /* movzwS */
5781 case 0x0fbe: /* movsbS */
5782 case 0x0fbf: /* movswS */
5783 if (i386_record_modrm (&ir))
5784 return -1;
5785 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
5786 break;
5787
5788 case 0x8d: /* lea */
5789 if (i386_record_modrm (&ir))
5790 return -1;
5791 if (ir.mod == 3)
5792 {
5793 ir.addr -= 2;
5794 opcode = opcode << 8 | ir.modrm;
5795 goto no_support;
5796 }
5797 ir.ot = ir.dflag;
5798 ir.reg |= rex_r;
5799 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5800 ir.reg &= 0x3;
5801 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5802 break;
5803
5804 case 0xa0: /* mov EAX */
5805 case 0xa1:
5806
5807 case 0xd7: /* xlat */
5808 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5809 break;
5810
5811 case 0xa2: /* mov EAX */
5812 case 0xa3:
5813 if (ir.override >= 0)
5814 {
5815 if (record_full_memory_query)
5816 {
5817 if (yquery (_("\
5818 Process record ignores the memory change of instruction at address %s\n\
5819 because it can't get the value of the segment register.\n\
5820 Do you want to stop the program?"),
5821 paddress (gdbarch, ir.orig_addr)))
5822 return -1;
5823 }
5824 }
5825 else
5826 {
5827 if ((opcode & 1) == 0)
5828 ir.ot = OT_BYTE;
5829 else
5830 ir.ot = ir.dflag + OT_WORD;
5831 if (ir.aflag == 2)
5832 {
5833 if (record_read_memory (gdbarch, ir.addr, buf, 8))
5834 return -1;
5835 ir.addr += 8;
5836 addr = extract_unsigned_integer (buf, 8, byte_order);
5837 }
5838 else if (ir.aflag)
5839 {
5840 if (record_read_memory (gdbarch, ir.addr, buf, 4))
5841 return -1;
5842 ir.addr += 4;
5843 addr = extract_unsigned_integer (buf, 4, byte_order);
5844 }
5845 else
5846 {
5847 if (record_read_memory (gdbarch, ir.addr, buf, 2))
5848 return -1;
5849 ir.addr += 2;
5850 addr = extract_unsigned_integer (buf, 2, byte_order);
5851 }
5852 if (record_full_arch_list_add_mem (addr, 1 << ir.ot))
5853 return -1;
5854 }
5855 break;
5856
5857 case 0xb0: /* mov R, Ib */
5858 case 0xb1:
5859 case 0xb2:
5860 case 0xb3:
5861 case 0xb4:
5862 case 0xb5:
5863 case 0xb6:
5864 case 0xb7:
5865 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((ir.regmap[X86_RECORD_R8_REGNUM])
5866 ? ((opcode & 0x7) | ir.rex_b)
5867 : ((opcode & 0x7) & 0x3));
5868 break;
5869
5870 case 0xb8: /* mov R, Iv */
5871 case 0xb9:
5872 case 0xba:
5873 case 0xbb:
5874 case 0xbc:
5875 case 0xbd:
5876 case 0xbe:
5877 case 0xbf:
5878 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b);
5879 break;
5880
5881 case 0x91: /* xchg R, EAX */
5882 case 0x92:
5883 case 0x93:
5884 case 0x94:
5885 case 0x95:
5886 case 0x96:
5887 case 0x97:
5888 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
5889 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode & 0x7);
5890 break;
5891
5892 case 0x86: /* xchg Ev, Gv */
5893 case 0x87:
5894 if ((opcode & 1) == 0)
5895 ir.ot = OT_BYTE;
5896 else
5897 ir.ot = ir.dflag + OT_WORD;
5898 if (i386_record_modrm (&ir))
5899 return -1;
5900 if (ir.mod == 3)
5901 {
5902 ir.rm |= ir.rex_b;
5903 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5904 ir.rm &= 0x3;
5905 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5906 }
5907 else
5908 {
5909 if (i386_record_lea_modrm (&ir))
5910 return -1;
5911 }
5912 ir.reg |= rex_r;
5913 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5914 ir.reg &= 0x3;
5915 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
5916 break;
5917
5918 case 0xc4: /* les Gv */
5919 case 0xc5: /* lds Gv */
5920 if (ir.regmap[X86_RECORD_R8_REGNUM])
5921 {
5922 ir.addr -= 1;
5923 goto no_support;
5924 }
5925 /* FALLTHROUGH */
5926 case 0x0fb2: /* lss Gv */
5927 case 0x0fb4: /* lfs Gv */
5928 case 0x0fb5: /* lgs Gv */
5929 if (i386_record_modrm (&ir))
5930 return -1;
5931 if (ir.mod == 3)
5932 {
5933 if (opcode > 0xff)
5934 ir.addr -= 3;
5935 else
5936 ir.addr -= 2;
5937 opcode = opcode << 8 | ir.modrm;
5938 goto no_support;
5939 }
5940 switch (opcode)
5941 {
5942 case 0xc4: /* les Gv */
5943 regnum = X86_RECORD_ES_REGNUM;
5944 break;
5945 case 0xc5: /* lds Gv */
5946 regnum = X86_RECORD_DS_REGNUM;
5947 break;
5948 case 0x0fb2: /* lss Gv */
5949 regnum = X86_RECORD_SS_REGNUM;
5950 break;
5951 case 0x0fb4: /* lfs Gv */
5952 regnum = X86_RECORD_FS_REGNUM;
5953 break;
5954 case 0x0fb5: /* lgs Gv */
5955 regnum = X86_RECORD_GS_REGNUM;
5956 break;
5957 }
5958 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum);
5959 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
5960 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5961 break;
5962
5963 case 0xc0: /* shifts */
5964 case 0xc1:
5965 case 0xd0:
5966 case 0xd1:
5967 case 0xd2:
5968 case 0xd3:
5969 if ((opcode & 1) == 0)
5970 ir.ot = OT_BYTE;
5971 else
5972 ir.ot = ir.dflag + OT_WORD;
5973 if (i386_record_modrm (&ir))
5974 return -1;
5975 if (ir.mod != 3 && (opcode == 0xd2 || opcode == 0xd3))
5976 {
5977 if (i386_record_lea_modrm (&ir))
5978 return -1;
5979 }
5980 else
5981 {
5982 ir.rm |= ir.rex_b;
5983 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5984 ir.rm &= 0x3;
5985 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm);
5986 }
5987 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
5988 break;
5989
5990 case 0x0fa4:
5991 case 0x0fa5:
5992 case 0x0fac:
5993 case 0x0fad:
5994 if (i386_record_modrm (&ir))
5995 return -1;
5996 if (ir.mod == 3)
5997 {
5998 if (record_full_arch_list_add_reg (ir.regcache, ir.rm))
5999 return -1;
6000 }
6001 else
6002 {
6003 if (i386_record_lea_modrm (&ir))
6004 return -1;
6005 }
6006 break;
6007
6008 case 0xd8: /* Floats. */
6009 case 0xd9:
6010 case 0xda:
6011 case 0xdb:
6012 case 0xdc:
6013 case 0xdd:
6014 case 0xde:
6015 case 0xdf:
6016 if (i386_record_modrm (&ir))
6017 return -1;
6018 ir.reg |= ((opcode & 7) << 3);
6019 if (ir.mod != 3)
6020 {
6021 /* Memory. */
6022 uint64_t addr64;
6023
6024 if (i386_record_lea_modrm_addr (&ir, &addr64))
6025 return -1;
6026 switch (ir.reg)
6027 {
6028 case 0x02:
6029 case 0x12:
6030 case 0x22:
6031 case 0x32:
6032 /* For fcom, ficom nothing to do. */
6033 break;
6034 case 0x03:
6035 case 0x13:
6036 case 0x23:
6037 case 0x33:
6038 /* For fcomp, ficomp pop FPU stack, store all. */
6039 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6040 return -1;
6041 break;
6042 case 0x00:
6043 case 0x01:
6044 case 0x04:
6045 case 0x05:
6046 case 0x06:
6047 case 0x07:
6048 case 0x10:
6049 case 0x11:
6050 case 0x14:
6051 case 0x15:
6052 case 0x16:
6053 case 0x17:
6054 case 0x20:
6055 case 0x21:
6056 case 0x24:
6057 case 0x25:
6058 case 0x26:
6059 case 0x27:
6060 case 0x30:
6061 case 0x31:
6062 case 0x34:
6063 case 0x35:
6064 case 0x36:
6065 case 0x37:
6066 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
6067 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
6068 of code, always affects st(0) register. */
6069 if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep)))
6070 return -1;
6071 break;
6072 case 0x08:
6073 case 0x0a:
6074 case 0x0b:
6075 case 0x18:
6076 case 0x19:
6077 case 0x1a:
6078 case 0x1b:
6079 case 0x1d:
6080 case 0x28:
6081 case 0x29:
6082 case 0x2a:
6083 case 0x2b:
6084 case 0x38:
6085 case 0x39:
6086 case 0x3a:
6087 case 0x3b:
6088 case 0x3c:
6089 case 0x3d:
6090 switch (ir.reg & 7)
6091 {
6092 case 0:
6093 /* Handling fld, fild. */
6094 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6095 return -1;
6096 break;
6097 case 1:
6098 switch (ir.reg >> 4)
6099 {
6100 case 0:
6101 if (record_full_arch_list_add_mem (addr64, 4))
6102 return -1;
6103 break;
6104 case 2:
6105 if (record_full_arch_list_add_mem (addr64, 8))
6106 return -1;
6107 break;
6108 case 3:
6109 break;
6110 default:
6111 if (record_full_arch_list_add_mem (addr64, 2))
6112 return -1;
6113 break;
6114 }
6115 break;
6116 default:
6117 switch (ir.reg >> 4)
6118 {
6119 case 0:
6120 if (record_full_arch_list_add_mem (addr64, 4))
6121 return -1;
6122 if (3 == (ir.reg & 7))
6123 {
6124 /* For fstp m32fp. */
6125 if (i386_record_floats (gdbarch, &ir,
6126 I386_SAVE_FPU_REGS))
6127 return -1;
6128 }
6129 break;
6130 case 1:
6131 if (record_full_arch_list_add_mem (addr64, 4))
6132 return -1;
6133 if ((3 == (ir.reg & 7))
6134 || (5 == (ir.reg & 7))
6135 || (7 == (ir.reg & 7)))
6136 {
6137 /* For fstp insn. */
6138 if (i386_record_floats (gdbarch, &ir,
6139 I386_SAVE_FPU_REGS))
6140 return -1;
6141 }
6142 break;
6143 case 2:
6144 if (record_full_arch_list_add_mem (addr64, 8))
6145 return -1;
6146 if (3 == (ir.reg & 7))
6147 {
6148 /* For fstp m64fp. */
6149 if (i386_record_floats (gdbarch, &ir,
6150 I386_SAVE_FPU_REGS))
6151 return -1;
6152 }
6153 break;
6154 case 3:
6155 if ((3 <= (ir.reg & 7)) && (6 <= (ir.reg & 7)))
6156 {
6157 /* For fistp, fbld, fild, fbstp. */
6158 if (i386_record_floats (gdbarch, &ir,
6159 I386_SAVE_FPU_REGS))
6160 return -1;
6161 }
6162 /* Fall through */
6163 default:
6164 if (record_full_arch_list_add_mem (addr64, 2))
6165 return -1;
6166 break;
6167 }
6168 break;
6169 }
6170 break;
6171 case 0x0c:
6172 /* Insn fldenv. */
6173 if (i386_record_floats (gdbarch, &ir,
6174 I386_SAVE_FPU_ENV_REG_STACK))
6175 return -1;
6176 break;
6177 case 0x0d:
6178 /* Insn fldcw. */
6179 if (i386_record_floats (gdbarch, &ir, I387_FCTRL_REGNUM (tdep)))
6180 return -1;
6181 break;
6182 case 0x2c:
6183 /* Insn frstor. */
6184 if (i386_record_floats (gdbarch, &ir,
6185 I386_SAVE_FPU_ENV_REG_STACK))
6186 return -1;
6187 break;
6188 case 0x0e:
6189 if (ir.dflag)
6190 {
6191 if (record_full_arch_list_add_mem (addr64, 28))
6192 return -1;
6193 }
6194 else
6195 {
6196 if (record_full_arch_list_add_mem (addr64, 14))
6197 return -1;
6198 }
6199 break;
6200 case 0x0f:
6201 case 0x2f:
6202 if (record_full_arch_list_add_mem (addr64, 2))
6203 return -1;
6204 /* Insn fstp, fbstp. */
6205 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6206 return -1;
6207 break;
6208 case 0x1f:
6209 case 0x3e:
6210 if (record_full_arch_list_add_mem (addr64, 10))
6211 return -1;
6212 break;
6213 case 0x2e:
6214 if (ir.dflag)
6215 {
6216 if (record_full_arch_list_add_mem (addr64, 28))
6217 return -1;
6218 addr64 += 28;
6219 }
6220 else
6221 {
6222 if (record_full_arch_list_add_mem (addr64, 14))
6223 return -1;
6224 addr64 += 14;
6225 }
6226 if (record_full_arch_list_add_mem (addr64, 80))
6227 return -1;
6228 /* Insn fsave. */
6229 if (i386_record_floats (gdbarch, &ir,
6230 I386_SAVE_FPU_ENV_REG_STACK))
6231 return -1;
6232 break;
6233 case 0x3f:
6234 if (record_full_arch_list_add_mem (addr64, 8))
6235 return -1;
6236 /* Insn fistp. */
6237 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6238 return -1;
6239 break;
6240 default:
6241 ir.addr -= 2;
6242 opcode = opcode << 8 | ir.modrm;
6243 goto no_support;
6244 break;
6245 }
6246 }
6247 /* Opcode is an extension of modR/M byte. */
6248 else
6249 {
6250 switch (opcode)
6251 {
6252 case 0xd8:
6253 if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep)))
6254 return -1;
6255 break;
6256 case 0xd9:
6257 if (0x0c == (ir.modrm >> 4))
6258 {
6259 if ((ir.modrm & 0x0f) <= 7)
6260 {
6261 if (i386_record_floats (gdbarch, &ir,
6262 I386_SAVE_FPU_REGS))
6263 return -1;
6264 }
6265 else
6266 {
6267 if (i386_record_floats (gdbarch, &ir,
6268 I387_ST0_REGNUM (tdep)))
6269 return -1;
6270 /* If only st(0) is changing, then we have already
6271 recorded. */
6272 if ((ir.modrm & 0x0f) - 0x08)
6273 {
6274 if (i386_record_floats (gdbarch, &ir,
6275 I387_ST0_REGNUM (tdep) +
6276 ((ir.modrm & 0x0f) - 0x08)))
6277 return -1;
6278 }
6279 }
6280 }
6281 else
6282 {
6283 switch (ir.modrm)
6284 {
6285 case 0xe0:
6286 case 0xe1:
6287 case 0xf0:
6288 case 0xf5:
6289 case 0xf8:
6290 case 0xfa:
6291 case 0xfc:
6292 case 0xfe:
6293 case 0xff:
6294 if (i386_record_floats (gdbarch, &ir,
6295 I387_ST0_REGNUM (tdep)))
6296 return -1;
6297 break;
6298 case 0xf1:
6299 case 0xf2:
6300 case 0xf3:
6301 case 0xf4:
6302 case 0xf6:
6303 case 0xf7:
6304 case 0xe8:
6305 case 0xe9:
6306 case 0xea:
6307 case 0xeb:
6308 case 0xec:
6309 case 0xed:
6310 case 0xee:
6311 case 0xf9:
6312 case 0xfb:
6313 if (i386_record_floats (gdbarch, &ir,
6314 I386_SAVE_FPU_REGS))
6315 return -1;
6316 break;
6317 case 0xfd:
6318 if (i386_record_floats (gdbarch, &ir,
6319 I387_ST0_REGNUM (tdep)))
6320 return -1;
6321 if (i386_record_floats (gdbarch, &ir,
6322 I387_ST0_REGNUM (tdep) + 1))
6323 return -1;
6324 break;
6325 }
6326 }
6327 break;
6328 case 0xda:
6329 if (0xe9 == ir.modrm)
6330 {
6331 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6332 return -1;
6333 }
6334 else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4))
6335 {
6336 if (i386_record_floats (gdbarch, &ir,
6337 I387_ST0_REGNUM (tdep)))
6338 return -1;
6339 if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7))
6340 {
6341 if (i386_record_floats (gdbarch, &ir,
6342 I387_ST0_REGNUM (tdep) +
6343 (ir.modrm & 0x0f)))
6344 return -1;
6345 }
6346 else if ((ir.modrm & 0x0f) - 0x08)
6347 {
6348 if (i386_record_floats (gdbarch, &ir,
6349 I387_ST0_REGNUM (tdep) +
6350 ((ir.modrm & 0x0f) - 0x08)))
6351 return -1;
6352 }
6353 }
6354 break;
6355 case 0xdb:
6356 if (0xe3 == ir.modrm)
6357 {
6358 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_ENV))
6359 return -1;
6360 }
6361 else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4))
6362 {
6363 if (i386_record_floats (gdbarch, &ir,
6364 I387_ST0_REGNUM (tdep)))
6365 return -1;
6366 if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7))
6367 {
6368 if (i386_record_floats (gdbarch, &ir,
6369 I387_ST0_REGNUM (tdep) +
6370 (ir.modrm & 0x0f)))
6371 return -1;
6372 }
6373 else if ((ir.modrm & 0x0f) - 0x08)
6374 {
6375 if (i386_record_floats (gdbarch, &ir,
6376 I387_ST0_REGNUM (tdep) +
6377 ((ir.modrm & 0x0f) - 0x08)))
6378 return -1;
6379 }
6380 }
6381 break;
6382 case 0xdc:
6383 if ((0x0c == ir.modrm >> 4)
6384 || (0x0d == ir.modrm >> 4)
6385 || (0x0f == ir.modrm >> 4))
6386 {
6387 if ((ir.modrm & 0x0f) <= 7)
6388 {
6389 if (i386_record_floats (gdbarch, &ir,
6390 I387_ST0_REGNUM (tdep) +
6391 (ir.modrm & 0x0f)))
6392 return -1;
6393 }
6394 else
6395 {
6396 if (i386_record_floats (gdbarch, &ir,
6397 I387_ST0_REGNUM (tdep) +
6398 ((ir.modrm & 0x0f) - 0x08)))
6399 return -1;
6400 }
6401 }
6402 break;
6403 case 0xdd:
6404 if (0x0c == ir.modrm >> 4)
6405 {
6406 if (i386_record_floats (gdbarch, &ir,
6407 I387_FTAG_REGNUM (tdep)))
6408 return -1;
6409 }
6410 else if ((0x0d == ir.modrm >> 4) || (0x0e == ir.modrm >> 4))
6411 {
6412 if ((ir.modrm & 0x0f) <= 7)
6413 {
6414 if (i386_record_floats (gdbarch, &ir,
6415 I387_ST0_REGNUM (tdep) +
6416 (ir.modrm & 0x0f)))
6417 return -1;
6418 }
6419 else
6420 {
6421 if (i386_record_floats (gdbarch, &ir,
6422 I386_SAVE_FPU_REGS))
6423 return -1;
6424 }
6425 }
6426 break;
6427 case 0xde:
6428 if ((0x0c == ir.modrm >> 4)
6429 || (0x0e == ir.modrm >> 4)
6430 || (0x0f == ir.modrm >> 4)
6431 || (0xd9 == ir.modrm))
6432 {
6433 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6434 return -1;
6435 }
6436 break;
6437 case 0xdf:
6438 if (0xe0 == ir.modrm)
6439 {
6440 if (record_full_arch_list_add_reg (ir.regcache,
6441 I386_EAX_REGNUM))
6442 return -1;
6443 }
6444 else if ((0x0f == ir.modrm >> 4) || (0x0e == ir.modrm >> 4))
6445 {
6446 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6447 return -1;
6448 }
6449 break;
6450 }
6451 }
6452 break;
6453 /* string ops */
6454 case 0xa4: /* movsS */
6455 case 0xa5:
6456 case 0xaa: /* stosS */
6457 case 0xab:
6458 case 0x6c: /* insS */
6459 case 0x6d:
6460 regcache_raw_read_unsigned (ir.regcache,
6461 ir.regmap[X86_RECORD_RECX_REGNUM],
6462 &addr);
6463 if (addr)
6464 {
6465 ULONGEST es, ds;
6466
6467 if ((opcode & 1) == 0)
6468 ir.ot = OT_BYTE;
6469 else
6470 ir.ot = ir.dflag + OT_WORD;
6471 regcache_raw_read_unsigned (ir.regcache,
6472 ir.regmap[X86_RECORD_REDI_REGNUM],
6473 &addr);
6474
6475 regcache_raw_read_unsigned (ir.regcache,
6476 ir.regmap[X86_RECORD_ES_REGNUM],
6477 &es);
6478 regcache_raw_read_unsigned (ir.regcache,
6479 ir.regmap[X86_RECORD_DS_REGNUM],
6480 &ds);
6481 if (ir.aflag && (es != ds))
6482 {
6483 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
6484 if (record_full_memory_query)
6485 {
6486 if (yquery (_("\
6487 Process record ignores the memory change of instruction at address %s\n\
6488 because it can't get the value of the segment register.\n\
6489 Do you want to stop the program?"),
6490 paddress (gdbarch, ir.orig_addr)))
6491 return -1;
6492 }
6493 }
6494 else
6495 {
6496 if (record_full_arch_list_add_mem (addr, 1 << ir.ot))
6497 return -1;
6498 }
6499
6500 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6501 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6502 if (opcode == 0xa4 || opcode == 0xa5)
6503 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6504 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
6505 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6506 }
6507 break;
6508
6509 case 0xa6: /* cmpsS */
6510 case 0xa7:
6511 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
6512 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6513 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6514 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6515 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6516 break;
6517
6518 case 0xac: /* lodsS */
6519 case 0xad:
6520 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6521 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6522 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6523 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6524 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6525 break;
6526
6527 case 0xae: /* scasS */
6528 case 0xaf:
6529 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
6530 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6531 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6532 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6533 break;
6534
6535 case 0x6e: /* outsS */
6536 case 0x6f:
6537 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
6538 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6539 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6540 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6541 break;
6542
6543 case 0xe4: /* port I/O */
6544 case 0xe5:
6545 case 0xec:
6546 case 0xed:
6547 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6548 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6549 break;
6550
6551 case 0xe6:
6552 case 0xe7:
6553 case 0xee:
6554 case 0xef:
6555 break;
6556
6557 /* control */
6558 case 0xc2: /* ret im */
6559 case 0xc3: /* ret */
6560 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
6561 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6562 break;
6563
6564 case 0xca: /* lret im */
6565 case 0xcb: /* lret */
6566 case 0xcf: /* iret */
6567 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
6568 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
6569 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6570 break;
6571
6572 case 0xe8: /* call im */
6573 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
6574 ir.dflag = 2;
6575 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
6576 return -1;
6577 break;
6578
6579 case 0x9a: /* lcall im */
6580 if (ir.regmap[X86_RECORD_R8_REGNUM])
6581 {
6582 ir.addr -= 1;
6583 goto no_support;
6584 }
6585 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM);
6586 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
6587 return -1;
6588 break;
6589
6590 case 0xe9: /* jmp im */
6591 case 0xea: /* ljmp im */
6592 case 0xeb: /* jmp Jb */
6593 case 0x70: /* jcc Jb */
6594 case 0x71:
6595 case 0x72:
6596 case 0x73:
6597 case 0x74:
6598 case 0x75:
6599 case 0x76:
6600 case 0x77:
6601 case 0x78:
6602 case 0x79:
6603 case 0x7a:
6604 case 0x7b:
6605 case 0x7c:
6606 case 0x7d:
6607 case 0x7e:
6608 case 0x7f:
6609 case 0x0f80: /* jcc Jv */
6610 case 0x0f81:
6611 case 0x0f82:
6612 case 0x0f83:
6613 case 0x0f84:
6614 case 0x0f85:
6615 case 0x0f86:
6616 case 0x0f87:
6617 case 0x0f88:
6618 case 0x0f89:
6619 case 0x0f8a:
6620 case 0x0f8b:
6621 case 0x0f8c:
6622 case 0x0f8d:
6623 case 0x0f8e:
6624 case 0x0f8f:
6625 break;
6626
6627 case 0x0f90: /* setcc Gv */
6628 case 0x0f91:
6629 case 0x0f92:
6630 case 0x0f93:
6631 case 0x0f94:
6632 case 0x0f95:
6633 case 0x0f96:
6634 case 0x0f97:
6635 case 0x0f98:
6636 case 0x0f99:
6637 case 0x0f9a:
6638 case 0x0f9b:
6639 case 0x0f9c:
6640 case 0x0f9d:
6641 case 0x0f9e:
6642 case 0x0f9f:
6643 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6644 ir.ot = OT_BYTE;
6645 if (i386_record_modrm (&ir))
6646 return -1;
6647 if (ir.mod == 3)
6648 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rex_b ? (ir.rm | ir.rex_b)
6649 : (ir.rm & 0x3));
6650 else
6651 {
6652 if (i386_record_lea_modrm (&ir))
6653 return -1;
6654 }
6655 break;
6656
6657 case 0x0f40: /* cmov Gv, Ev */
6658 case 0x0f41:
6659 case 0x0f42:
6660 case 0x0f43:
6661 case 0x0f44:
6662 case 0x0f45:
6663 case 0x0f46:
6664 case 0x0f47:
6665 case 0x0f48:
6666 case 0x0f49:
6667 case 0x0f4a:
6668 case 0x0f4b:
6669 case 0x0f4c:
6670 case 0x0f4d:
6671 case 0x0f4e:
6672 case 0x0f4f:
6673 if (i386_record_modrm (&ir))
6674 return -1;
6675 ir.reg |= rex_r;
6676 if (ir.dflag == OT_BYTE)
6677 ir.reg &= 0x3;
6678 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
6679 break;
6680
6681 /* flags */
6682 case 0x9c: /* pushf */
6683 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6684 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
6685 ir.dflag = 2;
6686 if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
6687 return -1;
6688 break;
6689
6690 case 0x9d: /* popf */
6691 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
6692 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6693 break;
6694
6695 case 0x9e: /* sahf */
6696 if (ir.regmap[X86_RECORD_R8_REGNUM])
6697 {
6698 ir.addr -= 1;
6699 goto no_support;
6700 }
6701 /* FALLTHROUGH */
6702 case 0xf5: /* cmc */
6703 case 0xf8: /* clc */
6704 case 0xf9: /* stc */
6705 case 0xfc: /* cld */
6706 case 0xfd: /* std */
6707 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6708 break;
6709
6710 case 0x9f: /* lahf */
6711 if (ir.regmap[X86_RECORD_R8_REGNUM])
6712 {
6713 ir.addr -= 1;
6714 goto no_support;
6715 }
6716 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6717 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6718 break;
6719
6720 /* bit operations */
6721 case 0x0fba: /* bt/bts/btr/btc Gv, im */
6722 ir.ot = ir.dflag + OT_WORD;
6723 if (i386_record_modrm (&ir))
6724 return -1;
6725 if (ir.reg < 4)
6726 {
6727 ir.addr -= 2;
6728 opcode = opcode << 8 | ir.modrm;
6729 goto no_support;
6730 }
6731 if (ir.reg != 4)
6732 {
6733 if (ir.mod == 3)
6734 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6735 else
6736 {
6737 if (i386_record_lea_modrm (&ir))
6738 return -1;
6739 }
6740 }
6741 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6742 break;
6743
6744 case 0x0fa3: /* bt Gv, Ev */
6745 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6746 break;
6747
6748 case 0x0fab: /* bts */
6749 case 0x0fb3: /* btr */
6750 case 0x0fbb: /* btc */
6751 ir.ot = ir.dflag + OT_WORD;
6752 if (i386_record_modrm (&ir))
6753 return -1;
6754 if (ir.mod == 3)
6755 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6756 else
6757 {
6758 uint64_t addr64;
6759 if (i386_record_lea_modrm_addr (&ir, &addr64))
6760 return -1;
6761 regcache_raw_read_unsigned (ir.regcache,
6762 ir.regmap[ir.reg | rex_r],
6763 &addr);
6764 switch (ir.dflag)
6765 {
6766 case 0:
6767 addr64 += ((int16_t) addr >> 4) << 4;
6768 break;
6769 case 1:
6770 addr64 += ((int32_t) addr >> 5) << 5;
6771 break;
6772 case 2:
6773 addr64 += ((int64_t) addr >> 6) << 6;
6774 break;
6775 }
6776 if (record_full_arch_list_add_mem (addr64, 1 << ir.ot))
6777 return -1;
6778 if (i386_record_lea_modrm (&ir))
6779 return -1;
6780 }
6781 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6782 break;
6783
6784 case 0x0fbc: /* bsf */
6785 case 0x0fbd: /* bsr */
6786 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
6787 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6788 break;
6789
6790 /* bcd */
6791 case 0x27: /* daa */
6792 case 0x2f: /* das */
6793 case 0x37: /* aaa */
6794 case 0x3f: /* aas */
6795 case 0xd4: /* aam */
6796 case 0xd5: /* aad */
6797 if (ir.regmap[X86_RECORD_R8_REGNUM])
6798 {
6799 ir.addr -= 1;
6800 goto no_support;
6801 }
6802 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6803 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6804 break;
6805
6806 /* misc */
6807 case 0x90: /* nop */
6808 if (prefixes & PREFIX_LOCK)
6809 {
6810 ir.addr -= 1;
6811 goto no_support;
6812 }
6813 break;
6814
6815 case 0x9b: /* fwait */
6816 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
6817 return -1;
6818 opcode = (uint32_t) opcode8;
6819 ir.addr++;
6820 goto reswitch;
6821 break;
6822
6823 /* XXX */
6824 case 0xcc: /* int3 */
6825 printf_unfiltered (_("Process record does not support instruction "
6826 "int3.\n"));
6827 ir.addr -= 1;
6828 goto no_support;
6829 break;
6830
6831 /* XXX */
6832 case 0xcd: /* int */
6833 {
6834 int ret;
6835 uint8_t interrupt;
6836 if (record_read_memory (gdbarch, ir.addr, &interrupt, 1))
6837 return -1;
6838 ir.addr++;
6839 if (interrupt != 0x80
6840 || tdep->i386_intx80_record == NULL)
6841 {
6842 printf_unfiltered (_("Process record does not support "
6843 "instruction int 0x%02x.\n"),
6844 interrupt);
6845 ir.addr -= 2;
6846 goto no_support;
6847 }
6848 ret = tdep->i386_intx80_record (ir.regcache);
6849 if (ret)
6850 return ret;
6851 }
6852 break;
6853
6854 /* XXX */
6855 case 0xce: /* into */
6856 printf_unfiltered (_("Process record does not support "
6857 "instruction into.\n"));
6858 ir.addr -= 1;
6859 goto no_support;
6860 break;
6861
6862 case 0xfa: /* cli */
6863 case 0xfb: /* sti */
6864 break;
6865
6866 case 0x62: /* bound */
6867 printf_unfiltered (_("Process record does not support "
6868 "instruction bound.\n"));
6869 ir.addr -= 1;
6870 goto no_support;
6871 break;
6872
6873 case 0x0fc8: /* bswap reg */
6874 case 0x0fc9:
6875 case 0x0fca:
6876 case 0x0fcb:
6877 case 0x0fcc:
6878 case 0x0fcd:
6879 case 0x0fce:
6880 case 0x0fcf:
6881 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 7) | ir.rex_b);
6882 break;
6883
6884 case 0xd6: /* salc */
6885 if (ir.regmap[X86_RECORD_R8_REGNUM])
6886 {
6887 ir.addr -= 1;
6888 goto no_support;
6889 }
6890 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6891 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6892 break;
6893
6894 case 0xe0: /* loopnz */
6895 case 0xe1: /* loopz */
6896 case 0xe2: /* loop */
6897 case 0xe3: /* jecxz */
6898 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6899 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
6900 break;
6901
6902 case 0x0f30: /* wrmsr */
6903 printf_unfiltered (_("Process record does not support "
6904 "instruction wrmsr.\n"));
6905 ir.addr -= 2;
6906 goto no_support;
6907 break;
6908
6909 case 0x0f32: /* rdmsr */
6910 printf_unfiltered (_("Process record does not support "
6911 "instruction rdmsr.\n"));
6912 ir.addr -= 2;
6913 goto no_support;
6914 break;
6915
6916 case 0x0f31: /* rdtsc */
6917 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6918 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
6919 break;
6920
6921 case 0x0f34: /* sysenter */
6922 {
6923 int ret;
6924 if (ir.regmap[X86_RECORD_R8_REGNUM])
6925 {
6926 ir.addr -= 2;
6927 goto no_support;
6928 }
6929 if (tdep->i386_sysenter_record == NULL)
6930 {
6931 printf_unfiltered (_("Process record does not support "
6932 "instruction sysenter.\n"));
6933 ir.addr -= 2;
6934 goto no_support;
6935 }
6936 ret = tdep->i386_sysenter_record (ir.regcache);
6937 if (ret)
6938 return ret;
6939 }
6940 break;
6941
6942 case 0x0f35: /* sysexit */
6943 printf_unfiltered (_("Process record does not support "
6944 "instruction sysexit.\n"));
6945 ir.addr -= 2;
6946 goto no_support;
6947 break;
6948
6949 case 0x0f05: /* syscall */
6950 {
6951 int ret;
6952 if (tdep->i386_syscall_record == NULL)
6953 {
6954 printf_unfiltered (_("Process record does not support "
6955 "instruction syscall.\n"));
6956 ir.addr -= 2;
6957 goto no_support;
6958 }
6959 ret = tdep->i386_syscall_record (ir.regcache);
6960 if (ret)
6961 return ret;
6962 }
6963 break;
6964
6965 case 0x0f07: /* sysret */
6966 printf_unfiltered (_("Process record does not support "
6967 "instruction sysret.\n"));
6968 ir.addr -= 2;
6969 goto no_support;
6970 break;
6971
6972 case 0x0fa2: /* cpuid */
6973 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
6974 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
6975 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
6976 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM);
6977 break;
6978
6979 case 0xf4: /* hlt */
6980 printf_unfiltered (_("Process record does not support "
6981 "instruction hlt.\n"));
6982 ir.addr -= 1;
6983 goto no_support;
6984 break;
6985
6986 case 0x0f00:
6987 if (i386_record_modrm (&ir))
6988 return -1;
6989 switch (ir.reg)
6990 {
6991 case 0: /* sldt */
6992 case 1: /* str */
6993 if (ir.mod == 3)
6994 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
6995 else
6996 {
6997 ir.ot = OT_WORD;
6998 if (i386_record_lea_modrm (&ir))
6999 return -1;
7000 }
7001 break;
7002 case 2: /* lldt */
7003 case 3: /* ltr */
7004 break;
7005 case 4: /* verr */
7006 case 5: /* verw */
7007 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7008 break;
7009 default:
7010 ir.addr -= 3;
7011 opcode = opcode << 8 | ir.modrm;
7012 goto no_support;
7013 break;
7014 }
7015 break;
7016
7017 case 0x0f01:
7018 if (i386_record_modrm (&ir))
7019 return -1;
7020 switch (ir.reg)
7021 {
7022 case 0: /* sgdt */
7023 {
7024 uint64_t addr64;
7025
7026 if (ir.mod == 3)
7027 {
7028 ir.addr -= 3;
7029 opcode = opcode << 8 | ir.modrm;
7030 goto no_support;
7031 }
7032 if (ir.override >= 0)
7033 {
7034 if (record_full_memory_query)
7035 {
7036 if (yquery (_("\
7037 Process record ignores the memory change of instruction at address %s\n\
7038 because it can't get the value of the segment register.\n\
7039 Do you want to stop the program?"),
7040 paddress (gdbarch, ir.orig_addr)))
7041 return -1;
7042 }
7043 }
7044 else
7045 {
7046 if (i386_record_lea_modrm_addr (&ir, &addr64))
7047 return -1;
7048 if (record_full_arch_list_add_mem (addr64, 2))
7049 return -1;
7050 addr64 += 2;
7051 if (ir.regmap[X86_RECORD_R8_REGNUM])
7052 {
7053 if (record_full_arch_list_add_mem (addr64, 8))
7054 return -1;
7055 }
7056 else
7057 {
7058 if (record_full_arch_list_add_mem (addr64, 4))
7059 return -1;
7060 }
7061 }
7062 }
7063 break;
7064 case 1:
7065 if (ir.mod == 3)
7066 {
7067 switch (ir.rm)
7068 {
7069 case 0: /* monitor */
7070 break;
7071 case 1: /* mwait */
7072 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7073 break;
7074 default:
7075 ir.addr -= 3;
7076 opcode = opcode << 8 | ir.modrm;
7077 goto no_support;
7078 break;
7079 }
7080 }
7081 else
7082 {
7083 /* sidt */
7084 if (ir.override >= 0)
7085 {
7086 if (record_full_memory_query)
7087 {
7088 if (yquery (_("\
7089 Process record ignores the memory change of instruction at address %s\n\
7090 because it can't get the value of the segment register.\n\
7091 Do you want to stop the program?"),
7092 paddress (gdbarch, ir.orig_addr)))
7093 return -1;
7094 }
7095 }
7096 else
7097 {
7098 uint64_t addr64;
7099
7100 if (i386_record_lea_modrm_addr (&ir, &addr64))
7101 return -1;
7102 if (record_full_arch_list_add_mem (addr64, 2))
7103 return -1;
7104 addr64 += 2;
7105 if (ir.regmap[X86_RECORD_R8_REGNUM])
7106 {
7107 if (record_full_arch_list_add_mem (addr64, 8))
7108 return -1;
7109 }
7110 else
7111 {
7112 if (record_full_arch_list_add_mem (addr64, 4))
7113 return -1;
7114 }
7115 }
7116 }
7117 break;
7118 case 2: /* lgdt */
7119 if (ir.mod == 3)
7120 {
7121 /* xgetbv */
7122 if (ir.rm == 0)
7123 {
7124 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
7125 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
7126 break;
7127 }
7128 /* xsetbv */
7129 else if (ir.rm == 1)
7130 break;
7131 }
7132 case 3: /* lidt */
7133 if (ir.mod == 3)
7134 {
7135 ir.addr -= 3;
7136 opcode = opcode << 8 | ir.modrm;
7137 goto no_support;
7138 }
7139 break;
7140 case 4: /* smsw */
7141 if (ir.mod == 3)
7142 {
7143 if (record_full_arch_list_add_reg (ir.regcache, ir.rm | ir.rex_b))
7144 return -1;
7145 }
7146 else
7147 {
7148 ir.ot = OT_WORD;
7149 if (i386_record_lea_modrm (&ir))
7150 return -1;
7151 }
7152 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7153 break;
7154 case 6: /* lmsw */
7155 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7156 break;
7157 case 7: /* invlpg */
7158 if (ir.mod == 3)
7159 {
7160 if (ir.rm == 0 && ir.regmap[X86_RECORD_R8_REGNUM])
7161 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM);
7162 else
7163 {
7164 ir.addr -= 3;
7165 opcode = opcode << 8 | ir.modrm;
7166 goto no_support;
7167 }
7168 }
7169 else
7170 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7171 break;
7172 default:
7173 ir.addr -= 3;
7174 opcode = opcode << 8 | ir.modrm;
7175 goto no_support;
7176 break;
7177 }
7178 break;
7179
7180 case 0x0f08: /* invd */
7181 case 0x0f09: /* wbinvd */
7182 break;
7183
7184 case 0x63: /* arpl */
7185 if (i386_record_modrm (&ir))
7186 return -1;
7187 if (ir.mod == 3 || ir.regmap[X86_RECORD_R8_REGNUM])
7188 {
7189 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.regmap[X86_RECORD_R8_REGNUM]
7190 ? (ir.reg | rex_r) : ir.rm);
7191 }
7192 else
7193 {
7194 ir.ot = ir.dflag ? OT_LONG : OT_WORD;
7195 if (i386_record_lea_modrm (&ir))
7196 return -1;
7197 }
7198 if (!ir.regmap[X86_RECORD_R8_REGNUM])
7199 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7200 break;
7201
7202 case 0x0f02: /* lar */
7203 case 0x0f03: /* lsl */
7204 if (i386_record_modrm (&ir))
7205 return -1;
7206 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
7207 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7208 break;
7209
7210 case 0x0f18:
7211 if (i386_record_modrm (&ir))
7212 return -1;
7213 if (ir.mod == 3 && ir.reg == 3)
7214 {
7215 ir.addr -= 3;
7216 opcode = opcode << 8 | ir.modrm;
7217 goto no_support;
7218 }
7219 break;
7220
7221 case 0x0f19:
7222 case 0x0f1a:
7223 case 0x0f1b:
7224 case 0x0f1c:
7225 case 0x0f1d:
7226 case 0x0f1e:
7227 case 0x0f1f:
7228 /* nop (multi byte) */
7229 break;
7230
7231 case 0x0f20: /* mov reg, crN */
7232 case 0x0f22: /* mov crN, reg */
7233 if (i386_record_modrm (&ir))
7234 return -1;
7235 if ((ir.modrm & 0xc0) != 0xc0)
7236 {
7237 ir.addr -= 3;
7238 opcode = opcode << 8 | ir.modrm;
7239 goto no_support;
7240 }
7241 switch (ir.reg)
7242 {
7243 case 0:
7244 case 2:
7245 case 3:
7246 case 4:
7247 case 8:
7248 if (opcode & 2)
7249 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7250 else
7251 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
7252 break;
7253 default:
7254 ir.addr -= 3;
7255 opcode = opcode << 8 | ir.modrm;
7256 goto no_support;
7257 break;
7258 }
7259 break;
7260
7261 case 0x0f21: /* mov reg, drN */
7262 case 0x0f23: /* mov drN, reg */
7263 if (i386_record_modrm (&ir))
7264 return -1;
7265 if ((ir.modrm & 0xc0) != 0xc0 || ir.reg == 4
7266 || ir.reg == 5 || ir.reg >= 8)
7267 {
7268 ir.addr -= 3;
7269 opcode = opcode << 8 | ir.modrm;
7270 goto no_support;
7271 }
7272 if (opcode & 2)
7273 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7274 else
7275 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
7276 break;
7277
7278 case 0x0f06: /* clts */
7279 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7280 break;
7281
7282 /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */
7283
7284 case 0x0f0d: /* 3DNow! prefetch */
7285 break;
7286
7287 case 0x0f0e: /* 3DNow! femms */
7288 case 0x0f77: /* emms */
7289 if (i386_fpc_regnum_p (gdbarch, I387_FTAG_REGNUM(tdep)))
7290 goto no_support;
7291 record_full_arch_list_add_reg (ir.regcache, I387_FTAG_REGNUM(tdep));
7292 break;
7293
7294 case 0x0f0f: /* 3DNow! data */
7295 if (i386_record_modrm (&ir))
7296 return -1;
7297 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
7298 return -1;
7299 ir.addr++;
7300 switch (opcode8)
7301 {
7302 case 0x0c: /* 3DNow! pi2fw */
7303 case 0x0d: /* 3DNow! pi2fd */
7304 case 0x1c: /* 3DNow! pf2iw */
7305 case 0x1d: /* 3DNow! pf2id */
7306 case 0x8a: /* 3DNow! pfnacc */
7307 case 0x8e: /* 3DNow! pfpnacc */
7308 case 0x90: /* 3DNow! pfcmpge */
7309 case 0x94: /* 3DNow! pfmin */
7310 case 0x96: /* 3DNow! pfrcp */
7311 case 0x97: /* 3DNow! pfrsqrt */
7312 case 0x9a: /* 3DNow! pfsub */
7313 case 0x9e: /* 3DNow! pfadd */
7314 case 0xa0: /* 3DNow! pfcmpgt */
7315 case 0xa4: /* 3DNow! pfmax */
7316 case 0xa6: /* 3DNow! pfrcpit1 */
7317 case 0xa7: /* 3DNow! pfrsqit1 */
7318 case 0xaa: /* 3DNow! pfsubr */
7319 case 0xae: /* 3DNow! pfacc */
7320 case 0xb0: /* 3DNow! pfcmpeq */
7321 case 0xb4: /* 3DNow! pfmul */
7322 case 0xb6: /* 3DNow! pfrcpit2 */
7323 case 0xb7: /* 3DNow! pmulhrw */
7324 case 0xbb: /* 3DNow! pswapd */
7325 case 0xbf: /* 3DNow! pavgusb */
7326 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg))
7327 goto no_support_3dnow_data;
7328 record_full_arch_list_add_reg (ir.regcache, ir.reg);
7329 break;
7330
7331 default:
7332 no_support_3dnow_data:
7333 opcode = (opcode << 8) | opcode8;
7334 goto no_support;
7335 break;
7336 }
7337 break;
7338
7339 case 0x0faa: /* rsm */
7340 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7341 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
7342 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM);
7343 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
7344 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM);
7345 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM);
7346 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM);
7347 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM);
7348 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM);
7349 break;
7350
7351 case 0x0fae:
7352 if (i386_record_modrm (&ir))
7353 return -1;
7354 switch(ir.reg)
7355 {
7356 case 0: /* fxsave */
7357 {
7358 uint64_t tmpu64;
7359
7360 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7361 if (i386_record_lea_modrm_addr (&ir, &tmpu64))
7362 return -1;
7363 if (record_full_arch_list_add_mem (tmpu64, 512))
7364 return -1;
7365 }
7366 break;
7367
7368 case 1: /* fxrstor */
7369 {
7370 int i;
7371
7372 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7373
7374 for (i = I387_MM0_REGNUM (tdep);
7375 i386_mmx_regnum_p (gdbarch, i); i++)
7376 record_full_arch_list_add_reg (ir.regcache, i);
7377
7378 for (i = I387_XMM0_REGNUM (tdep);
7379 i386_xmm_regnum_p (gdbarch, i); i++)
7380 record_full_arch_list_add_reg (ir.regcache, i);
7381
7382 if (i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep)))
7383 record_full_arch_list_add_reg (ir.regcache,
7384 I387_MXCSR_REGNUM(tdep));
7385
7386 for (i = I387_ST0_REGNUM (tdep);
7387 i386_fp_regnum_p (gdbarch, i); i++)
7388 record_full_arch_list_add_reg (ir.regcache, i);
7389
7390 for (i = I387_FCTRL_REGNUM (tdep);
7391 i386_fpc_regnum_p (gdbarch, i); i++)
7392 record_full_arch_list_add_reg (ir.regcache, i);
7393 }
7394 break;
7395
7396 case 2: /* ldmxcsr */
7397 if (!i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep)))
7398 goto no_support;
7399 record_full_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep));
7400 break;
7401
7402 case 3: /* stmxcsr */
7403 ir.ot = OT_LONG;
7404 if (i386_record_lea_modrm (&ir))
7405 return -1;
7406 break;
7407
7408 case 5: /* lfence */
7409 case 6: /* mfence */
7410 case 7: /* sfence clflush */
7411 break;
7412
7413 default:
7414 opcode = (opcode << 8) | ir.modrm;
7415 goto no_support;
7416 break;
7417 }
7418 break;
7419
7420 case 0x0fc3: /* movnti */
7421 ir.ot = (ir.dflag == 2) ? OT_QUAD : OT_LONG;
7422 if (i386_record_modrm (&ir))
7423 return -1;
7424 if (ir.mod == 3)
7425 goto no_support;
7426 ir.reg |= rex_r;
7427 if (i386_record_lea_modrm (&ir))
7428 return -1;
7429 break;
7430
7431 /* Add prefix to opcode. */
7432 case 0x0f10:
7433 case 0x0f11:
7434 case 0x0f12:
7435 case 0x0f13:
7436 case 0x0f14:
7437 case 0x0f15:
7438 case 0x0f16:
7439 case 0x0f17:
7440 case 0x0f28:
7441 case 0x0f29:
7442 case 0x0f2a:
7443 case 0x0f2b:
7444 case 0x0f2c:
7445 case 0x0f2d:
7446 case 0x0f2e:
7447 case 0x0f2f:
7448 case 0x0f38:
7449 case 0x0f39:
7450 case 0x0f3a:
7451 case 0x0f50:
7452 case 0x0f51:
7453 case 0x0f52:
7454 case 0x0f53:
7455 case 0x0f54:
7456 case 0x0f55:
7457 case 0x0f56:
7458 case 0x0f57:
7459 case 0x0f58:
7460 case 0x0f59:
7461 case 0x0f5a:
7462 case 0x0f5b:
7463 case 0x0f5c:
7464 case 0x0f5d:
7465 case 0x0f5e:
7466 case 0x0f5f:
7467 case 0x0f60:
7468 case 0x0f61:
7469 case 0x0f62:
7470 case 0x0f63:
7471 case 0x0f64:
7472 case 0x0f65:
7473 case 0x0f66:
7474 case 0x0f67:
7475 case 0x0f68:
7476 case 0x0f69:
7477 case 0x0f6a:
7478 case 0x0f6b:
7479 case 0x0f6c:
7480 case 0x0f6d:
7481 case 0x0f6e:
7482 case 0x0f6f:
7483 case 0x0f70:
7484 case 0x0f71:
7485 case 0x0f72:
7486 case 0x0f73:
7487 case 0x0f74:
7488 case 0x0f75:
7489 case 0x0f76:
7490 case 0x0f7c:
7491 case 0x0f7d:
7492 case 0x0f7e:
7493 case 0x0f7f:
7494 case 0x0fb8:
7495 case 0x0fc2:
7496 case 0x0fc4:
7497 case 0x0fc5:
7498 case 0x0fc6:
7499 case 0x0fd0:
7500 case 0x0fd1:
7501 case 0x0fd2:
7502 case 0x0fd3:
7503 case 0x0fd4:
7504 case 0x0fd5:
7505 case 0x0fd6:
7506 case 0x0fd7:
7507 case 0x0fd8:
7508 case 0x0fd9:
7509 case 0x0fda:
7510 case 0x0fdb:
7511 case 0x0fdc:
7512 case 0x0fdd:
7513 case 0x0fde:
7514 case 0x0fdf:
7515 case 0x0fe0:
7516 case 0x0fe1:
7517 case 0x0fe2:
7518 case 0x0fe3:
7519 case 0x0fe4:
7520 case 0x0fe5:
7521 case 0x0fe6:
7522 case 0x0fe7:
7523 case 0x0fe8:
7524 case 0x0fe9:
7525 case 0x0fea:
7526 case 0x0feb:
7527 case 0x0fec:
7528 case 0x0fed:
7529 case 0x0fee:
7530 case 0x0fef:
7531 case 0x0ff0:
7532 case 0x0ff1:
7533 case 0x0ff2:
7534 case 0x0ff3:
7535 case 0x0ff4:
7536 case 0x0ff5:
7537 case 0x0ff6:
7538 case 0x0ff7:
7539 case 0x0ff8:
7540 case 0x0ff9:
7541 case 0x0ffa:
7542 case 0x0ffb:
7543 case 0x0ffc:
7544 case 0x0ffd:
7545 case 0x0ffe:
7546 /* Mask out PREFIX_ADDR. */
7547 switch ((prefixes & ~PREFIX_ADDR))
7548 {
7549 case PREFIX_REPNZ:
7550 opcode |= 0xf20000;
7551 break;
7552 case PREFIX_DATA:
7553 opcode |= 0x660000;
7554 break;
7555 case PREFIX_REPZ:
7556 opcode |= 0xf30000;
7557 break;
7558 }
7559 reswitch_prefix_add:
7560 switch (opcode)
7561 {
7562 case 0x0f38:
7563 case 0x660f38:
7564 case 0xf20f38:
7565 case 0x0f3a:
7566 case 0x660f3a:
7567 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
7568 return -1;
7569 ir.addr++;
7570 opcode = (uint32_t) opcode8 | opcode << 8;
7571 goto reswitch_prefix_add;
7572 break;
7573
7574 case 0x0f10: /* movups */
7575 case 0x660f10: /* movupd */
7576 case 0xf30f10: /* movss */
7577 case 0xf20f10: /* movsd */
7578 case 0x0f12: /* movlps */
7579 case 0x660f12: /* movlpd */
7580 case 0xf30f12: /* movsldup */
7581 case 0xf20f12: /* movddup */
7582 case 0x0f14: /* unpcklps */
7583 case 0x660f14: /* unpcklpd */
7584 case 0x0f15: /* unpckhps */
7585 case 0x660f15: /* unpckhpd */
7586 case 0x0f16: /* movhps */
7587 case 0x660f16: /* movhpd */
7588 case 0xf30f16: /* movshdup */
7589 case 0x0f28: /* movaps */
7590 case 0x660f28: /* movapd */
7591 case 0x0f2a: /* cvtpi2ps */
7592 case 0x660f2a: /* cvtpi2pd */
7593 case 0xf30f2a: /* cvtsi2ss */
7594 case 0xf20f2a: /* cvtsi2sd */
7595 case 0x0f2c: /* cvttps2pi */
7596 case 0x660f2c: /* cvttpd2pi */
7597 case 0x0f2d: /* cvtps2pi */
7598 case 0x660f2d: /* cvtpd2pi */
7599 case 0x660f3800: /* pshufb */
7600 case 0x660f3801: /* phaddw */
7601 case 0x660f3802: /* phaddd */
7602 case 0x660f3803: /* phaddsw */
7603 case 0x660f3804: /* pmaddubsw */
7604 case 0x660f3805: /* phsubw */
7605 case 0x660f3806: /* phsubd */
7606 case 0x660f3807: /* phsubsw */
7607 case 0x660f3808: /* psignb */
7608 case 0x660f3809: /* psignw */
7609 case 0x660f380a: /* psignd */
7610 case 0x660f380b: /* pmulhrsw */
7611 case 0x660f3810: /* pblendvb */
7612 case 0x660f3814: /* blendvps */
7613 case 0x660f3815: /* blendvpd */
7614 case 0x660f381c: /* pabsb */
7615 case 0x660f381d: /* pabsw */
7616 case 0x660f381e: /* pabsd */
7617 case 0x660f3820: /* pmovsxbw */
7618 case 0x660f3821: /* pmovsxbd */
7619 case 0x660f3822: /* pmovsxbq */
7620 case 0x660f3823: /* pmovsxwd */
7621 case 0x660f3824: /* pmovsxwq */
7622 case 0x660f3825: /* pmovsxdq */
7623 case 0x660f3828: /* pmuldq */
7624 case 0x660f3829: /* pcmpeqq */
7625 case 0x660f382a: /* movntdqa */
7626 case 0x660f3a08: /* roundps */
7627 case 0x660f3a09: /* roundpd */
7628 case 0x660f3a0a: /* roundss */
7629 case 0x660f3a0b: /* roundsd */
7630 case 0x660f3a0c: /* blendps */
7631 case 0x660f3a0d: /* blendpd */
7632 case 0x660f3a0e: /* pblendw */
7633 case 0x660f3a0f: /* palignr */
7634 case 0x660f3a20: /* pinsrb */
7635 case 0x660f3a21: /* insertps */
7636 case 0x660f3a22: /* pinsrd pinsrq */
7637 case 0x660f3a40: /* dpps */
7638 case 0x660f3a41: /* dppd */
7639 case 0x660f3a42: /* mpsadbw */
7640 case 0x660f3a60: /* pcmpestrm */
7641 case 0x660f3a61: /* pcmpestri */
7642 case 0x660f3a62: /* pcmpistrm */
7643 case 0x660f3a63: /* pcmpistri */
7644 case 0x0f51: /* sqrtps */
7645 case 0x660f51: /* sqrtpd */
7646 case 0xf20f51: /* sqrtsd */
7647 case 0xf30f51: /* sqrtss */
7648 case 0x0f52: /* rsqrtps */
7649 case 0xf30f52: /* rsqrtss */
7650 case 0x0f53: /* rcpps */
7651 case 0xf30f53: /* rcpss */
7652 case 0x0f54: /* andps */
7653 case 0x660f54: /* andpd */
7654 case 0x0f55: /* andnps */
7655 case 0x660f55: /* andnpd */
7656 case 0x0f56: /* orps */
7657 case 0x660f56: /* orpd */
7658 case 0x0f57: /* xorps */
7659 case 0x660f57: /* xorpd */
7660 case 0x0f58: /* addps */
7661 case 0x660f58: /* addpd */
7662 case 0xf20f58: /* addsd */
7663 case 0xf30f58: /* addss */
7664 case 0x0f59: /* mulps */
7665 case 0x660f59: /* mulpd */
7666 case 0xf20f59: /* mulsd */
7667 case 0xf30f59: /* mulss */
7668 case 0x0f5a: /* cvtps2pd */
7669 case 0x660f5a: /* cvtpd2ps */
7670 case 0xf20f5a: /* cvtsd2ss */
7671 case 0xf30f5a: /* cvtss2sd */
7672 case 0x0f5b: /* cvtdq2ps */
7673 case 0x660f5b: /* cvtps2dq */
7674 case 0xf30f5b: /* cvttps2dq */
7675 case 0x0f5c: /* subps */
7676 case 0x660f5c: /* subpd */
7677 case 0xf20f5c: /* subsd */
7678 case 0xf30f5c: /* subss */
7679 case 0x0f5d: /* minps */
7680 case 0x660f5d: /* minpd */
7681 case 0xf20f5d: /* minsd */
7682 case 0xf30f5d: /* minss */
7683 case 0x0f5e: /* divps */
7684 case 0x660f5e: /* divpd */
7685 case 0xf20f5e: /* divsd */
7686 case 0xf30f5e: /* divss */
7687 case 0x0f5f: /* maxps */
7688 case 0x660f5f: /* maxpd */
7689 case 0xf20f5f: /* maxsd */
7690 case 0xf30f5f: /* maxss */
7691 case 0x660f60: /* punpcklbw */
7692 case 0x660f61: /* punpcklwd */
7693 case 0x660f62: /* punpckldq */
7694 case 0x660f63: /* packsswb */
7695 case 0x660f64: /* pcmpgtb */
7696 case 0x660f65: /* pcmpgtw */
7697 case 0x660f66: /* pcmpgtd */
7698 case 0x660f67: /* packuswb */
7699 case 0x660f68: /* punpckhbw */
7700 case 0x660f69: /* punpckhwd */
7701 case 0x660f6a: /* punpckhdq */
7702 case 0x660f6b: /* packssdw */
7703 case 0x660f6c: /* punpcklqdq */
7704 case 0x660f6d: /* punpckhqdq */
7705 case 0x660f6e: /* movd */
7706 case 0x660f6f: /* movdqa */
7707 case 0xf30f6f: /* movdqu */
7708 case 0x660f70: /* pshufd */
7709 case 0xf20f70: /* pshuflw */
7710 case 0xf30f70: /* pshufhw */
7711 case 0x660f74: /* pcmpeqb */
7712 case 0x660f75: /* pcmpeqw */
7713 case 0x660f76: /* pcmpeqd */
7714 case 0x660f7c: /* haddpd */
7715 case 0xf20f7c: /* haddps */
7716 case 0x660f7d: /* hsubpd */
7717 case 0xf20f7d: /* hsubps */
7718 case 0xf30f7e: /* movq */
7719 case 0x0fc2: /* cmpps */
7720 case 0x660fc2: /* cmppd */
7721 case 0xf20fc2: /* cmpsd */
7722 case 0xf30fc2: /* cmpss */
7723 case 0x660fc4: /* pinsrw */
7724 case 0x0fc6: /* shufps */
7725 case 0x660fc6: /* shufpd */
7726 case 0x660fd0: /* addsubpd */
7727 case 0xf20fd0: /* addsubps */
7728 case 0x660fd1: /* psrlw */
7729 case 0x660fd2: /* psrld */
7730 case 0x660fd3: /* psrlq */
7731 case 0x660fd4: /* paddq */
7732 case 0x660fd5: /* pmullw */
7733 case 0xf30fd6: /* movq2dq */
7734 case 0x660fd8: /* psubusb */
7735 case 0x660fd9: /* psubusw */
7736 case 0x660fda: /* pminub */
7737 case 0x660fdb: /* pand */
7738 case 0x660fdc: /* paddusb */
7739 case 0x660fdd: /* paddusw */
7740 case 0x660fde: /* pmaxub */
7741 case 0x660fdf: /* pandn */
7742 case 0x660fe0: /* pavgb */
7743 case 0x660fe1: /* psraw */
7744 case 0x660fe2: /* psrad */
7745 case 0x660fe3: /* pavgw */
7746 case 0x660fe4: /* pmulhuw */
7747 case 0x660fe5: /* pmulhw */
7748 case 0x660fe6: /* cvttpd2dq */
7749 case 0xf20fe6: /* cvtpd2dq */
7750 case 0xf30fe6: /* cvtdq2pd */
7751 case 0x660fe8: /* psubsb */
7752 case 0x660fe9: /* psubsw */
7753 case 0x660fea: /* pminsw */
7754 case 0x660feb: /* por */
7755 case 0x660fec: /* paddsb */
7756 case 0x660fed: /* paddsw */
7757 case 0x660fee: /* pmaxsw */
7758 case 0x660fef: /* pxor */
7759 case 0xf20ff0: /* lddqu */
7760 case 0x660ff1: /* psllw */
7761 case 0x660ff2: /* pslld */
7762 case 0x660ff3: /* psllq */
7763 case 0x660ff4: /* pmuludq */
7764 case 0x660ff5: /* pmaddwd */
7765 case 0x660ff6: /* psadbw */
7766 case 0x660ff8: /* psubb */
7767 case 0x660ff9: /* psubw */
7768 case 0x660ffa: /* psubd */
7769 case 0x660ffb: /* psubq */
7770 case 0x660ffc: /* paddb */
7771 case 0x660ffd: /* paddw */
7772 case 0x660ffe: /* paddd */
7773 if (i386_record_modrm (&ir))
7774 return -1;
7775 ir.reg |= rex_r;
7776 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.reg))
7777 goto no_support;
7778 record_full_arch_list_add_reg (ir.regcache,
7779 I387_XMM0_REGNUM (tdep) + ir.reg);
7780 if ((opcode & 0xfffffffc) == 0x660f3a60)
7781 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
7782 break;
7783
7784 case 0x0f11: /* movups */
7785 case 0x660f11: /* movupd */
7786 case 0xf30f11: /* movss */
7787 case 0xf20f11: /* movsd */
7788 case 0x0f13: /* movlps */
7789 case 0x660f13: /* movlpd */
7790 case 0x0f17: /* movhps */
7791 case 0x660f17: /* movhpd */
7792 case 0x0f29: /* movaps */
7793 case 0x660f29: /* movapd */
7794 case 0x660f3a14: /* pextrb */
7795 case 0x660f3a15: /* pextrw */
7796 case 0x660f3a16: /* pextrd pextrq */
7797 case 0x660f3a17: /* extractps */
7798 case 0x660f7f: /* movdqa */
7799 case 0xf30f7f: /* movdqu */
7800 if (i386_record_modrm (&ir))
7801 return -1;
7802 if (ir.mod == 3)
7803 {
7804 if (opcode == 0x0f13 || opcode == 0x660f13
7805 || opcode == 0x0f17 || opcode == 0x660f17)
7806 goto no_support;
7807 ir.rm |= ir.rex_b;
7808 if (!i386_xmm_regnum_p (gdbarch,
7809 I387_XMM0_REGNUM (tdep) + ir.rm))
7810 goto no_support;
7811 record_full_arch_list_add_reg (ir.regcache,
7812 I387_XMM0_REGNUM (tdep) + ir.rm);
7813 }
7814 else
7815 {
7816 switch (opcode)
7817 {
7818 case 0x660f3a14:
7819 ir.ot = OT_BYTE;
7820 break;
7821 case 0x660f3a15:
7822 ir.ot = OT_WORD;
7823 break;
7824 case 0x660f3a16:
7825 ir.ot = OT_LONG;
7826 break;
7827 case 0x660f3a17:
7828 ir.ot = OT_QUAD;
7829 break;
7830 default:
7831 ir.ot = OT_DQUAD;
7832 break;
7833 }
7834 if (i386_record_lea_modrm (&ir))
7835 return -1;
7836 }
7837 break;
7838
7839 case 0x0f2b: /* movntps */
7840 case 0x660f2b: /* movntpd */
7841 case 0x0fe7: /* movntq */
7842 case 0x660fe7: /* movntdq */
7843 if (ir.mod == 3)
7844 goto no_support;
7845 if (opcode == 0x0fe7)
7846 ir.ot = OT_QUAD;
7847 else
7848 ir.ot = OT_DQUAD;
7849 if (i386_record_lea_modrm (&ir))
7850 return -1;
7851 break;
7852
7853 case 0xf30f2c: /* cvttss2si */
7854 case 0xf20f2c: /* cvttsd2si */
7855 case 0xf30f2d: /* cvtss2si */
7856 case 0xf20f2d: /* cvtsd2si */
7857 case 0xf20f38f0: /* crc32 */
7858 case 0xf20f38f1: /* crc32 */
7859 case 0x0f50: /* movmskps */
7860 case 0x660f50: /* movmskpd */
7861 case 0x0fc5: /* pextrw */
7862 case 0x660fc5: /* pextrw */
7863 case 0x0fd7: /* pmovmskb */
7864 case 0x660fd7: /* pmovmskb */
7865 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r);
7866 break;
7867
7868 case 0x0f3800: /* pshufb */
7869 case 0x0f3801: /* phaddw */
7870 case 0x0f3802: /* phaddd */
7871 case 0x0f3803: /* phaddsw */
7872 case 0x0f3804: /* pmaddubsw */
7873 case 0x0f3805: /* phsubw */
7874 case 0x0f3806: /* phsubd */
7875 case 0x0f3807: /* phsubsw */
7876 case 0x0f3808: /* psignb */
7877 case 0x0f3809: /* psignw */
7878 case 0x0f380a: /* psignd */
7879 case 0x0f380b: /* pmulhrsw */
7880 case 0x0f381c: /* pabsb */
7881 case 0x0f381d: /* pabsw */
7882 case 0x0f381e: /* pabsd */
7883 case 0x0f382b: /* packusdw */
7884 case 0x0f3830: /* pmovzxbw */
7885 case 0x0f3831: /* pmovzxbd */
7886 case 0x0f3832: /* pmovzxbq */
7887 case 0x0f3833: /* pmovzxwd */
7888 case 0x0f3834: /* pmovzxwq */
7889 case 0x0f3835: /* pmovzxdq */
7890 case 0x0f3837: /* pcmpgtq */
7891 case 0x0f3838: /* pminsb */
7892 case 0x0f3839: /* pminsd */
7893 case 0x0f383a: /* pminuw */
7894 case 0x0f383b: /* pminud */
7895 case 0x0f383c: /* pmaxsb */
7896 case 0x0f383d: /* pmaxsd */
7897 case 0x0f383e: /* pmaxuw */
7898 case 0x0f383f: /* pmaxud */
7899 case 0x0f3840: /* pmulld */
7900 case 0x0f3841: /* phminposuw */
7901 case 0x0f3a0f: /* palignr */
7902 case 0x0f60: /* punpcklbw */
7903 case 0x0f61: /* punpcklwd */
7904 case 0x0f62: /* punpckldq */
7905 case 0x0f63: /* packsswb */
7906 case 0x0f64: /* pcmpgtb */
7907 case 0x0f65: /* pcmpgtw */
7908 case 0x0f66: /* pcmpgtd */
7909 case 0x0f67: /* packuswb */
7910 case 0x0f68: /* punpckhbw */
7911 case 0x0f69: /* punpckhwd */
7912 case 0x0f6a: /* punpckhdq */
7913 case 0x0f6b: /* packssdw */
7914 case 0x0f6e: /* movd */
7915 case 0x0f6f: /* movq */
7916 case 0x0f70: /* pshufw */
7917 case 0x0f74: /* pcmpeqb */
7918 case 0x0f75: /* pcmpeqw */
7919 case 0x0f76: /* pcmpeqd */
7920 case 0x0fc4: /* pinsrw */
7921 case 0x0fd1: /* psrlw */
7922 case 0x0fd2: /* psrld */
7923 case 0x0fd3: /* psrlq */
7924 case 0x0fd4: /* paddq */
7925 case 0x0fd5: /* pmullw */
7926 case 0xf20fd6: /* movdq2q */
7927 case 0x0fd8: /* psubusb */
7928 case 0x0fd9: /* psubusw */
7929 case 0x0fda: /* pminub */
7930 case 0x0fdb: /* pand */
7931 case 0x0fdc: /* paddusb */
7932 case 0x0fdd: /* paddusw */
7933 case 0x0fde: /* pmaxub */
7934 case 0x0fdf: /* pandn */
7935 case 0x0fe0: /* pavgb */
7936 case 0x0fe1: /* psraw */
7937 case 0x0fe2: /* psrad */
7938 case 0x0fe3: /* pavgw */
7939 case 0x0fe4: /* pmulhuw */
7940 case 0x0fe5: /* pmulhw */
7941 case 0x0fe8: /* psubsb */
7942 case 0x0fe9: /* psubsw */
7943 case 0x0fea: /* pminsw */
7944 case 0x0feb: /* por */
7945 case 0x0fec: /* paddsb */
7946 case 0x0fed: /* paddsw */
7947 case 0x0fee: /* pmaxsw */
7948 case 0x0fef: /* pxor */
7949 case 0x0ff1: /* psllw */
7950 case 0x0ff2: /* pslld */
7951 case 0x0ff3: /* psllq */
7952 case 0x0ff4: /* pmuludq */
7953 case 0x0ff5: /* pmaddwd */
7954 case 0x0ff6: /* psadbw */
7955 case 0x0ff8: /* psubb */
7956 case 0x0ff9: /* psubw */
7957 case 0x0ffa: /* psubd */
7958 case 0x0ffb: /* psubq */
7959 case 0x0ffc: /* paddb */
7960 case 0x0ffd: /* paddw */
7961 case 0x0ffe: /* paddd */
7962 if (i386_record_modrm (&ir))
7963 return -1;
7964 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg))
7965 goto no_support;
7966 record_full_arch_list_add_reg (ir.regcache,
7967 I387_MM0_REGNUM (tdep) + ir.reg);
7968 break;
7969
7970 case 0x0f71: /* psllw */
7971 case 0x0f72: /* pslld */
7972 case 0x0f73: /* psllq */
7973 if (i386_record_modrm (&ir))
7974 return -1;
7975 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm))
7976 goto no_support;
7977 record_full_arch_list_add_reg (ir.regcache,
7978 I387_MM0_REGNUM (tdep) + ir.rm);
7979 break;
7980
7981 case 0x660f71: /* psllw */
7982 case 0x660f72: /* pslld */
7983 case 0x660f73: /* psllq */
7984 if (i386_record_modrm (&ir))
7985 return -1;
7986 ir.rm |= ir.rex_b;
7987 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm))
7988 goto no_support;
7989 record_full_arch_list_add_reg (ir.regcache,
7990 I387_XMM0_REGNUM (tdep) + ir.rm);
7991 break;
7992
7993 case 0x0f7e: /* movd */
7994 case 0x660f7e: /* movd */
7995 if (i386_record_modrm (&ir))
7996 return -1;
7997 if (ir.mod == 3)
7998 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b);
7999 else
8000 {
8001 if (ir.dflag == 2)
8002 ir.ot = OT_QUAD;
8003 else
8004 ir.ot = OT_LONG;
8005 if (i386_record_lea_modrm (&ir))
8006 return -1;
8007 }
8008 break;
8009
8010 case 0x0f7f: /* movq */
8011 if (i386_record_modrm (&ir))
8012 return -1;
8013 if (ir.mod == 3)
8014 {
8015 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm))
8016 goto no_support;
8017 record_full_arch_list_add_reg (ir.regcache,
8018 I387_MM0_REGNUM (tdep) + ir.rm);
8019 }
8020 else
8021 {
8022 ir.ot = OT_QUAD;
8023 if (i386_record_lea_modrm (&ir))
8024 return -1;
8025 }
8026 break;
8027
8028 case 0xf30fb8: /* popcnt */
8029 if (i386_record_modrm (&ir))
8030 return -1;
8031 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg);
8032 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
8033 break;
8034
8035 case 0x660fd6: /* movq */
8036 if (i386_record_modrm (&ir))
8037 return -1;
8038 if (ir.mod == 3)
8039 {
8040 ir.rm |= ir.rex_b;
8041 if (!i386_xmm_regnum_p (gdbarch,
8042 I387_XMM0_REGNUM (tdep) + ir.rm))
8043 goto no_support;
8044 record_full_arch_list_add_reg (ir.regcache,
8045 I387_XMM0_REGNUM (tdep) + ir.rm);
8046 }
8047 else
8048 {
8049 ir.ot = OT_QUAD;
8050 if (i386_record_lea_modrm (&ir))
8051 return -1;
8052 }
8053 break;
8054
8055 case 0x660f3817: /* ptest */
8056 case 0x0f2e: /* ucomiss */
8057 case 0x660f2e: /* ucomisd */
8058 case 0x0f2f: /* comiss */
8059 case 0x660f2f: /* comisd */
8060 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
8061 break;
8062
8063 case 0x0ff7: /* maskmovq */
8064 regcache_raw_read_unsigned (ir.regcache,
8065 ir.regmap[X86_RECORD_REDI_REGNUM],
8066 &addr);
8067 if (record_full_arch_list_add_mem (addr, 64))
8068 return -1;
8069 break;
8070
8071 case 0x660ff7: /* maskmovdqu */
8072 regcache_raw_read_unsigned (ir.regcache,
8073 ir.regmap[X86_RECORD_REDI_REGNUM],
8074 &addr);
8075 if (record_full_arch_list_add_mem (addr, 128))
8076 return -1;
8077 break;
8078
8079 default:
8080 goto no_support;
8081 break;
8082 }
8083 break;
8084
8085 default:
8086 goto no_support;
8087 break;
8088 }
8089
8090 /* In the future, maybe still need to deal with need_dasm. */
8091 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM);
8092 if (record_full_arch_list_add_end ())
8093 return -1;
8094
8095 return 0;
8096
8097 no_support:
8098 printf_unfiltered (_("Process record does not support instruction 0x%02x "
8099 "at address %s.\n"),
8100 (unsigned int) (opcode),
8101 paddress (gdbarch, ir.orig_addr));
8102 return -1;
8103 }
8104
8105 static const int i386_record_regmap[] =
8106 {
8107 I386_EAX_REGNUM, I386_ECX_REGNUM, I386_EDX_REGNUM, I386_EBX_REGNUM,
8108 I386_ESP_REGNUM, I386_EBP_REGNUM, I386_ESI_REGNUM, I386_EDI_REGNUM,
8109 0, 0, 0, 0, 0, 0, 0, 0,
8110 I386_EIP_REGNUM, I386_EFLAGS_REGNUM, I386_CS_REGNUM, I386_SS_REGNUM,
8111 I386_DS_REGNUM, I386_ES_REGNUM, I386_FS_REGNUM, I386_GS_REGNUM
8112 };
8113
8114 /* Check that the given address appears suitable for a fast
8115 tracepoint, which on x86-64 means that we need an instruction of at
8116 least 5 bytes, so that we can overwrite it with a 4-byte-offset
8117 jump and not have to worry about program jumps to an address in the
8118 middle of the tracepoint jump. On x86, it may be possible to use
8119 4-byte jumps with a 2-byte offset to a trampoline located in the
8120 bottom 64 KiB of memory. Returns 1 if OK, and writes a size
8121 of instruction to replace, and 0 if not, plus an explanatory
8122 string. */
8123
8124 static int
8125 i386_fast_tracepoint_valid_at (struct gdbarch *gdbarch, CORE_ADDR addr,
8126 char **msg)
8127 {
8128 int len, jumplen;
8129
8130 /* Ask the target for the minimum instruction length supported. */
8131 jumplen = target_get_min_fast_tracepoint_insn_len ();
8132
8133 if (jumplen < 0)
8134 {
8135 /* If the target does not support the get_min_fast_tracepoint_insn_len
8136 operation, assume that fast tracepoints will always be implemented
8137 using 4-byte relative jumps on both x86 and x86-64. */
8138 jumplen = 5;
8139 }
8140 else if (jumplen == 0)
8141 {
8142 /* If the target does support get_min_fast_tracepoint_insn_len but
8143 returns zero, then the IPA has not loaded yet. In this case,
8144 we optimistically assume that truncated 2-byte relative jumps
8145 will be available on x86, and compensate later if this assumption
8146 turns out to be incorrect. On x86-64 architectures, 4-byte relative
8147 jumps will always be used. */
8148 jumplen = (register_size (gdbarch, 0) == 8) ? 5 : 4;
8149 }
8150
8151 /* Check for fit. */
8152 len = gdb_insn_length (gdbarch, addr);
8153
8154 if (len < jumplen)
8155 {
8156 /* Return a bit of target-specific detail to add to the caller's
8157 generic failure message. */
8158 if (msg)
8159 *msg = xstrprintf (_("; instruction is only %d bytes long, "
8160 "need at least %d bytes for the jump"),
8161 len, jumplen);
8162 return 0;
8163 }
8164 else
8165 {
8166 if (msg)
8167 *msg = NULL;
8168 return 1;
8169 }
8170 }
8171
8172 /* Return a floating-point format for a floating-point variable of
8173 length LEN in bits. If non-NULL, NAME is the name of its type.
8174 If no suitable type is found, return NULL. */
8175
8176 const struct floatformat **
8177 i386_floatformat_for_type (struct gdbarch *gdbarch,
8178 const char *name, int len)
8179 {
8180 if (len == 128 && name)
8181 if (strcmp (name, "__float128") == 0
8182 || strcmp (name, "_Float128") == 0
8183 || strcmp (name, "complex _Float128") == 0)
8184 return floatformats_ia64_quad;
8185
8186 return default_floatformat_for_type (gdbarch, name, len);
8187 }
8188
8189 static int
8190 i386_validate_tdesc_p (struct gdbarch_tdep *tdep,
8191 struct tdesc_arch_data *tdesc_data)
8192 {
8193 const struct target_desc *tdesc = tdep->tdesc;
8194 const struct tdesc_feature *feature_core;
8195
8196 const struct tdesc_feature *feature_sse, *feature_avx, *feature_mpx,
8197 *feature_avx512, *feature_pkeys;
8198 int i, num_regs, valid_p;
8199
8200 if (! tdesc_has_registers (tdesc))
8201 return 0;
8202
8203 /* Get core registers. */
8204 feature_core = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.core");
8205 if (feature_core == NULL)
8206 return 0;
8207
8208 /* Get SSE registers. */
8209 feature_sse = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.sse");
8210
8211 /* Try AVX registers. */
8212 feature_avx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx");
8213
8214 /* Try MPX registers. */
8215 feature_mpx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx");
8216
8217 /* Try AVX512 registers. */
8218 feature_avx512 = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx512");
8219
8220 /* Try PKEYS */
8221 feature_pkeys = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.pkeys");
8222
8223 valid_p = 1;
8224
8225 /* The XCR0 bits. */
8226 if (feature_avx512)
8227 {
8228 /* AVX512 register description requires AVX register description. */
8229 if (!feature_avx)
8230 return 0;
8231
8232 tdep->xcr0 = X86_XSTATE_AVX_AVX512_MASK;
8233
8234 /* It may have been set by OSABI initialization function. */
8235 if (tdep->k0_regnum < 0)
8236 {
8237 tdep->k_register_names = i386_k_names;
8238 tdep->k0_regnum = I386_K0_REGNUM;
8239 }
8240
8241 for (i = 0; i < I387_NUM_K_REGS; i++)
8242 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8243 tdep->k0_regnum + i,
8244 i386_k_names[i]);
8245
8246 if (tdep->num_zmm_regs == 0)
8247 {
8248 tdep->zmmh_register_names = i386_zmmh_names;
8249 tdep->num_zmm_regs = 8;
8250 tdep->zmm0h_regnum = I386_ZMM0H_REGNUM;
8251 }
8252
8253 for (i = 0; i < tdep->num_zmm_regs; i++)
8254 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8255 tdep->zmm0h_regnum + i,
8256 tdep->zmmh_register_names[i]);
8257
8258 for (i = 0; i < tdep->num_xmm_avx512_regs; i++)
8259 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8260 tdep->xmm16_regnum + i,
8261 tdep->xmm_avx512_register_names[i]);
8262
8263 for (i = 0; i < tdep->num_ymm_avx512_regs; i++)
8264 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8265 tdep->ymm16h_regnum + i,
8266 tdep->ymm16h_register_names[i]);
8267 }
8268 if (feature_avx)
8269 {
8270 /* AVX register description requires SSE register description. */
8271 if (!feature_sse)
8272 return 0;
8273
8274 if (!feature_avx512)
8275 tdep->xcr0 = X86_XSTATE_AVX_MASK;
8276
8277 /* It may have been set by OSABI initialization function. */
8278 if (tdep->num_ymm_regs == 0)
8279 {
8280 tdep->ymmh_register_names = i386_ymmh_names;
8281 tdep->num_ymm_regs = 8;
8282 tdep->ymm0h_regnum = I386_YMM0H_REGNUM;
8283 }
8284
8285 for (i = 0; i < tdep->num_ymm_regs; i++)
8286 valid_p &= tdesc_numbered_register (feature_avx, tdesc_data,
8287 tdep->ymm0h_regnum + i,
8288 tdep->ymmh_register_names[i]);
8289 }
8290 else if (feature_sse)
8291 tdep->xcr0 = X86_XSTATE_SSE_MASK;
8292 else
8293 {
8294 tdep->xcr0 = X86_XSTATE_X87_MASK;
8295 tdep->num_xmm_regs = 0;
8296 }
8297
8298 num_regs = tdep->num_core_regs;
8299 for (i = 0; i < num_regs; i++)
8300 valid_p &= tdesc_numbered_register (feature_core, tdesc_data, i,
8301 tdep->register_names[i]);
8302
8303 if (feature_sse)
8304 {
8305 /* Need to include %mxcsr, so add one. */
8306 num_regs += tdep->num_xmm_regs + 1;
8307 for (; i < num_regs; i++)
8308 valid_p &= tdesc_numbered_register (feature_sse, tdesc_data, i,
8309 tdep->register_names[i]);
8310 }
8311
8312 if (feature_mpx)
8313 {
8314 tdep->xcr0 |= X86_XSTATE_MPX_MASK;
8315
8316 if (tdep->bnd0r_regnum < 0)
8317 {
8318 tdep->mpx_register_names = i386_mpx_names;
8319 tdep->bnd0r_regnum = I386_BND0R_REGNUM;
8320 tdep->bndcfgu_regnum = I386_BNDCFGU_REGNUM;
8321 }
8322
8323 for (i = 0; i < I387_NUM_MPX_REGS; i++)
8324 valid_p &= tdesc_numbered_register (feature_mpx, tdesc_data,
8325 I387_BND0R_REGNUM (tdep) + i,
8326 tdep->mpx_register_names[i]);
8327 }
8328
8329 if (feature_pkeys)
8330 {
8331 tdep->xcr0 |= X86_XSTATE_PKRU;
8332 if (tdep->pkru_regnum < 0)
8333 {
8334 tdep->pkeys_register_names = i386_pkeys_names;
8335 tdep->pkru_regnum = I386_PKRU_REGNUM;
8336 tdep->num_pkeys_regs = 1;
8337 }
8338
8339 for (i = 0; i < I387_NUM_PKEYS_REGS; i++)
8340 valid_p &= tdesc_numbered_register (feature_pkeys, tdesc_data,
8341 I387_PKRU_REGNUM (tdep) + i,
8342 tdep->pkeys_register_names[i]);
8343 }
8344
8345 return valid_p;
8346 }
8347
8348
8349 /* Note: This is called for both i386 and amd64. */
8350
8351 static struct gdbarch *
8352 i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
8353 {
8354 struct gdbarch_tdep *tdep;
8355 struct gdbarch *gdbarch;
8356 struct tdesc_arch_data *tdesc_data;
8357 const struct target_desc *tdesc;
8358 int mm0_regnum;
8359 int ymm0_regnum;
8360 int bnd0_regnum;
8361 int num_bnd_cooked;
8362
8363 /* If there is already a candidate, use it. */
8364 arches = gdbarch_list_lookup_by_info (arches, &info);
8365 if (arches != NULL)
8366 return arches->gdbarch;
8367
8368 /* Allocate space for the new architecture. Assume i386 for now. */
8369 tdep = XCNEW (struct gdbarch_tdep);
8370 gdbarch = gdbarch_alloc (&info, tdep);
8371
8372 /* General-purpose registers. */
8373 tdep->gregset_reg_offset = NULL;
8374 tdep->gregset_num_regs = I386_NUM_GREGS;
8375 tdep->sizeof_gregset = 0;
8376
8377 /* Floating-point registers. */
8378 tdep->sizeof_fpregset = I387_SIZEOF_FSAVE;
8379 tdep->fpregset = &i386_fpregset;
8380
8381 /* The default settings include the FPU registers, the MMX registers
8382 and the SSE registers. This can be overridden for a specific ABI
8383 by adjusting the members `st0_regnum', `mm0_regnum' and
8384 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
8385 will show up in the output of "info all-registers". */
8386
8387 tdep->st0_regnum = I386_ST0_REGNUM;
8388
8389 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
8390 tdep->num_xmm_regs = I386_NUM_XREGS - 1;
8391
8392 tdep->jb_pc_offset = -1;
8393 tdep->struct_return = pcc_struct_return;
8394 tdep->sigtramp_start = 0;
8395 tdep->sigtramp_end = 0;
8396 tdep->sigtramp_p = i386_sigtramp_p;
8397 tdep->sigcontext_addr = NULL;
8398 tdep->sc_reg_offset = NULL;
8399 tdep->sc_pc_offset = -1;
8400 tdep->sc_sp_offset = -1;
8401
8402 tdep->xsave_xcr0_offset = -1;
8403
8404 tdep->record_regmap = i386_record_regmap;
8405
8406 set_gdbarch_long_long_align_bit (gdbarch, 32);
8407
8408 /* The format used for `long double' on almost all i386 targets is
8409 the i387 extended floating-point format. In fact, of all targets
8410 in the GCC 2.95 tree, only OSF/1 does it different, and insists
8411 on having a `long double' that's not `long' at all. */
8412 set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext);
8413
8414 /* Although the i387 extended floating-point has only 80 significant
8415 bits, a `long double' actually takes up 96, probably to enforce
8416 alignment. */
8417 set_gdbarch_long_double_bit (gdbarch, 96);
8418
8419 /* Support for floating-point data type variants. */
8420 set_gdbarch_floatformat_for_type (gdbarch, i386_floatformat_for_type);
8421
8422 /* Register numbers of various important registers. */
8423 set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */
8424 set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */
8425 set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */
8426 set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */
8427
8428 /* NOTE: kettenis/20040418: GCC does have two possible register
8429 numbering schemes on the i386: dbx and SVR4. These schemes
8430 differ in how they number %ebp, %esp, %eflags, and the
8431 floating-point registers, and are implemented by the arrays
8432 dbx_register_map[] and svr4_dbx_register_map in
8433 gcc/config/i386.c. GCC also defines a third numbering scheme in
8434 gcc/config/i386.c, which it designates as the "default" register
8435 map used in 64bit mode. This last register numbering scheme is
8436 implemented in dbx64_register_map, and is used for AMD64; see
8437 amd64-tdep.c.
8438
8439 Currently, each GCC i386 target always uses the same register
8440 numbering scheme across all its supported debugging formats
8441 i.e. SDB (COFF), stabs and DWARF 2. This is because
8442 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
8443 DBX_REGISTER_NUMBER macro which is defined by each target's
8444 respective config header in a manner independent of the requested
8445 output debugging format.
8446
8447 This does not match the arrangement below, which presumes that
8448 the SDB and stabs numbering schemes differ from the DWARF and
8449 DWARF 2 ones. The reason for this arrangement is that it is
8450 likely to get the numbering scheme for the target's
8451 default/native debug format right. For targets where GCC is the
8452 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
8453 targets where the native toolchain uses a different numbering
8454 scheme for a particular debug format (stabs-in-ELF on Solaris)
8455 the defaults below will have to be overridden, like
8456 i386_elf_init_abi() does. */
8457
8458 /* Use the dbx register numbering scheme for stabs and COFF. */
8459 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum);
8460 set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum);
8461
8462 /* Use the SVR4 register numbering scheme for DWARF 2. */
8463 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_dwarf_reg_to_regnum);
8464
8465 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
8466 be in use on any of the supported i386 targets. */
8467
8468 set_gdbarch_print_float_info (gdbarch, i387_print_float_info);
8469
8470 set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target);
8471
8472 /* Call dummy code. */
8473 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
8474 set_gdbarch_push_dummy_code (gdbarch, i386_push_dummy_code);
8475 set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call);
8476 set_gdbarch_frame_align (gdbarch, i386_frame_align);
8477
8478 set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p);
8479 set_gdbarch_register_to_value (gdbarch, i386_register_to_value);
8480 set_gdbarch_value_to_register (gdbarch, i386_value_to_register);
8481
8482 set_gdbarch_return_value (gdbarch, i386_return_value);
8483
8484 set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue);
8485
8486 /* Stack grows downward. */
8487 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
8488
8489 set_gdbarch_breakpoint_kind_from_pc (gdbarch, i386_breakpoint::kind_from_pc);
8490 set_gdbarch_sw_breakpoint_from_kind (gdbarch, i386_breakpoint::bp_from_kind);
8491
8492 set_gdbarch_decr_pc_after_break (gdbarch, 1);
8493 set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN);
8494
8495 set_gdbarch_frame_args_skip (gdbarch, 8);
8496
8497 set_gdbarch_print_insn (gdbarch, i386_print_insn);
8498
8499 set_gdbarch_dummy_id (gdbarch, i386_dummy_id);
8500
8501 set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc);
8502
8503 /* Add the i386 register groups. */
8504 i386_add_reggroups (gdbarch);
8505 tdep->register_reggroup_p = i386_register_reggroup_p;
8506
8507 /* Helper for function argument information. */
8508 set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument);
8509
8510 /* Hook the function epilogue frame unwinder. This unwinder is
8511 appended to the list first, so that it supercedes the DWARF
8512 unwinder in function epilogues (where the DWARF unwinder
8513 currently fails). */
8514 frame_unwind_append_unwinder (gdbarch, &i386_epilogue_frame_unwind);
8515
8516 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
8517 to the list before the prologue-based unwinders, so that DWARF
8518 CFI info will be used if it is available. */
8519 dwarf2_append_unwinders (gdbarch);
8520
8521 frame_base_set_default (gdbarch, &i386_frame_base);
8522
8523 /* Pseudo registers may be changed by amd64_init_abi. */
8524 set_gdbarch_pseudo_register_read_value (gdbarch,
8525 i386_pseudo_register_read_value);
8526 set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write);
8527 set_gdbarch_ax_pseudo_register_collect (gdbarch,
8528 i386_ax_pseudo_register_collect);
8529
8530 set_tdesc_pseudo_register_type (gdbarch, i386_pseudo_register_type);
8531 set_tdesc_pseudo_register_name (gdbarch, i386_pseudo_register_name);
8532
8533 /* Override the normal target description method to make the AVX
8534 upper halves anonymous. */
8535 set_gdbarch_register_name (gdbarch, i386_register_name);
8536
8537 /* Even though the default ABI only includes general-purpose registers,
8538 floating-point registers and the SSE registers, we have to leave a
8539 gap for the upper AVX, MPX and AVX512 registers. */
8540 set_gdbarch_num_regs (gdbarch, I386_PKEYS_NUM_REGS);
8541
8542 set_gdbarch_gnu_triplet_regexp (gdbarch, i386_gnu_triplet_regexp);
8543
8544 /* Get the x86 target description from INFO. */
8545 tdesc = info.target_desc;
8546 if (! tdesc_has_registers (tdesc))
8547 tdesc = i386_target_description (X86_XSTATE_SSE_MASK);
8548 tdep->tdesc = tdesc;
8549
8550 tdep->num_core_regs = I386_NUM_GREGS + I387_NUM_REGS;
8551 tdep->register_names = i386_register_names;
8552
8553 /* No upper YMM registers. */
8554 tdep->ymmh_register_names = NULL;
8555 tdep->ymm0h_regnum = -1;
8556
8557 /* No upper ZMM registers. */
8558 tdep->zmmh_register_names = NULL;
8559 tdep->zmm0h_regnum = -1;
8560
8561 /* No high XMM registers. */
8562 tdep->xmm_avx512_register_names = NULL;
8563 tdep->xmm16_regnum = -1;
8564
8565 /* No upper YMM16-31 registers. */
8566 tdep->ymm16h_register_names = NULL;
8567 tdep->ymm16h_regnum = -1;
8568
8569 tdep->num_byte_regs = 8;
8570 tdep->num_word_regs = 8;
8571 tdep->num_dword_regs = 0;
8572 tdep->num_mmx_regs = 8;
8573 tdep->num_ymm_regs = 0;
8574
8575 /* No MPX registers. */
8576 tdep->bnd0r_regnum = -1;
8577 tdep->bndcfgu_regnum = -1;
8578
8579 /* No AVX512 registers. */
8580 tdep->k0_regnum = -1;
8581 tdep->num_zmm_regs = 0;
8582 tdep->num_ymm_avx512_regs = 0;
8583 tdep->num_xmm_avx512_regs = 0;
8584
8585 /* No PKEYS registers */
8586 tdep->pkru_regnum = -1;
8587 tdep->num_pkeys_regs = 0;
8588
8589 tdesc_data = tdesc_data_alloc ();
8590
8591 set_gdbarch_relocate_instruction (gdbarch, i386_relocate_instruction);
8592
8593 set_gdbarch_gen_return_address (gdbarch, i386_gen_return_address);
8594
8595 set_gdbarch_insn_is_call (gdbarch, i386_insn_is_call);
8596 set_gdbarch_insn_is_ret (gdbarch, i386_insn_is_ret);
8597 set_gdbarch_insn_is_jump (gdbarch, i386_insn_is_jump);
8598
8599 /* Hook in ABI-specific overrides, if they have been registered.
8600 Note: If INFO specifies a 64 bit arch, this is where we turn
8601 a 32-bit i386 into a 64-bit amd64. */
8602 info.tdesc_data = tdesc_data;
8603 gdbarch_init_osabi (info, gdbarch);
8604
8605 if (!i386_validate_tdesc_p (tdep, tdesc_data))
8606 {
8607 tdesc_data_cleanup (tdesc_data);
8608 xfree (tdep);
8609 gdbarch_free (gdbarch);
8610 return NULL;
8611 }
8612
8613 num_bnd_cooked = (tdep->bnd0r_regnum > 0 ? I387_NUM_BND_REGS : 0);
8614
8615 /* Wire in pseudo registers. Number of pseudo registers may be
8616 changed. */
8617 set_gdbarch_num_pseudo_regs (gdbarch, (tdep->num_byte_regs
8618 + tdep->num_word_regs
8619 + tdep->num_dword_regs
8620 + tdep->num_mmx_regs
8621 + tdep->num_ymm_regs
8622 + num_bnd_cooked
8623 + tdep->num_ymm_avx512_regs
8624 + tdep->num_zmm_regs));
8625
8626 /* Target description may be changed. */
8627 tdesc = tdep->tdesc;
8628
8629 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
8630
8631 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */
8632 set_gdbarch_register_reggroup_p (gdbarch, tdep->register_reggroup_p);
8633
8634 /* Make %al the first pseudo-register. */
8635 tdep->al_regnum = gdbarch_num_regs (gdbarch);
8636 tdep->ax_regnum = tdep->al_regnum + tdep->num_byte_regs;
8637
8638 ymm0_regnum = tdep->ax_regnum + tdep->num_word_regs;
8639 if (tdep->num_dword_regs)
8640 {
8641 /* Support dword pseudo-register if it hasn't been disabled. */
8642 tdep->eax_regnum = ymm0_regnum;
8643 ymm0_regnum += tdep->num_dword_regs;
8644 }
8645 else
8646 tdep->eax_regnum = -1;
8647
8648 mm0_regnum = ymm0_regnum;
8649 if (tdep->num_ymm_regs)
8650 {
8651 /* Support YMM pseudo-register if it is available. */
8652 tdep->ymm0_regnum = ymm0_regnum;
8653 mm0_regnum += tdep->num_ymm_regs;
8654 }
8655 else
8656 tdep->ymm0_regnum = -1;
8657
8658 if (tdep->num_ymm_avx512_regs)
8659 {
8660 /* Support YMM16-31 pseudo registers if available. */
8661 tdep->ymm16_regnum = mm0_regnum;
8662 mm0_regnum += tdep->num_ymm_avx512_regs;
8663 }
8664 else
8665 tdep->ymm16_regnum = -1;
8666
8667 if (tdep->num_zmm_regs)
8668 {
8669 /* Support ZMM pseudo-register if it is available. */
8670 tdep->zmm0_regnum = mm0_regnum;
8671 mm0_regnum += tdep->num_zmm_regs;
8672 }
8673 else
8674 tdep->zmm0_regnum = -1;
8675
8676 bnd0_regnum = mm0_regnum;
8677 if (tdep->num_mmx_regs != 0)
8678 {
8679 /* Support MMX pseudo-register if MMX hasn't been disabled. */
8680 tdep->mm0_regnum = mm0_regnum;
8681 bnd0_regnum += tdep->num_mmx_regs;
8682 }
8683 else
8684 tdep->mm0_regnum = -1;
8685
8686 if (tdep->bnd0r_regnum > 0)
8687 tdep->bnd0_regnum = bnd0_regnum;
8688 else
8689 tdep-> bnd0_regnum = -1;
8690
8691 /* Hook in the legacy prologue-based unwinders last (fallback). */
8692 frame_unwind_append_unwinder (gdbarch, &i386_stack_tramp_frame_unwind);
8693 frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind);
8694 frame_unwind_append_unwinder (gdbarch, &i386_frame_unwind);
8695
8696 /* If we have a register mapping, enable the generic core file
8697 support, unless it has already been enabled. */
8698 if (tdep->gregset_reg_offset
8699 && !gdbarch_iterate_over_regset_sections_p (gdbarch))
8700 set_gdbarch_iterate_over_regset_sections
8701 (gdbarch, i386_iterate_over_regset_sections);
8702
8703 set_gdbarch_fast_tracepoint_valid_at (gdbarch,
8704 i386_fast_tracepoint_valid_at);
8705
8706 return gdbarch;
8707 }
8708
8709
8710
8711 /* Return the target description for a specified XSAVE feature mask. */
8712
8713 const struct target_desc *
8714 i386_target_description (uint64_t xcr0)
8715 {
8716 static target_desc *i386_tdescs \
8717 [2/*SSE*/][2/*AVX*/][2/*MPX*/][2/*AVX512*/][2/*PKRU*/] = {};
8718 target_desc **tdesc;
8719
8720 tdesc = &i386_tdescs[(xcr0 & X86_XSTATE_SSE) ? 1 : 0]
8721 [(xcr0 & X86_XSTATE_AVX) ? 1 : 0]
8722 [(xcr0 & X86_XSTATE_MPX) ? 1 : 0]
8723 [(xcr0 & X86_XSTATE_AVX512) ? 1 : 0]
8724 [(xcr0 & X86_XSTATE_PKRU) ? 1 : 0];
8725
8726 if (*tdesc == NULL)
8727 *tdesc = i386_create_target_description (xcr0, false);
8728
8729 return *tdesc;
8730 }
8731
8732 #define MPX_BASE_MASK (~(ULONGEST) 0xfff)
8733
8734 /* Find the bound directory base address. */
8735
8736 static unsigned long
8737 i386_mpx_bd_base (void)
8738 {
8739 struct regcache *rcache;
8740 struct gdbarch_tdep *tdep;
8741 ULONGEST ret;
8742 enum register_status regstatus;
8743
8744 rcache = get_current_regcache ();
8745 tdep = gdbarch_tdep (rcache->arch ());
8746
8747 regstatus = regcache_raw_read_unsigned (rcache, tdep->bndcfgu_regnum, &ret);
8748
8749 if (regstatus != REG_VALID)
8750 error (_("BNDCFGU register invalid, read status %d."), regstatus);
8751
8752 return ret & MPX_BASE_MASK;
8753 }
8754
8755 int
8756 i386_mpx_enabled (void)
8757 {
8758 const struct gdbarch_tdep *tdep = gdbarch_tdep (get_current_arch ());
8759 const struct target_desc *tdesc = tdep->tdesc;
8760
8761 return (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx") != NULL);
8762 }
8763
8764 #define MPX_BD_MASK 0xfffffff00000ULL /* select bits [47:20] */
8765 #define MPX_BT_MASK 0x0000000ffff8 /* select bits [19:3] */
8766 #define MPX_BD_MASK_32 0xfffff000 /* select bits [31:12] */
8767 #define MPX_BT_MASK_32 0x00000ffc /* select bits [11:2] */
8768
8769 /* Find the bound table entry given the pointer location and the base
8770 address of the table. */
8771
8772 static CORE_ADDR
8773 i386_mpx_get_bt_entry (CORE_ADDR ptr, CORE_ADDR bd_base)
8774 {
8775 CORE_ADDR offset1;
8776 CORE_ADDR offset2;
8777 CORE_ADDR mpx_bd_mask, bd_ptr_r_shift, bd_ptr_l_shift;
8778 CORE_ADDR bt_mask, bt_select_r_shift, bt_select_l_shift;
8779 CORE_ADDR bd_entry_addr;
8780 CORE_ADDR bt_addr;
8781 CORE_ADDR bd_entry;
8782 struct gdbarch *gdbarch = get_current_arch ();
8783 struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr;
8784
8785
8786 if (gdbarch_ptr_bit (gdbarch) == 64)
8787 {
8788 mpx_bd_mask = (CORE_ADDR) MPX_BD_MASK;
8789 bd_ptr_r_shift = 20;
8790 bd_ptr_l_shift = 3;
8791 bt_select_r_shift = 3;
8792 bt_select_l_shift = 5;
8793 bt_mask = (CORE_ADDR) MPX_BT_MASK;
8794
8795 if ( sizeof (CORE_ADDR) == 4)
8796 error (_("bound table examination not supported\
8797 for 64-bit process with 32-bit GDB"));
8798 }
8799 else
8800 {
8801 mpx_bd_mask = MPX_BD_MASK_32;
8802 bd_ptr_r_shift = 12;
8803 bd_ptr_l_shift = 2;
8804 bt_select_r_shift = 2;
8805 bt_select_l_shift = 4;
8806 bt_mask = MPX_BT_MASK_32;
8807 }
8808
8809 offset1 = ((ptr & mpx_bd_mask) >> bd_ptr_r_shift) << bd_ptr_l_shift;
8810 bd_entry_addr = bd_base + offset1;
8811 bd_entry = read_memory_typed_address (bd_entry_addr, data_ptr_type);
8812
8813 if ((bd_entry & 0x1) == 0)
8814 error (_("Invalid bounds directory entry at %s."),
8815 paddress (get_current_arch (), bd_entry_addr));
8816
8817 /* Clearing status bit. */
8818 bd_entry--;
8819 bt_addr = bd_entry & ~bt_select_r_shift;
8820 offset2 = ((ptr & bt_mask) >> bt_select_r_shift) << bt_select_l_shift;
8821
8822 return bt_addr + offset2;
8823 }
8824
8825 /* Print routine for the mpx bounds. */
8826
8827 static void
8828 i386_mpx_print_bounds (const CORE_ADDR bt_entry[4])
8829 {
8830 struct ui_out *uiout = current_uiout;
8831 LONGEST size;
8832 struct gdbarch *gdbarch = get_current_arch ();
8833 CORE_ADDR onecompl = ~((CORE_ADDR) 0);
8834 int bounds_in_map = ((~bt_entry[1] == 0 && bt_entry[0] == onecompl) ? 1 : 0);
8835
8836 if (bounds_in_map == 1)
8837 {
8838 uiout->text ("Null bounds on map:");
8839 uiout->text (" pointer value = ");
8840 uiout->field_core_addr ("pointer-value", gdbarch, bt_entry[2]);
8841 uiout->text (".");
8842 uiout->text ("\n");
8843 }
8844 else
8845 {
8846 uiout->text ("{lbound = ");
8847 uiout->field_core_addr ("lower-bound", gdbarch, bt_entry[0]);
8848 uiout->text (", ubound = ");
8849
8850 /* The upper bound is stored in 1's complement. */
8851 uiout->field_core_addr ("upper-bound", gdbarch, ~bt_entry[1]);
8852 uiout->text ("}: pointer value = ");
8853 uiout->field_core_addr ("pointer-value", gdbarch, bt_entry[2]);
8854
8855 if (gdbarch_ptr_bit (gdbarch) == 64)
8856 size = ( (~(int64_t) bt_entry[1]) - (int64_t) bt_entry[0]);
8857 else
8858 size = ( ~((int32_t) bt_entry[1]) - (int32_t) bt_entry[0]);
8859
8860 /* In case the bounds are 0x0 and 0xffff... the difference will be -1.
8861 -1 represents in this sense full memory access, and there is no need
8862 one to the size. */
8863
8864 size = (size > -1 ? size + 1 : size);
8865 uiout->text (", size = ");
8866 uiout->field_fmt ("size", "%s", plongest (size));
8867
8868 uiout->text (", metadata = ");
8869 uiout->field_core_addr ("metadata", gdbarch, bt_entry[3]);
8870 uiout->text ("\n");
8871 }
8872 }
8873
8874 /* Implement the command "show mpx bound". */
8875
8876 static void
8877 i386_mpx_info_bounds (const char *args, int from_tty)
8878 {
8879 CORE_ADDR bd_base = 0;
8880 CORE_ADDR addr;
8881 CORE_ADDR bt_entry_addr = 0;
8882 CORE_ADDR bt_entry[4];
8883 int i;
8884 struct gdbarch *gdbarch = get_current_arch ();
8885 struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr;
8886
8887 if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_i386
8888 || !i386_mpx_enabled ())
8889 {
8890 printf_unfiltered (_("Intel Memory Protection Extensions not "
8891 "supported on this target.\n"));
8892 return;
8893 }
8894
8895 if (args == NULL)
8896 {
8897 printf_unfiltered (_("Address of pointer variable expected.\n"));
8898 return;
8899 }
8900
8901 addr = parse_and_eval_address (args);
8902
8903 bd_base = i386_mpx_bd_base ();
8904 bt_entry_addr = i386_mpx_get_bt_entry (addr, bd_base);
8905
8906 memset (bt_entry, 0, sizeof (bt_entry));
8907
8908 for (i = 0; i < 4; i++)
8909 bt_entry[i] = read_memory_typed_address (bt_entry_addr
8910 + i * TYPE_LENGTH (data_ptr_type),
8911 data_ptr_type);
8912
8913 i386_mpx_print_bounds (bt_entry);
8914 }
8915
8916 /* Implement the command "set mpx bound". */
8917
8918 static void
8919 i386_mpx_set_bounds (const char *args, int from_tty)
8920 {
8921 CORE_ADDR bd_base = 0;
8922 CORE_ADDR addr, lower, upper;
8923 CORE_ADDR bt_entry_addr = 0;
8924 CORE_ADDR bt_entry[2];
8925 const char *input = args;
8926 int i;
8927 struct gdbarch *gdbarch = get_current_arch ();
8928 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
8929 struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr;
8930
8931 if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_i386
8932 || !i386_mpx_enabled ())
8933 error (_("Intel Memory Protection Extensions not supported\
8934 on this target."));
8935
8936 if (args == NULL)
8937 error (_("Pointer value expected."));
8938
8939 addr = value_as_address (parse_to_comma_and_eval (&input));
8940
8941 if (input[0] == ',')
8942 ++input;
8943 if (input[0] == '\0')
8944 error (_("wrong number of arguments: missing lower and upper bound."));
8945 lower = value_as_address (parse_to_comma_and_eval (&input));
8946
8947 if (input[0] == ',')
8948 ++input;
8949 if (input[0] == '\0')
8950 error (_("Wrong number of arguments; Missing upper bound."));
8951 upper = value_as_address (parse_to_comma_and_eval (&input));
8952
8953 bd_base = i386_mpx_bd_base ();
8954 bt_entry_addr = i386_mpx_get_bt_entry (addr, bd_base);
8955 for (i = 0; i < 2; i++)
8956 bt_entry[i] = read_memory_typed_address (bt_entry_addr
8957 + i * TYPE_LENGTH (data_ptr_type),
8958 data_ptr_type);
8959 bt_entry[0] = (uint64_t) lower;
8960 bt_entry[1] = ~(uint64_t) upper;
8961
8962 for (i = 0; i < 2; i++)
8963 write_memory_unsigned_integer (bt_entry_addr
8964 + i * TYPE_LENGTH (data_ptr_type),
8965 TYPE_LENGTH (data_ptr_type), byte_order,
8966 bt_entry[i]);
8967 }
8968
8969 static struct cmd_list_element *mpx_set_cmdlist, *mpx_show_cmdlist;
8970
8971 /* Helper function for the CLI commands. */
8972
8973 static void
8974 set_mpx_cmd (const char *args, int from_tty)
8975 {
8976 help_list (mpx_set_cmdlist, "set mpx ", all_commands, gdb_stdout);
8977 }
8978
8979 /* Helper function for the CLI commands. */
8980
8981 static void
8982 show_mpx_cmd (const char *args, int from_tty)
8983 {
8984 cmd_show_list (mpx_show_cmdlist, from_tty, "");
8985 }
8986
8987 void
8988 _initialize_i386_tdep (void)
8989 {
8990 register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init);
8991
8992 /* Add the variable that controls the disassembly flavor. */
8993 add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors,
8994 &disassembly_flavor, _("\
8995 Set the disassembly flavor."), _("\
8996 Show the disassembly flavor."), _("\
8997 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
8998 NULL,
8999 NULL, /* FIXME: i18n: */
9000 &setlist, &showlist);
9001
9002 /* Add the variable that controls the convention for returning
9003 structs. */
9004 add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions,
9005 &struct_convention, _("\
9006 Set the convention for returning small structs."), _("\
9007 Show the convention for returning small structs."), _("\
9008 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
9009 is \"default\"."),
9010 NULL,
9011 NULL, /* FIXME: i18n: */
9012 &setlist, &showlist);
9013
9014 /* Add "mpx" prefix for the set commands. */
9015
9016 add_prefix_cmd ("mpx", class_support, set_mpx_cmd, _("\
9017 Set Intel Memory Protection Extensions specific variables."),
9018 &mpx_set_cmdlist, "set mpx ",
9019 0 /* allow-unknown */, &setlist);
9020
9021 /* Add "mpx" prefix for the show commands. */
9022
9023 add_prefix_cmd ("mpx", class_support, show_mpx_cmd, _("\
9024 Show Intel Memory Protection Extensions specific variables."),
9025 &mpx_show_cmdlist, "show mpx ",
9026 0 /* allow-unknown */, &showlist);
9027
9028 /* Add "bound" command for the show mpx commands list. */
9029
9030 add_cmd ("bound", no_class, i386_mpx_info_bounds,
9031 "Show the memory bounds for a given array/pointer storage\
9032 in the bound table.",
9033 &mpx_show_cmdlist);
9034
9035 /* Add "bound" command for the set mpx commands list. */
9036
9037 add_cmd ("bound", no_class, i386_mpx_set_bounds,
9038 "Set the memory bounds for a given array/pointer storage\
9039 in the bound table.",
9040 &mpx_set_cmdlist);
9041
9042 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4,
9043 i386_svr4_init_abi);
9044
9045 /* Initialize the i386-specific register groups. */
9046 i386_init_reggroups ();
9047
9048 /* Tell remote stub that we support XML target description. */
9049 register_remote_support_xml ("i386");
9050
9051 #if GDB_SELF_TEST
9052 struct
9053 {
9054 const char *xml;
9055 uint64_t mask;
9056 } xml_masks[] = {
9057 { "i386/i386.xml", X86_XSTATE_SSE_MASK },
9058 { "i386/i386-mmx.xml", X86_XSTATE_X87_MASK },
9059 { "i386/i386-avx.xml", X86_XSTATE_AVX_MASK },
9060 { "i386/i386-mpx.xml", X86_XSTATE_MPX_MASK },
9061 { "i386/i386-avx-mpx.xml", X86_XSTATE_AVX_MPX_MASK },
9062 { "i386/i386-avx-avx512.xml", X86_XSTATE_AVX_AVX512_MASK },
9063 { "i386/i386-avx-mpx-avx512-pku.xml",
9064 X86_XSTATE_AVX_MPX_AVX512_PKU_MASK },
9065 };
9066
9067 for (auto &a : xml_masks)
9068 {
9069 auto tdesc = i386_target_description (a.mask);
9070
9071 selftests::record_xml_tdesc (a.xml, tdesc);
9072 }
9073 #endif /* GDB_SELF_TEST */
9074 }
i386_zmm_regnum_p
int i386_zmm_regnum_p(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:229
reggroup_add
void reggroup_add(struct gdbarch *gdbarch, struct reggroup *group)
Definition: reggroups.c:117
i386_register_reggroup_p
int i386_register_reggroup_p(struct gdbarch *gdbarch, int regnum, struct reggroup *group)
Definition: i386-tdep.c:4515
target_gdbarch
struct gdbarch * target_gdbarch(void)
Definition: gdbarch.c:5467
set_gdbarch_num_regs
void set_gdbarch_num_regs(struct gdbarch *gdbarch, int num_regs)
Definition: gdbarch.c:2050
gdbarch
Definition: gdbarch.c:127
PREFIX_DATA
#define PREFIX_DATA
Definition: i386-tdep.c:4634
i386_record_s::mod
uint8_t mod
Definition: i386-tdep.c:4670
set_gdbarch_frame_align
void set_gdbarch_frame_align(struct gdbarch *gdbarch, gdbarch_frame_align_ftype frame_align)
Definition: gdbarch.c:3151
X86_XSTATE_AVX_MASK
#define X86_XSTATE_AVX_MASK
Definition: x86-xstate.h:43
i387_collect_fsave
void i387_collect_fsave(const struct regcache *regcache, int regnum, void *fsave)
Definition: i387-tdep.c:493
set_gdbarch_value_to_register
void set_gdbarch_value_to_register(struct gdbarch *gdbarch, gdbarch_value_to_register_ftype value_to_register)
Definition: gdbarch.c:2639
i386_record_lea_modrm
static int i386_record_lea_modrm(struct i386_record_s *irp)
Definition: i386-tdep.c:4900
i386_supply_gregset
void i386_supply_gregset(const struct regset *regset, struct regcache *regcache, int regnum, const void *gregs, size_t len)
Definition: i386-tdep.c:3839
i386_unwind_pc
static CORE_ADDR i386_unwind_pc(struct gdbarch *gdbarch, struct frame_info *next_frame)
Definition: i386-tdep.c:1961
I386_NUM_GREGS
#define I386_NUM_GREGS
Definition: i386-tdep.h:332
hex_string
char * hex_string(LONGEST num)
Definition: print-utils.c:220
axs_value
Definition: ax-gdb.h:77
i386_stack_tramp_frame_unwind
static const struct frame_unwind i386_stack_tramp_frame_unwind
Definition: i386-tdep.c:2396
type_code
type_code
Definition: gdbtypes.h:80
i386_store_return_value
static void i386_store_return_value(struct gdbarch *gdbarch, struct type *type, struct regcache *regcache, const gdb_byte *valbuf)
Definition: i386-tdep.c:2835
TYPE_CODE_ARRAY
Definition: gdbtypes.h:104
gdbarch_tdep::jb_pc_offset
int jb_pc_offset
Definition: i386-tdep.h:210
gdbarch_tdep::xsave_xcr0_offset
int xsave_xcr0_offset
Definition: i386-tdep.h:144
set_gdbarch_ps_regnum
void set_gdbarch_ps_regnum(struct gdbarch *gdbarch, int ps_regnum)
Definition: gdbarch.c:2190
X86_RECORD_RESI_REGNUM
Definition: i386-tdep.h:312
i386_mpx_info_bounds
static void i386_mpx_info_bounds(const char *args, int from_tty)
Definition: i386-tdep.c:8877
i386_record_s::popl_esp_hack
int popl_esp_hack
Definition: i386-tdep.c:4675
i386_frame_cache
static struct i386_frame_cache * i386_frame_cache(struct frame_info *this_frame, void **this_cache)
Definition: i386-tdep.c:2074
frame_id_build
struct frame_id frame_id_build(CORE_ADDR stack_addr, CORE_ADDR code_addr)
Definition: frame.c:624
I387_FOP_REGNUM
#define I387_FOP_REGNUM(tdep)
Definition: i387-tdep.h:63
extract_typed_address
CORE_ADDR extract_typed_address(const gdb_byte *buf, struct type *type)
Definition: findvar.c:154
set_gdbarch_get_longjmp_target
void set_gdbarch_get_longjmp_target(struct gdbarch *gdbarch, gdbarch_get_longjmp_target_ftype get_longjmp_target)
Definition: gdbarch.c:2572
gdbarch_tdep::register_reggroup_p
gdbarch_register_reggroup_p_ftype * register_reggroup_p
Definition: i386-tdep.h:207
gdbarch_tdep::zmm0_regnum
int zmm0_regnum
Definition: i386-tdep.h:99
REG_VALID
Definition: common-regcache.h:32
i386_match_insn
static struct i386_insn * i386_match_insn(CORE_ADDR pc, struct i386_insn *insn_patterns)
Definition: i386-tdep.c:1432
PREFIX_ADDR
#define PREFIX_ADDR
Definition: i386-tdep.c:4635
gdbarch_tdep::i386_bnd_type
struct type * i386_bnd_type
Definition: i386-tdep.h:239
buf_displaced_step_closure
Definition: infrun.h:256
i386_frame_cache::sp_offset
LONGEST sp_offset
Definition: i386-tdep.c:1073
target_get_min_fast_tracepoint_insn_len
#define target_get_min_fast_tracepoint_insn_len()
Definition: target.h:2182
gdbarch_tdep::xmm16_regnum
int xmm16_regnum
Definition: i386-tdep.h:130
i386_frame_cache::pc
CORE_ADDR pc
Definition: i386-tdep.c:1074
set_tdesc_pseudo_register_name
void set_tdesc_pseudo_register_name(struct gdbarch *gdbarch, gdbarch_register_name_ftype *pseudo_name)
Definition: target-descriptions.c:1341
I386_DS_REGNUM
Definition: i386-tdep.h:283
gdbarch_tdep::num_core_regs
int num_core_regs
Definition: i386-tdep.h:121
i386_mpx_set_bounds
static void i386_mpx_set_bounds(const char *args, int from_tty)
Definition: i386-tdep.c:8919
ui_out::field_core_addr
void field_core_addr(const char *fldname, struct gdbarch *gdbarch, CORE_ADDR address)
Definition: ui-out.c:513
i386_ymmh_regnum_p
static int i386_ymmh_regnum_p(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:255
get_frame_pc
CORE_ADDR get_frame_pc(struct frame_info *frame)
Definition: frame.c:2376
I386_EFLAGS_REGNUM
Definition: i386-tdep.h:280
I387_NUM_MPX_CTRL_REGS
#define I387_NUM_MPX_CTRL_REGS
Definition: i387-tdep.h:45
i386_frame_cache::saved_regs
CORE_ADDR saved_regs[I386_NUM_SAVED_REGS]
Definition: i386-tdep.c:1077
valid_conventions
static const char *const valid_conventions[]
Definition: i386-tdep.c:2901
set_gdbarch_fp0_regnum
void set_gdbarch_fp0_regnum(struct gdbarch *gdbarch, int fp0_regnum)
Definition: gdbarch.c:2207
MSYMBOL_LINKAGE_NAME
#define MSYMBOL_LINKAGE_NAME(symbol)
Definition: symtab.h:707
offset1
unsigned short offset1
Definition: go32-nat.c:1072
X86_XSTATE_SSE_MASK
#define X86_XSTATE_SSE_MASK
Definition: x86-xstate.h:42
stap_parse_info::arg_type
struct type * arg_type
Definition: stap-probe.h:60
CORE_ADDR
bfd_vma CORE_ADDR
Definition: common-types.h:41
i386_k_regnum_p
int i386_k_regnum_p(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:242
value::type
struct type * type
Definition: value.c:266
gdbarch_tdep::mpx_register_names
const char ** mpx_register_names
Definition: i386-tdep.h:176
i386_stap_parse_special_token_three_arg_disp
static int i386_stap_parse_special_token_three_arg_disp(struct gdbarch *gdbarch, struct stap_parse_info *p)
Definition: i386-tdep.c:4221
gdbarch_init_osabi
void gdbarch_init_osabi(struct gdbarch_info info, struct gdbarch *gdbarch)
Definition: osabi.c:334
displaced_step_dump_bytes
void displaced_step_dump_bytes(struct ui_file *file, const gdb_byte *buf, size_t len)
Definition: infrun.c:1721
I386_NUM_SAVED_REGS
#define I386_NUM_SAVED_REGS
Definition: i386-tdep.c:1066
att_flavor
static const char att_flavor[]
Definition: i386-tdep.c:585
target_write_memory
int target_write_memory(CORE_ADDR memaddr, const gdb_byte *myaddr, ssize_t len)
Definition: target.c:1451
reggroup_new
struct reggroup * reggroup_new(const char *name, enum reggroup_type type)
Definition: reggroups.c:40
i386_process_record
int i386_process_record(struct gdbarch *gdbarch, struct regcache *regcache, CORE_ADDR input_addr)
Definition: i386-tdep.c:5025
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struct type * i386_pseudo_register_type(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:3219
command.h
i386_record_s::dflag
int dflag
Definition: i386-tdep.c:4667
i386_alloc_frame_cache
static struct i386_frame_cache * i386_alloc_frame_cache(void)
Definition: i386-tdep.c:1089
gdbarch_tdep::sc_num_regs
int sc_num_regs
Definition: i386-tdep.h:227
ax_reg_mask
void ax_reg_mask(struct agent_expr *ax, int reg)
Definition: ax-general.c:425
stap-probe.h
OP_ANDL
Definition: i386-tdep.c:4654
I387_BND0R_REGNUM
#define I387_BND0R_REGNUM(tdep)
Definition: i387-tdep.h:39
stoken::ptr
const char * ptr
Definition: parser-defs.h:91
set_gdbarch_stap_parse_special_token
void set_gdbarch_stap_parse_special_token(struct gdbarch *gdbarch, gdbarch_stap_parse_special_token_ftype stap_parse_special_token)
Definition: gdbarch.c:4499
i386_syscall_p
static int i386_syscall_p(const gdb_byte *insn, int *lengthp)
Definition: i386-tdep.c:742
xfree
void xfree(void *)
i386_dword_regnum_p
int i386_dword_regnum_p(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:201
default_struct_convention
static const char default_struct_convention[]
Definition: i386-tdep.c:2898
i386_record_s::addr
CORE_ADDR addr
Definition: i386-tdep.c:4665
gdbarch_tdep::ymm16h_register_names
const char ** ymm16h_register_names
Definition: i386-tdep.h:161
no_class
Definition: command.h:41
gdbarch_tdep::i386_intx80_record
int(* i386_intx80_record)(struct regcache *regcache)
Definition: i386-tdep.h:246
i386_stack_frame_destroyed_p
static int i386_stack_frame_destroyed_p(struct gdbarch *gdbarch, CORE_ADDR pc)
Definition: i386-tdep.c:2212
default_floatformat_for_type
const struct floatformat ** default_floatformat_for_type(struct gdbarch *gdbarch, const char *name, int len)
Definition: arch-utils.c:230
class_support
Definition: command.h:42
i386_zmmh_regnum_p
int i386_zmmh_regnum_p(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:216
record-full.h
PREFIX_REPZ
#define PREFIX_REPZ
Definition: i386-tdep.c:4631
record_full_arch_list_add_reg
int record_full_arch_list_add_reg(struct regcache *regcache, int regnum)
Definition: record-full.c:468
X86_XSTATE_MPX_MASK
#define X86_XSTATE_MPX_MASK
Definition: x86-xstate.h:44
frame_unwind_got_memory
struct value * frame_unwind_got_memory(struct frame_info *frame, int regnum, CORE_ADDR addr)
Definition: frame-unwind.c:233
cmd_list_element
Definition: cli-decode.h:46
write_memory_unsigned_integer
void write_memory_unsigned_integer(CORE_ADDR addr, int len, enum bfd_endian byte_order, ULONGEST value)
Definition: corefile.c:417
buf_displaced_step_closure::buf
gdb::byte_vector buf
Definition: infrun.h:262
set_tdesc_pseudo_register_type
void set_tdesc_pseudo_register_type(struct gdbarch *gdbarch, gdbarch_register_type_ftype *pseudo_type)
Definition: target-descriptions.c:1351
gdbarch_tdep::sigtramp_start
CORE_ADDR sigtramp_start
Definition: i386-tdep.h:216
iterate_over_regset_sections_cb
void() iterate_over_regset_sections_cb(const char *sect_name, int size, const struct regset *regset, const char *human_name, void *cb_data)
Definition: gdbarch.h:99
gdbarch_tdep::ymm16_regnum
int ymm16_regnum
Definition: i386-tdep.h:136
set_gdbarch_skip_trampoline_code
void set_gdbarch_skip_trampoline_code(struct gdbarch *gdbarch, gdbarch_skip_trampoline_code_ftype skip_trampoline_code)
Definition: gdbarch.c:3316
MPX_BT_MASK
#define MPX_BT_MASK
Definition: i386-tdep.c:8765
i386_convert_register_p
static int i386_convert_register_p(struct gdbarch *gdbarch, int regnum, struct type *type)
Definition: i386-tdep.c:3738
set_gdbarch_relocate_instruction
void set_gdbarch_relocate_instruction(struct gdbarch *gdbarch, gdbarch_relocate_instruction_ftype relocate_instruction)
Definition: gdbarch.c:4024
I386_PKRU_REGNUM
Definition: i386-tdep.h:299
warning
void warning(const char *fmt,...)
Definition: errors.c:26
i386_zmmh_names
static const char * i386_zmmh_names[]
Definition: i386-tdep.c:90
set_gdbarch_gen_return_address
void set_gdbarch_gen_return_address(struct gdbarch *gdbarch, gdbarch_gen_return_address_ftype gen_return_address)
Definition: gdbarch.c:4764
i386_frame_cache::base
CORE_ADDR base
Definition: i386-tdep.c:1071
i386_insn::mask
gdb_byte mask[I386_MAX_MATCHED_INSN_LEN]
Definition: i386-tdep.c:1392
i387_supply_fxsave
void i387_supply_fxsave(struct regcache *regcache, int regnum, const void *fxsave)
Definition: i387-tdep.c:586
set_gdbarch_stab_reg_to_regnum
void set_gdbarch_stab_reg_to_regnum(struct gdbarch *gdbarch, gdbarch_stab_reg_to_regnum_ftype stab_reg_to_regnum)
Definition: gdbarch.c:2224
TYPE_NAME
#define TYPE_NAME(thistype)
Definition: gdbtypes.h:1224
i386_extract_return_value
static void i386_extract_return_value(struct gdbarch *gdbarch, struct type *type, struct regcache *regcache, gdb_byte *valbuf)
Definition: i386-tdep.c:2784
i386_zmm_names
static const char * i386_zmm_names[]
Definition: i386-tdep.c:84
gdbarch_tdep::num_mmx_regs
int num_mmx_regs
Definition: i386-tdep.h:74
X86_RECORD_CS_REGNUM
Definition: i386-tdep.h:324
OT_WORD
Definition: i386-tdep.c:4641
gdbarch_ptr_bit
int gdbarch_ptr_bit(struct gdbarch *gdbarch)
Definition: gdbarch.c:1831
value_enclosing_type
struct type * value_enclosing_type(const struct value *value)
Definition: value.c:1175
set_gdbarch_sdb_reg_to_regnum
void set_gdbarch_sdb_reg_to_regnum(struct gdbarch *gdbarch, gdbarch_sdb_reg_to_regnum_ftype sdb_reg_to_regnum)
Definition: gdbarch.c:2258
plongest
char * plongest(LONGEST l)
Definition: print-utils.c:137
set_gdbarch_stap_register_prefixes
void set_gdbarch_stap_register_prefixes(struct gdbarch *gdbarch, const char *const *stap_register_prefixes)
Definition: gdbarch.c:4366
lval_register
Definition: defs.h:385
register_remote_support_xml
void register_remote_support_xml(const char *xml)
Definition: remote.c:4662
gdb_insn_length
int gdb_insn_length(struct gdbarch *gdbarch, CORE_ADDR addr)
Definition: disasm.c:826
reggroups.h
stap_parse_info
Definition: stap-probe.h:29
i386_word_names
static const char * i386_word_names[]
Definition: i386-tdep.c:149
i386_svr4_sigtramp_p
static int i386_svr4_sigtramp_p(struct frame_info *this_frame)
Definition: i386-tdep.c:4024
i386_mpx_bd_base
static unsigned long i386_mpx_bd_base(void)
Definition: i386-tdep.c:8737
builtin_type
const struct builtin_type * builtin_type(struct gdbarch *gdbarch)
Definition: gdbtypes.c:5217
mark_value_bytes_unavailable
void mark_value_bytes_unavailable(struct value *value, LONGEST offset, LONGEST length)
Definition: value.c:601
RETURN_MASK_ERROR
Definition: common-exceptions.h:43
i386_fpregset
const struct regset i386_fpregset
Definition: i386-tdep.c:3933
frame_id_build_unavailable_stack
struct frame_id frame_id_build_unavailable_stack(CORE_ADDR code_addr)
Definition: frame.c:597
gdbarch_tdep::i386_syscall_record
int(* i386_syscall_record)(struct regcache *regcache)
Definition: i386-tdep.h:250
memset
void * memset(T *s, int c, size_t n)=delete
internal_error
void internal_error(const char *file, int line, const char *fmt,...)
Definition: errors.c:50
gdbarch_tdep::num_word_regs
int num_word_regs
Definition: i386-tdep.h:108
frame_unwind_register
void frame_unwind_register(struct frame_info *frame, int regnum, gdb_byte *buf)
Definition: frame.c:1145
i386_displaced_step_copy_insn
struct displaced_step_closure * i386_displaced_step_copy_insn(struct gdbarch *gdbarch, CORE_ADDR from, CORE_ADDR to, struct regcache *regs)
Definition: i386-tdep.c:800
set_gdbarch_ax_pseudo_register_collect
void set_gdbarch_ax_pseudo_register_collect(struct gdbarch *gdbarch, gdbarch_ax_pseudo_register_collect_ftype ax_pseudo_register_collect)
Definition: gdbarch.c:2091
gdbarch_tdep::sigtramp_end
CORE_ADDR sigtramp_end
Definition: i386-tdep.h:217
ax-gdb.h
tdesc_register_name
const char * tdesc_register_name(struct gdbarch *gdbarch, int regno)
Definition: target-descriptions.c:1173
record_debug
unsigned int record_debug
Definition: record.c:33
gdbarch_tdep::pc
struct m32c_reg * pc
Definition: m32c-tdep.c:116
i386_sse_reggroup
static struct reggroup * i386_sse_reggroup
Definition: i386-tdep.c:4490
gdbarch_tdep
Definition: aarch64-tdep.h:55
return_value_convention
return_value_convention
Definition: defs.h:247
stap_parse_info::arg
const char * arg
Definition: stap-probe.h:46
I386_NUM_XREGS
#define I386_NUM_XREGS
Definition: i386-tdep.h:333
OT_LONG
Definition: i386-tdep.c:4642
i386_sigtramp_p
int i386_sigtramp_p(struct frame_info *this_frame)
Definition: i386-tdep.c:3988
i386_frame_cache::base_p
int base_p
Definition: i386-tdep.c:1072
I387_NUM_MPX_REGS
#define I387_NUM_MPX_REGS
Definition: i387-tdep.h:43
i386_skip_noop
static CORE_ADDR i386_skip_noop(CORE_ADDR pc)
Definition: i386-tdep.c:1539
add_setshow_enum_cmd
void add_setshow_enum_cmd(const char *name, enum command_class theclass, const char *const *enumlist, const char **var, const char *set_doc, const char *show_doc, const char *help_doc, cmd_const_sfunc_ftype *set_func, show_value_ftype *show_func, struct cmd_list_element **set_list, struct cmd_list_element **show_list)
Definition: cli-decode.c:515
I386_SS_REGNUM
Definition: i386-tdep.h:282
i386_stap_parse_special_token
int i386_stap_parse_special_token(struct gdbarch *gdbarch, struct stap_parse_info *p)
Definition: i386-tdep.c:4378
disasm.h
X86_RECORD_REAX_REGNUM
Definition: i386-tdep.h:306
set_gdbarch_register_reggroup_p
void set_gdbarch_register_reggroup_p(struct gdbarch *gdbarch, gdbarch_register_reggroup_p_ftype register_reggroup_p)
Definition: gdbarch.c:3599
i386_xmm_avx512_regnum_p
int i386_xmm_avx512_regnum_p(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:341
target_float_convert
void target_float_convert(const gdb_byte *from, const struct type *from_type, gdb_byte *to, const struct type *to_type)
Definition: target-float.c:2429
i386_print_insn
static int i386_print_insn(bfd_vma pc, struct disassemble_info *info)
Definition: i386-tdep.c:4002
i386_record_s::override
int override
Definition: i386-tdep.c:4668
I387_NUM_XMM_REGS
#define I387_NUM_XMM_REGS(tdep)
Definition: i387-tdep.h:33
ON_STACK
#define ON_STACK
Definition: inferior.h:263
i386_mpx_enabled
int i386_mpx_enabled(void)
Definition: i386-tdep.c:8756
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Definition: i386-tdep.c:96
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static CORE_ADDR i386_analyze_struct_return(CORE_ADDR pc, CORE_ADDR current_pc, struct i386_frame_cache *cache)
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Definition: i386-tdep.c:2426
OP_ADDL
Definition: i386-tdep.c:4650
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Definition: i386-tdep.c:1388
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struct cmd_list_element * add_prefix_cmd(const char *name, enum command_class theclass, cmd_const_cfunc_ftype *fun, const char *doc, struct cmd_list_element **prefixlist, const char *prefixname, int allow_unknown, struct cmd_list_element **list)
Definition: cli-decode.c:367
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Definition: symtab.c:2988
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Definition: i386-tdep.c:1398
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Definition: regset.h:34
I386_CS_REGNUM
Definition: i386-tdep.h:281
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void set_gdbarch_floatformat_for_type(struct gdbarch *gdbarch, gdbarch_floatformat_for_type_ftype floatformat_for_type)
Definition: gdbarch.c:1824
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Definition: i386-tdep.c:270
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Definition: common-exceptions.h:82
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Definition: gdbarch.c:2057
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Definition: common-exceptions.h:246
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Definition: stap-probe.h:49
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Definition: reggroups.c:315
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Definition: i386-tdep.c:593
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Definition: x86-xstate.h:38
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Definition: gdbtypes.h:1542
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Definition: gdbarch.c:2032
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Definition: i386-tdep.h:286
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Definition: gdbtypes.c:5208
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Definition: gdbtypes.c:2421
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Definition: corefile.c:316
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Definition: frame.h:244
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ULONGEST gdbarch_max_insn_length(struct gdbarch *gdbarch)
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Definition: i386-tdep.c:1825
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Definition: common-exceptions.h:254
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Definition: reggroups.c:314
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Definition: i387-tdep.c:669
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#define I387_FSTAT_REGNUM(tdep)
Definition: i387-tdep.h:57
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#define X86_XSTATE_AVX_AVX512_MASK
Definition: x86-xstate.h:46
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Definition: i386-tdep.c:4669
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Definition: i386-tdep.c:787
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Definition: i386-tdep.c:2900
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Definition: i386-tdep.c:8766
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enum struct_return struct_return
Definition: arm-tdep.h:137
I386_EIP_REGNUM
Definition: i386-tdep.h:279
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Definition: gdbarch.c:4880
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static const struct frame_base i386_frame_base
Definition: i386-tdep.c:2563
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Definition: i386-tdep.c:1927
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static int i386_epilogue_frame_sniffer(const struct frame_unwind *self, struct frame_info *this_frame, void **this_prologue_cache)
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Definition: minsyms.c:1492
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Definition: defs.h:514
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Definition: i386-tdep.c:2348
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Definition: defs.h:577
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Definition: i386-tdep.h:154
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OT_DQUAD
Definition: i386-tdep.c:4644
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Definition: infrun.c:156
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void set_gdbarch_decr_pc_after_break(struct gdbarch *gdbarch, CORE_ADDR decr_pc_after_break)
Definition: gdbarch.c:2980
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static CORE_ADDR i386_push_dummy_call(struct gdbarch *gdbarch, struct value *function, struct regcache *regcache, CORE_ADDR bp_addr, int nargs, struct value **args, CORE_ADDR sp, int struct_return, CORE_ADDR struct_addr)
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Definition: regcache.c:152
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Definition: i386-tdep.h:287
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Definition: arch-utils.c:950
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Definition: i386-tdep.c:609
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buf_displaced_step_closure i386_displaced_step_closure
Definition: i386-tdep.h:421
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#define X86_XSTATE_SSE
Definition: x86-xstate.h:25
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Definition: i386-tdep.c:4953
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static const char * i386_gnu_triplet_regexp(struct gdbarch *gdbarch)
Definition: i386-tdep.c:4429
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Definition: i386-tdep.c:607
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const char ** pkeys_register_names
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Definition: i387-tdep.h:54
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Definition: i387-tdep.c:327
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Definition: i386-tdep.c:4652
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Definition: i386-tdep.h:297
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Definition: record-full.c:161
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Definition: i386-tdep.c:3625
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Definition: i386-tdep.h:327
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Definition: corefile.c:336
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Definition: regdef.h:22
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Definition: i386-tdep.c:2292
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Definition: frame.c:1334
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Definition: record-full.c:491
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Definition: i386-tdep.h:339
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Definition: gdb_assert.h:32
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Definition: i386-tdep.c:2193
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Definition: gdbarch.h:1660
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Definition: value.c:169
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Definition: i386-tdep.h:285
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Definition: i387-tdep.h:117
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Definition: i386-tdep.c:4039
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Definition: i387-tdep.h:35
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static struct value * i386_pseudo_register_read_value(struct gdbarch *gdbarch, struct regcache *regcache, int regnum)
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Definition: i386-tdep.h:272
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Definition: i386-tdep.c:4674
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Definition: parse.c:205
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Definition: i386-tdep.c:1390
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Definition: regcache.c:957
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Definition: x86-xstate.h:41
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Definition: i386-tdep.c:2099
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const char * i386_pseudo_register_name(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:457
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Definition: i386-tdep.c:2915
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Definition: i386-tdep.c:970
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Definition: i386-tdep.c:4663
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static int i386_ymmh_avx512_regnum_p(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:283
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Definition: common-exceptions.c:312
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Definition: target-descriptions.c:1374
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Definition: i386-tdep.h:71
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Definition: common-types.h:38
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Definition: i386-tdep.c:8767
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Definition: i386-tdep.c:4951
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static const struct frame_unwind i386_sigtramp_frame_unwind
Definition: i386-tdep.c:2544
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static int i386_mmx_regnum_to_fp_regnum(struct regcache *regcache, int regnum)
Definition: i386-tdep.c:3251
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static struct type * i386_zmm_type(struct gdbarch *gdbarch)
Definition: i386-tdep.c:3071
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Definition: i386-tdep.h:158
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Definition: cli-decode.c:1071
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const struct floatformat * floatformats_i387_ext[BFD_ENDIAN_UNKNOWN]
Definition: gdbtypes.c:84
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Definition: i386-tdep.c:4655
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int(* sigtramp_p)(struct frame_info *)
Definition: i386-tdep.h:220
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Definition: defs.h:264
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ULONGEST align_up(ULONGEST v, int n)
Definition: utils.c:2997
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gdb_byte insn[I386_MAX_MATCHED_INSN_LEN]
Definition: i386-tdep.c:1391
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int i386_svr4_reg_to_regnum(struct gdbarch *gdbarch, int reg)
Definition: i386-tdep.c:572
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Definition: gdbtypes.h:1226
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struct type * i386_ymm_type
Definition: i386-tdep.h:236
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Definition: gdbtypes.h:1511
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struct bound_minimal_symbol lookup_minimal_symbol_by_pc(CORE_ADDR pc)
Definition: minsyms.c:928
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Definition: i386-tdep.h:141
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static void i386_collect_gregset(const struct regset *regset, const struct regcache *regcache, int regnum, void *gregs, size_t len)
Definition: i386-tdep.c:3863
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void set_gdbarch_convert_register_p(struct gdbarch *gdbarch, gdbarch_convert_register_p_ftype convert_register_p)
Definition: gdbarch.c:2605
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Definition: i386-tdep.c:4664
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int ot
Definition: i386-tdep.c:4671
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static const struct frame_unwind i386_epilogue_frame_unwind
Definition: i386-tdep.c:2315
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Definition: frame.c:1372
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static struct value * i386_sigtramp_frame_prev_register(struct frame_info *this_frame, void **this_cache, int regnum)
Definition: i386-tdep.c:2505
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Definition: poison.h:121
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struct gdbarch * gdbarch
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Definition: frame.c:2610
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Definition: windows-nat.c:323
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Definition: eval.c:101
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Definition: i386-tdep.h:278
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Definition: gdbtypes.h:1238
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static void i386_collect_fpregset(const struct regset *regset, const struct regcache *regcache, int regnum, void *fpregs, size_t len)
Definition: i386-tdep.c:3909
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enum register_status regcache_raw_read(struct regcache *regcache, int regnum, gdb_byte *buf)
Definition: regcache.c:565
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struct type * i386_mmx_type
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const int * record_regmap
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Definition: frame-unwind.c:223
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Definition: regcache.c:806
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#define X86_XSTATE_AVX512
Definition: x86-xstate.h:35
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int num_pkeys_regs
Definition: i386-tdep.h:195
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static CORE_ADDR i386_mpx_get_bt_entry(CORE_ADDR ptr, CORE_ADDR bd_base)
Definition: i386-tdep.c:8773
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void set_gdbarch_fast_tracepoint_valid_at(struct gdbarch *gdbarch, gdbarch_fast_tracepoint_valid_at_ftype fast_tracepoint_valid_at)
Definition: gdbarch.c:4663
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int target_read_memory(CORE_ADDR memaddr, gdb_byte *myaddr, ssize_t len)
Definition: target.c:1370
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Definition: i386-tdep.h:310
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static struct cmd_list_element * mpx_show_cmdlist
Definition: i386-tdep.c:8969
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int num_xmm_regs
Definition: i386-tdep.h:124
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Definition: target-descriptions.c:591
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static int i386_insn_is_ret(struct gdbarch *gdbarch, CORE_ADDR addr)
Definition: i386-tdep.c:774
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struct type * builtin_data_ptr
Definition: gdbtypes.h:1554
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Definition: minsyms.h:34
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Definition: i386-tdep.c:4058
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void set_gdbarch_stap_is_single_operand(struct gdbarch *gdbarch, gdbarch_stap_is_single_operand_ftype stap_is_single_operand)
Definition: gdbarch.c:4475
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static CORE_ADDR i386_analyze_frame_setup(struct gdbarch *gdbarch, CORE_ADDR pc, CORE_ADDR limit, struct i386_frame_cache *cache)
Definition: i386-tdep.c:1593
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static void i386_supply_fpregset(const struct regset *regset, struct regcache *regcache, int regnum, const void *fpregs, size_t len)
Definition: i386-tdep.c:3887
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static int i386_validate_tdesc_p(struct gdbarch_tdep *tdep, struct tdesc_arch_data *tdesc_data)
Definition: i386-tdep.c:8190
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Definition: i386-tdep.c:4439
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Definition: agent.c:65
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Definition: i386-tdep.c:1449
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Definition: regcache.c:640
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Definition: ser-unix.c:239
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Definition: i387-tdep.h:40
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Definition: gdbarch.c:2473
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Definition: i386-tdep.h:295
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static const char * i386_mpx_names[]
Definition: i386-tdep.c:114
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void get_frame_register(struct frame_info *frame, int regnum, gdb_byte *buf)
Definition: frame.c:1165
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Definition: gdbtypes.h:1239
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set_gdbarch_num_pseudo_regs
void set_gdbarch_num_pseudo_regs(struct gdbarch *gdbarch, int num_pseudo_regs)
Definition: gdbarch.c:2067
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gdbarch * arch() const
Definition: regcache.c:221
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static int i386_next_regnum(int regnum)
Definition: i386-tdep.c:3709
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Definition: i386-tdep.c:4952
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Definition: dwarf2-frame.c:1384
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Definition: i386-tdep.h:63
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Definition: i386-tdep.c:2572
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int eax_regnum
Definition: i386-tdep.h:118
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Definition: i386-tdep.c:4632
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Definition: defs.h:570
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Definition: i387-tdep.h:116
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struct m32c_reg regs[M32C_MAX_NUM_REGS]
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Definition: i386-tdep.c:2556
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Definition: i386-tdep.h:308
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Definition: i387-tdep.h:66
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Definition: i386-tdep.h:342
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Definition: i386-tdep.h:204
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Definition: i386-tdep.c:4657
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Definition: i386-tdep.c:296
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Definition: i386-tdep.h:253
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Definition: x86-xstate.h:29
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Definition: regcache.c:164
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Definition: regcache.h:232
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OT_QUAD
Definition: i386-tdep.c:4643
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Definition: gdbarch.c:1756
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Definition: i386-tdep.c:1973
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static int i386_register_to_value(struct frame_info *frame, int regnum, struct type *type, gdb_byte *to, int *optimizedp, int *unavailablep)
Definition: i386-tdep.c:3769
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#define I387_NUM_XMM_AVX512_REGS(tdep)
Definition: i387-tdep.h:34
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const struct bfd_arch_info * gdbarch_bfd_arch_info(struct gdbarch *gdbarch)
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Definition: regcache.c:1085
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Definition: i386-tdep.h:325
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Definition: command.h:39
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int gdbarch_pc_regnum(struct gdbarch *gdbarch)
Definition: gdbarch.c:2163
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Definition: value.c:2762
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Definition: x86-xstate.h:45
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static int i386_record_floats(struct gdbarch *gdbarch, struct i386_record_s *ir, uint32_t iregnum)
Definition: i386-tdep.c:4959
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Definition: gdbarch.c:1772
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Definition: i386-tdep.c:4676
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Definition: value.c:1158
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Definition: reggroups.c:192
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struct reggroup *const save_reggroup
Definition: reggroups.c:319
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#define I387_FCTRL_REGNUM(tdep)
Definition: i387-tdep.h:56
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static void i386_gen_return_address(struct gdbarch *gdbarch, struct agent_expr *ax, struct axs_value *value, CORE_ADDR scope)
Definition: i386-tdep.c:2409
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Definition: gdbtypes.h:1235
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Definition: symtab.h:623
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static int i386_insn_is_call(struct gdbarch *gdbarch, CORE_ADDR addr)
Definition: i386-tdep.c:761
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int mm0_regnum
Definition: i386-tdep.h:78
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Definition: i386-tdep.h:284
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enum register_status regcache_raw_read_unsigned(struct regcache *regcache, int regnum, ULONGEST *val)
Definition: regcache.c:612
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Definition: gdbarch.c:2381
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Definition: i386-tdep.c:2362
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#define COMPUNIT_EPILOGUE_UNWIND_VALID(cust)
Definition: symtab.h:1468
OT_BYTE
Definition: i386-tdep.c:4640
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static struct gdbarch * i386_gdbarch_init(struct gdbarch_info info, struct gdbarch_list *arches)
Definition: i386-tdep.c:8352
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ULONGEST read_memory_unsigned_integer(CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
Definition: corefile.c:326
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Definition: gdbarch.c:4863
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void set_gdbarch_sw_breakpoint_from_kind(struct gdbarch *gdbarch, gdbarch_sw_breakpoint_from_kind_ftype sw_breakpoint_from_kind)
Definition: gdbarch.c:2888
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Definition: corefile.c:383
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void set_gdbarch_iterate_over_regset_sections(struct gdbarch *gdbarch, gdbarch_iterate_over_regset_sections_ftype iterate_over_regset_sections)
Definition: gdbarch.c:3647
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static int i386_mxcsr_regnum_p(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:354
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Definition: gdbarch.c:5299
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static CORE_ADDR i386_frame_align(struct gdbarch *gdbarch, CORE_ADDR sp)
Definition: i386-tdep.c:2586
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void write_memory(CORE_ADDR memaddr, const bfd_byte *myaddr, ssize_t len)
Definition: corefile.c:394
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void set_gdbarch_skip_prologue(struct gdbarch *gdbarch, gdbarch_skip_prologue_ftype skip_prologue)
Definition: gdbarch.c:2772
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const char ** k_register_names
Definition: i386-tdep.h:183
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int k0_regnum
Definition: i386-tdep.h:92
X86_RECORD_REDI_REGNUM
Definition: i386-tdep.h:313
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Definition: gdbtypes.h:1534
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void i386_pseudo_register_read_into_value(struct gdbarch *gdbarch, struct regcache *regcache, int regnum, struct value *result_value)
Definition: i386-tdep.c:3271
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static struct gdbarch_data * tdesc_data
Definition: target-descriptions.c:725
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const int num_lower_zmm_regs
Definition: i386-tdep.c:159
RETURN_VALUE_REGISTER_CONVENTION
Definition: defs.h:251
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struct tdesc_arch_data * tdesc_data
Definition: gdbarch.h:1648
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#define I387_NUM_REGS
Definition: i387-tdep.h:30
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Definition: i386-tdep.c:1078
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Definition: parser-defs.h:88
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int gregset_num_regs
Definition: i386-tdep.h:62
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enum bfd_endian byte_order
Definition: gdbarch.c:137
X86_XSTATE_AVX
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Definition: x86-xstate.h:26
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void i386_iterate_over_regset_sections(struct gdbarch *gdbarch, iterate_over_regset_sections_cb *cb, void *cb_data, const struct regcache *regcache)
Definition: i386-tdep.c:3941
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void set_gdbarch_pc_regnum(struct gdbarch *gdbarch, int pc_regnum)
Definition: gdbarch.c:2173
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void set_gdbarch_max_insn_length(struct gdbarch *gdbarch, ULONGEST max_insn_length)
Definition: gdbarch.c:3916
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static const char * i386_byte_names[]
Definition: i386-tdep.c:141
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int record_full_arch_list_add_end(void)
Definition: record-full.c:522
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Definition: parse.c:277
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Definition: gdbarch.c:2292
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Definition: frame.c:1001
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Definition: i386-tdep.c:8974
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Definition: i386-tdep.h:165
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Definition: i386-tdep.h:326
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Definition: i386-tdep.h:293
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Definition: defs.h:597
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Definition: i386-tdep.c:1227
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Definition: errors.c:38
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Definition: i386-tdep.h:273
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Definition: go32-nat.c:242
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Definition: i386-tdep.h:105
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Definition: gdbarch.c:361
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Definition: gdbarch.c:2837
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Definition: i386-tdep.h:291
X86_RECORD_REIP_REGNUM
Definition: i386-tdep.h:322
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Definition: i386-tdep.h:271
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Definition: gdbtypes.c:381
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Definition: frame.h:111
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Definition: i387-tdep.h:47
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Definition: i386-tdep.c:311
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Definition: i386-tdep.h:169
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Definition: frame.c:2691
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Definition: x86-xstate.h:47
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Definition: i386-tdep.c:8714
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int gdb_buffered_insn_length(struct gdbarch *gdbarch, const gdb_byte *insn, int max_len, CORE_ADDR addr)
Definition: disasm.c:871
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Definition: i386-tdep.c:4702
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Definition: i386-tdep.c:5021
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Definition: i386-tdep.c:586
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Definition: arm-tdep.h:90
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int zmm0h_regnum
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Definition: defs.h:604
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Definition: gdbarch.h:1620
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