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arm.h
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1 /* Common target dependent code for GDB on ARM systems.
2 Copyright (C) 1988-2018 Free Software Foundation, Inc.
3
4 This file is part of GDB.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program. If not, see <http://www.gnu.org/licenses/>. */
18
19 #ifndef ARM_H
20 #define ARM_H
21
22 /* Register numbers of various important registers. */
23
24 enum gdb_regnum {
25 ARM_A1_REGNUM = 0, /* first integer-like argument */
26 ARM_A4_REGNUM = 3, /* last integer-like argument */
27 ARM_AP_REGNUM = 11,
28 ARM_IP_REGNUM = 12,
29 ARM_SP_REGNUM = 13, /* Contains address of top of stack */
30 ARM_LR_REGNUM = 14, /* address to return to from a function call */
31 ARM_PC_REGNUM = 15, /* Contains program counter */
32 ARM_F0_REGNUM = 16, /* first floating point register */
33 ARM_F3_REGNUM = 19, /* last floating point argument register */
34 ARM_F7_REGNUM = 23, /* last floating point register */
35 ARM_FPS_REGNUM = 24, /* floating point status register */
36 ARM_PS_REGNUM = 25, /* Contains processor status */
37 ARM_WR0_REGNUM, /* WMMX data registers. */
38 ARM_WR15_REGNUM = ARM_WR0_REGNUM + 15,
39 ARM_WC0_REGNUM, /* WMMX control registers. */
40 ARM_WCSSF_REGNUM = ARM_WC0_REGNUM + 2,
41 ARM_WCASF_REGNUM = ARM_WC0_REGNUM + 3,
42 ARM_WC7_REGNUM = ARM_WC0_REGNUM + 7,
43 ARM_WCGR0_REGNUM, /* WMMX general purpose registers. */
44 ARM_WCGR3_REGNUM = ARM_WCGR0_REGNUM + 3,
45 ARM_WCGR7_REGNUM = ARM_WCGR0_REGNUM + 7,
46 ARM_D0_REGNUM, /* VFP double-precision registers. */
47 ARM_D31_REGNUM = ARM_D0_REGNUM + 31,
48 ARM_FPSCR_REGNUM,
49
50 ARM_NUM_REGS,
51
52 /* Other useful registers. */
53 ARM_FP_REGNUM = 11, /* Frame register in ARM code, if used. */
54 THUMB_FP_REGNUM = 7, /* Frame register in Thumb code, if used. */
55 ARM_NUM_ARG_REGS = 4,
56 ARM_LAST_ARG_REGNUM = ARM_A4_REGNUM,
57 ARM_NUM_FP_ARG_REGS = 4,
58 ARM_LAST_FP_ARG_REGNUM = ARM_F3_REGNUM
59 };
60
61 /* Enum describing the different kinds of breakpoints. */
62 enum arm_breakpoint_kinds
63 {
64 ARM_BP_KIND_THUMB = 2,
65 ARM_BP_KIND_THUMB2 = 3,
66 ARM_BP_KIND_ARM = 4,
67 };
68
69 /* Instruction condition field values. */
70 #define INST_EQ 0x0
71 #define INST_NE 0x1
72 #define INST_CS 0x2
73 #define INST_CC 0x3
74 #define INST_MI 0x4
75 #define INST_PL 0x5
76 #define INST_VS 0x6
77 #define INST_VC 0x7
78 #define INST_HI 0x8
79 #define INST_LS 0x9
80 #define INST_GE 0xa
81 #define INST_LT 0xb
82 #define INST_GT 0xc
83 #define INST_LE 0xd
84 #define INST_AL 0xe
85 #define INST_NV 0xf
86
87 #define FLAG_N 0x80000000
88 #define FLAG_Z 0x40000000
89 #define FLAG_C 0x20000000
90 #define FLAG_V 0x10000000
91
92 #define CPSR_T 0x20
93
94 #define XPSR_T 0x01000000
95
96 /* Size of integer registers. */
97 #define INT_REGISTER_SIZE 4
98
99 /* Addresses for calling Thumb functions have the bit 0 set.
100 Here are some macros to test, set, or clear bit 0 of addresses. */
101 #define IS_THUMB_ADDR(addr) ((addr) & 1)
102 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
103 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
104
105 /* Support routines for instruction parsing. */
106 #define submask(x) ((1L << ((x) + 1)) - 1)
107 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
108 #define bit(obj,st) (((obj) >> (st)) & 1)
109 #define sbits(obj,st,fn) \
110 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
111 #define BranchDest(addr,instr) \
112 ((CORE_ADDR) (((unsigned long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
113
114 /* Forward declaration. */
115 struct regcache;
116
117 /* Return the size in bytes of the complete Thumb instruction whose
118 first halfword is INST1. */
119 int thumb_insn_size (unsigned short inst1);
120
121 /* Returns true if the condition evaluates to true. */
122 int condition_true (unsigned long cond, unsigned long status_reg);
123
124 /* Return number of 1-bits in VAL. */
125 int bitcount (unsigned long val);
126
127 /* Return 1 if THIS_INSTR might change control flow, 0 otherwise. */
128 int arm_instruction_changes_pc (uint32_t this_instr);
129
130 /* Return 1 if the 16-bit Thumb instruction INST might change
131 control flow, 0 otherwise. */
132 int thumb_instruction_changes_pc (unsigned short inst);
133
134 /* Return 1 if the 32-bit Thumb instruction in INST1 and INST2
135 might change control flow, 0 otherwise. */
136 int thumb2_instruction_changes_pc (unsigned short inst1, unsigned short inst2);
137
138 /* Advance the state of the IT block and return that state. */
139 int thumb_advance_itstate (unsigned int itstate);
140
141 /* Decode shifted register value. */
142
143 unsigned long shifted_reg_val (struct regcache *regcache,
144 unsigned long inst,
145 int carry,
146 unsigned long pc_val,
147 unsigned long status_reg);
148
149 #endif
ARM_WCASF_REGNUM
Definition: arm.h:41
ARM_NUM_FP_ARG_REGS
Definition: arm.h:57
thumb_instruction_changes_pc
int thumb_instruction_changes_pc(unsigned short inst)
Definition: arm.c:204
ARM_F7_REGNUM
Definition: arm.h:34
ARM_D0_REGNUM
Definition: arm.h:46
ARM_WR15_REGNUM
Definition: arm.h:38
ARM_WCGR3_REGNUM
Definition: arm.h:44
gdb_regnum
gdb_regnum
Definition: arm.h:24
ARM_NUM_ARG_REGS
Definition: arm.h:55
ARM_F3_REGNUM
Definition: arm.h:33
ARM_A4_REGNUM
Definition: arm.h:26
ARM_LAST_ARG_REGNUM
Definition: arm.h:56
ARM_IP_REGNUM
Definition: arm.h:28
thumb_advance_itstate
int thumb_advance_itstate(unsigned int itstate)
Definition: arm.c:96
thumb_insn_size
int thumb_insn_size(unsigned short inst1)
Definition: arm.c:27
condition_true
int condition_true(unsigned long cond, unsigned long status_reg)
Definition: arm.c:49
ARM_WC0_REGNUM
Definition: arm.h:39
ARM_WR0_REGNUM
Definition: arm.h:37
ARM_BP_KIND_ARM
Definition: arm.h:66
ARM_NUM_REGS
Definition: arm.h:50
shifted_reg_val
unsigned long shifted_reg_val(struct regcache *regcache, unsigned long inst, int carry, unsigned long pc_val, unsigned long status_reg)
Definition: arm.c:325
thumb2_instruction_changes_pc
int thumb2_instruction_changes_pc(unsigned short inst1, unsigned short inst2)
Definition: arm.c:231
ARM_WCGR7_REGNUM
Definition: arm.h:45
ARM_D31_REGNUM
Definition: arm.h:47
ARM_A1_REGNUM
Definition: arm.h:25
ARM_FPSCR_REGNUM
Definition: arm.h:48
ARM_LR_REGNUM
Definition: arm.h:30
ARM_FP_REGNUM
Definition: arm.h:53
ARM_WC7_REGNUM
Definition: arm.h:42
ARM_PS_REGNUM
Definition: arm.h:36
ARM_SP_REGNUM
Definition: arm.h:29
ARM_AP_REGNUM
Definition: arm.h:27
ARM_BP_KIND_THUMB2
Definition: arm.h:65
THUMB_FP_REGNUM
Definition: arm.h:54
regcache
Definition: regcache.h:232
ARM_BP_KIND_THUMB
Definition: arm.h:64
ARM_WCSSF_REGNUM
Definition: arm.h:40
ARM_FPS_REGNUM
Definition: arm.h:35
ARM_PC_REGNUM
Definition: arm.h:31
arm_instruction_changes_pc
int arm_instruction_changes_pc(uint32_t this_instr)
Definition: arm.c:112
ARM_LAST_FP_ARG_REGNUM
Definition: arm.h:58
arm_breakpoint_kinds
arm_breakpoint_kinds
Definition: arm.h:62
ARM_WCGR0_REGNUM
Definition: arm.h:43
ARM_F0_REGNUM
Definition: arm.h:32
bitcount
int bitcount(unsigned long val)
Definition: arm.c:38