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/tmp/gdb-8.1/gdb/ppc-linux-nat.c
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1 /* PPC GNU/Linux native support.
2
3 Copyright (C) 1988-2018 Free Software Foundation, Inc.
4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19
20 #include "defs.h"
21 #include "observer.h"
22 #include "frame.h"
23 #include "inferior.h"
24 #include "gdbthread.h"
25 #include "gdbcore.h"
26 #include "regcache.h"
27 #include "target.h"
28 #include "linux-nat.h"
29 #include <sys/types.h>
30 #include <signal.h>
31 #include <sys/user.h>
32 #include <sys/ioctl.h>
33 #include "gdb_wait.h"
34 #include <fcntl.h>
35 #include <sys/procfs.h>
36 #include "nat/gdb_ptrace.h"
37 #include "inf-ptrace.h"
38
39 /* Prototypes for supply_gregset etc. */
40 #include "gregset.h"
41 #include "ppc-tdep.h"
42 #include "ppc-linux-tdep.h"
43
44 /* Required when using the AUXV. */
45 #include "elf/common.h"
46 #include "auxv.h"
47
48 #include "nat/ppc-linux.h"
49
50 /* Similarly for the hardware watchpoint support. These requests are used
51 when the PowerPC HWDEBUG ptrace interface is not available. */
52 #ifndef PTRACE_GET_DEBUGREG
53 #define PTRACE_GET_DEBUGREG 25
54 #endif
55 #ifndef PTRACE_SET_DEBUGREG
56 #define PTRACE_SET_DEBUGREG 26
57 #endif
58 #ifndef PTRACE_GETSIGINFO
59 #define PTRACE_GETSIGINFO 0x4202
60 #endif
61
62 /* These requests are used when the PowerPC HWDEBUG ptrace interface is
63 available. It exposes the debug facilities of PowerPC processors, as well
64 as additional features of BookE processors, such as ranged breakpoints and
65 watchpoints and hardware-accelerated condition evaluation. */
66 #ifndef PPC_PTRACE_GETHWDBGINFO
67
68 /* Not having PPC_PTRACE_GETHWDBGINFO defined means that the PowerPC HWDEBUG
69 ptrace interface is not present in ptrace.h, so we'll have to pretty much
70 include it all here so that the code at least compiles on older systems. */
71 #define PPC_PTRACE_GETHWDBGINFO 0x89
72 #define PPC_PTRACE_SETHWDEBUG 0x88
73 #define PPC_PTRACE_DELHWDEBUG 0x87
74
75 struct ppc_debug_info
76 {
77 uint32_t version; /* Only version 1 exists to date. */
78 uint32_t num_instruction_bps;
79 uint32_t num_data_bps;
80 uint32_t num_condition_regs;
81 uint32_t data_bp_alignment;
82 uint32_t sizeof_condition; /* size of the DVC register. */
83 uint64_t features;
84 };
85
86 /* Features will have bits indicating whether there is support for: */
87 #define PPC_DEBUG_FEATURE_INSN_BP_RANGE 0x1
88 #define PPC_DEBUG_FEATURE_INSN_BP_MASK 0x2
89 #define PPC_DEBUG_FEATURE_DATA_BP_RANGE 0x4
90 #define PPC_DEBUG_FEATURE_DATA_BP_MASK 0x8
91
92 struct ppc_hw_breakpoint
93 {
94 uint32_t version; /* currently, version must be 1 */
95 uint32_t trigger_type; /* only some combinations allowed */
96 uint32_t addr_mode; /* address match mode */
97 uint32_t condition_mode; /* break/watchpoint condition flags */
98 uint64_t addr; /* break/watchpoint address */
99 uint64_t addr2; /* range end or mask */
100 uint64_t condition_value; /* contents of the DVC register */
101 };
102
103 /* Trigger type. */
104 #define PPC_BREAKPOINT_TRIGGER_EXECUTE 0x1
105 #define PPC_BREAKPOINT_TRIGGER_READ 0x2
106 #define PPC_BREAKPOINT_TRIGGER_WRITE 0x4
107 #define PPC_BREAKPOINT_TRIGGER_RW 0x6
108
109 /* Address mode. */
110 #define PPC_BREAKPOINT_MODE_EXACT 0x0
111 #define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE 0x1
112 #define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE 0x2
113 #define PPC_BREAKPOINT_MODE_MASK 0x3
114
115 /* Condition mode. */
116 #define PPC_BREAKPOINT_CONDITION_NONE 0x0
117 #define PPC_BREAKPOINT_CONDITION_AND 0x1
118 #define PPC_BREAKPOINT_CONDITION_EXACT 0x1
119 #define PPC_BREAKPOINT_CONDITION_OR 0x2
120 #define PPC_BREAKPOINT_CONDITION_AND_OR 0x3
121 #define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000
122 #define PPC_BREAKPOINT_CONDITION_BE_SHIFT 16
123 #define PPC_BREAKPOINT_CONDITION_BE(n) \
124 (1<<((n)+PPC_BREAKPOINT_CONDITION_BE_SHIFT))
125 #endif /* PPC_PTRACE_GETHWDBGINFO */
126
127 /* Feature defined on Linux kernel v3.9: DAWR interface, that enables wider
128 watchpoint (up to 512 bytes). */
129 #ifndef PPC_DEBUG_FEATURE_DATA_BP_DAWR
130 #define PPC_DEBUG_FEATURE_DATA_BP_DAWR 0x10
131 #endif /* PPC_DEBUG_FEATURE_DATA_BP_DAWR */
132
133 /* Similarly for the general-purpose (gp0 -- gp31)
134 and floating-point registers (fp0 -- fp31). */
135 #ifndef PTRACE_GETREGS
136 #define PTRACE_GETREGS 12
137 #endif
138 #ifndef PTRACE_SETREGS
139 #define PTRACE_SETREGS 13
140 #endif
141 #ifndef PTRACE_GETFPREGS
142 #define PTRACE_GETFPREGS 14
143 #endif
144 #ifndef PTRACE_SETFPREGS
145 #define PTRACE_SETFPREGS 15
146 #endif
147
148 /* This oddity is because the Linux kernel defines elf_vrregset_t as
149 an array of 33 16 bytes long elements. I.e. it leaves out vrsave.
150 However the PTRACE_GETVRREGS and PTRACE_SETVRREGS requests return
151 the vrsave as an extra 4 bytes at the end. I opted for creating a
152 flat array of chars, so that it is easier to manipulate for gdb.
153
154 There are 32 vector registers 16 bytes longs, plus a VSCR register
155 which is only 4 bytes long, but is fetched as a 16 bytes
156 quantity. Up to here we have the elf_vrregset_t structure.
157 Appended to this there is space for the VRSAVE register: 4 bytes.
158 Even though this vrsave register is not included in the regset
159 typedef, it is handled by the ptrace requests.
160
161 Note that GNU/Linux doesn't support little endian PPC hardware,
162 therefore the offset at which the real value of the VSCR register
163 is located will be always 12 bytes.
164
165 The layout is like this (where x is the actual value of the vscr reg): */
166
167 /* *INDENT-OFF* */
168 /*
169 |.|.|.|.|.....|.|.|.|.||.|.|.|x||.|
170 <-------> <-------><-------><->
171 VR0 VR31 VSCR VRSAVE
172 */
173 /* *INDENT-ON* */
174
175 #define SIZEOF_VRREGS 33*16+4
176
177 typedef char gdb_vrregset_t[SIZEOF_VRREGS];
178
179 /* This is the layout of the POWER7 VSX registers and the way they overlap
180 with the existing FPR and VMX registers.
181
182 VSR doubleword 0 VSR doubleword 1
183 ----------------------------------------------------------------
184 VSR[0] | FPR[0] | |
185 ----------------------------------------------------------------
186 VSR[1] | FPR[1] | |
187 ----------------------------------------------------------------
188 | ... | |
189 | ... | |
190 ----------------------------------------------------------------
191 VSR[30] | FPR[30] | |
192 ----------------------------------------------------------------
193 VSR[31] | FPR[31] | |
194 ----------------------------------------------------------------
195 VSR[32] | VR[0] |
196 ----------------------------------------------------------------
197 VSR[33] | VR[1] |
198 ----------------------------------------------------------------
199 | ... |
200 | ... |
201 ----------------------------------------------------------------
202 VSR[62] | VR[30] |
203 ----------------------------------------------------------------
204 VSR[63] | VR[31] |
205 ----------------------------------------------------------------
206
207 VSX has 64 128bit registers. The first 32 registers overlap with
208 the FP registers (doubleword 0) and hence extend them with additional
209 64 bits (doubleword 1). The other 32 regs overlap with the VMX
210 registers. */
211 #define SIZEOF_VSXREGS 32*8
212
213 typedef char gdb_vsxregset_t[SIZEOF_VSXREGS];
214
215 /* On PPC processors that support the Signal Processing Extension
216 (SPE) APU, the general-purpose registers are 64 bits long.
217 However, the ordinary Linux kernel PTRACE_PEEKUSER / PTRACE_POKEUSER
218 ptrace calls only access the lower half of each register, to allow
219 them to behave the same way they do on non-SPE systems. There's a
220 separate pair of calls, PTRACE_GETEVRREGS / PTRACE_SETEVRREGS, that
221 read and write the top halves of all the general-purpose registers
222 at once, along with some SPE-specific registers.
223
224 GDB itself continues to claim the general-purpose registers are 32
225 bits long. It has unnamed raw registers that hold the upper halves
226 of the gprs, and the full 64-bit SIMD views of the registers,
227 'ev0' -- 'ev31', are pseudo-registers that splice the top and
228 bottom halves together.
229
230 This is the structure filled in by PTRACE_GETEVRREGS and written to
231 the inferior's registers by PTRACE_SETEVRREGS. */
232 struct gdb_evrregset_t
233 {
234 unsigned long evr[32];
235 unsigned long long acc;
236 unsigned long spefscr;
237 };
238
239 /* Non-zero if our kernel may support the PTRACE_GETVSXREGS and
240 PTRACE_SETVSXREGS requests, for reading and writing the VSX
241 POWER7 registers 0 through 31. Zero if we've tried one of them and
242 gotten an error. Note that VSX registers 32 through 63 overlap
243 with VR registers 0 through 31. */
244 int have_ptrace_getsetvsxregs = 1;
245
246 /* Non-zero if our kernel may support the PTRACE_GETVRREGS and
247 PTRACE_SETVRREGS requests, for reading and writing the Altivec
248 registers. Zero if we've tried one of them and gotten an
249 error. */
250 int have_ptrace_getvrregs = 1;
251
252 /* Non-zero if our kernel may support the PTRACE_GETEVRREGS and
253 PTRACE_SETEVRREGS requests, for reading and writing the SPE
254 registers. Zero if we've tried one of them and gotten an
255 error. */
256 int have_ptrace_getsetevrregs = 1;
257
258 /* Non-zero if our kernel may support the PTRACE_GETREGS and
259 PTRACE_SETREGS requests, for reading and writing the
260 general-purpose registers. Zero if we've tried one of
261 them and gotten an error. */
262 int have_ptrace_getsetregs = 1;
263
264 /* Non-zero if our kernel may support the PTRACE_GETFPREGS and
265 PTRACE_SETFPREGS requests, for reading and writing the
266 floating-pointers registers. Zero if we've tried one of
267 them and gotten an error. */
268 int have_ptrace_getsetfpregs = 1;
269
270 /* *INDENT-OFF* */
271 /* registers layout, as presented by the ptrace interface:
272 PT_R0, PT_R1, PT_R2, PT_R3, PT_R4, PT_R5, PT_R6, PT_R7,
273 PT_R8, PT_R9, PT_R10, PT_R11, PT_R12, PT_R13, PT_R14, PT_R15,
274 PT_R16, PT_R17, PT_R18, PT_R19, PT_R20, PT_R21, PT_R22, PT_R23,
275 PT_R24, PT_R25, PT_R26, PT_R27, PT_R28, PT_R29, PT_R30, PT_R31,
276 PT_FPR0, PT_FPR0 + 2, PT_FPR0 + 4, PT_FPR0 + 6,
277 PT_FPR0 + 8, PT_FPR0 + 10, PT_FPR0 + 12, PT_FPR0 + 14,
278 PT_FPR0 + 16, PT_FPR0 + 18, PT_FPR0 + 20, PT_FPR0 + 22,
279 PT_FPR0 + 24, PT_FPR0 + 26, PT_FPR0 + 28, PT_FPR0 + 30,
280 PT_FPR0 + 32, PT_FPR0 + 34, PT_FPR0 + 36, PT_FPR0 + 38,
281 PT_FPR0 + 40, PT_FPR0 + 42, PT_FPR0 + 44, PT_FPR0 + 46,
282 PT_FPR0 + 48, PT_FPR0 + 50, PT_FPR0 + 52, PT_FPR0 + 54,
283 PT_FPR0 + 56, PT_FPR0 + 58, PT_FPR0 + 60, PT_FPR0 + 62,
284 PT_NIP, PT_MSR, PT_CCR, PT_LNK, PT_CTR, PT_XER, PT_MQ */
285 /* *INDENT_ON * */
286
287 static int
288 ppc_register_u_addr (struct gdbarch *gdbarch, int regno)
289 {
290 int u_addr = -1;
291 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
292 /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace
293 interface, and not the wordsize of the program's ABI. */
294 int wordsize = sizeof (long);
295
296 /* General purpose registers occupy 1 slot each in the buffer. */
297 if (regno >= tdep->ppc_gp0_regnum
298 && regno < tdep->ppc_gp0_regnum + ppc_num_gprs)
299 u_addr = ((regno - tdep->ppc_gp0_regnum + PT_R0) * wordsize);
300
301 /* Floating point regs: eight bytes each in both 32- and 64-bit
302 ptrace interfaces. Thus, two slots each in 32-bit interface, one
303 slot each in 64-bit interface. */
304 if (tdep->ppc_fp0_regnum >= 0
305 && regno >= tdep->ppc_fp0_regnum
306 && regno < tdep->ppc_fp0_regnum + ppc_num_fprs)
307 u_addr = (PT_FPR0 * wordsize) + ((regno - tdep->ppc_fp0_regnum) * 8);
308
309 /* UISA special purpose registers: 1 slot each. */
310 if (regno == gdbarch_pc_regnum (gdbarch))
311 u_addr = PT_NIP * wordsize;
312 if (regno == tdep->ppc_lr_regnum)
313 u_addr = PT_LNK * wordsize;
314 if (regno == tdep->ppc_cr_regnum)
315 u_addr = PT_CCR * wordsize;
316 if (regno == tdep->ppc_xer_regnum)
317 u_addr = PT_XER * wordsize;
318 if (regno == tdep->ppc_ctr_regnum)
319 u_addr = PT_CTR * wordsize;
320 #ifdef PT_MQ
321 if (regno == tdep->ppc_mq_regnum)
322 u_addr = PT_MQ * wordsize;
323 #endif
324 if (regno == tdep->ppc_ps_regnum)
325 u_addr = PT_MSR * wordsize;
326 if (regno == PPC_ORIG_R3_REGNUM)
327 u_addr = PT_ORIG_R3 * wordsize;
328 if (regno == PPC_TRAP_REGNUM)
329 u_addr = PT_TRAP * wordsize;
330 if (tdep->ppc_fpscr_regnum >= 0
331 && regno == tdep->ppc_fpscr_regnum)
332 {
333 /* NOTE: cagney/2005-02-08: On some 64-bit GNU/Linux systems the
334 kernel headers incorrectly contained the 32-bit definition of
335 PT_FPSCR. For the 32-bit definition, floating-point
336 registers occupy two 32-bit "slots", and the FPSCR lives in
337 the second half of such a slot-pair (hence +1). For 64-bit,
338 the FPSCR instead occupies the full 64-bit 2-word-slot and
339 hence no adjustment is necessary. Hack around this. */
340 if (wordsize == 8 && PT_FPSCR == (48 + 32 + 1))
341 u_addr = (48 + 32) * wordsize;
342 /* If the FPSCR is 64-bit wide, we need to fetch the whole 64-bit
343 slot and not just its second word. The PT_FPSCR supplied when
344 GDB is compiled as a 32-bit app doesn't reflect this. */
345 else if (wordsize == 4 && register_size (gdbarch, regno) == 8
346 && PT_FPSCR == (48 + 2*32 + 1))
347 u_addr = (48 + 2*32) * wordsize;
348 else
349 u_addr = PT_FPSCR * wordsize;
350 }
351 return u_addr;
352 }
353
354 /* The Linux kernel ptrace interface for POWER7 VSX registers uses the
355 registers set mechanism, as opposed to the interface for all the
356 other registers, that stores/fetches each register individually. */
357 static void
358 fetch_vsx_register (struct regcache *regcache, int tid, int regno)
359 {
360 int ret;
361 gdb_vsxregset_t regs;
362 struct gdbarch *gdbarch = regcache->arch ();
363 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
364 int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum);
365
366 ret = ptrace (PTRACE_GETVSXREGS, tid, 0, &regs);
367 if (ret < 0)
368 {
369 if (errno == EIO)
370 {
371 have_ptrace_getsetvsxregs = 0;
372 return;
373 }
374 perror_with_name (_("Unable to fetch VSX register"));
375 }
376
377 regcache_raw_supply (regcache, regno,
378 regs + (regno - tdep->ppc_vsr0_upper_regnum)
379 * vsxregsize);
380 }
381
382 /* The Linux kernel ptrace interface for AltiVec registers uses the
383 registers set mechanism, as opposed to the interface for all the
384 other registers, that stores/fetches each register individually. */
385 static void
386 fetch_altivec_register (struct regcache *regcache, int tid, int regno)
387 {
388 int ret;
389 int offset = 0;
390 gdb_vrregset_t regs;
391 struct gdbarch *gdbarch = regcache->arch ();
392 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
393 int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum);
394
395 ret = ptrace (PTRACE_GETVRREGS, tid, 0, &regs);
396 if (ret < 0)
397 {
398 if (errno == EIO)
399 {
400 have_ptrace_getvrregs = 0;
401 return;
402 }
403 perror_with_name (_("Unable to fetch AltiVec register"));
404 }
405
406 /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes
407 long on the hardware. We deal only with the lower 4 bytes of the
408 vector. VRSAVE is at the end of the array in a 4 bytes slot, so
409 there is no need to define an offset for it. */
410 if (regno == (tdep->ppc_vrsave_regnum - 1))
411 offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum);
412
413 regcache_raw_supply (regcache, regno,
414 regs + (regno
415 - tdep->ppc_vr0_regnum) * vrregsize + offset);
416 }
417
418 /* Fetch the top 32 bits of TID's general-purpose registers and the
419 SPE-specific registers, and place the results in EVRREGSET. If we
420 don't support PTRACE_GETEVRREGS, then just fill EVRREGSET with
421 zeros.
422
423 All the logic to deal with whether or not the PTRACE_GETEVRREGS and
424 PTRACE_SETEVRREGS requests are supported is isolated here, and in
425 set_spe_registers. */
426 static void
427 get_spe_registers (int tid, struct gdb_evrregset_t *evrregset)
428 {
429 if (have_ptrace_getsetevrregs)
430 {
431 if (ptrace (PTRACE_GETEVRREGS, tid, 0, evrregset) >= 0)
432 return;
433 else
434 {
435 /* EIO means that the PTRACE_GETEVRREGS request isn't supported;
436 we just return zeros. */
437 if (errno == EIO)
438 have_ptrace_getsetevrregs = 0;
439 else
440 /* Anything else needs to be reported. */
441 perror_with_name (_("Unable to fetch SPE registers"));
442 }
443 }
444
445 memset (evrregset, 0, sizeof (*evrregset));
446 }
447
448 /* Supply values from TID for SPE-specific raw registers: the upper
449 halves of the GPRs, the accumulator, and the spefscr. REGNO must
450 be the number of an upper half register, acc, spefscr, or -1 to
451 supply the values of all registers. */
452 static void
453 fetch_spe_register (struct regcache *regcache, int tid, int regno)
454 {
455 struct gdbarch *gdbarch = regcache->arch ();
456 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
457 struct gdb_evrregset_t evrregs;
458
459 gdb_assert (sizeof (evrregs.evr[0])
460 == register_size (gdbarch, tdep->ppc_ev0_upper_regnum));
461 gdb_assert (sizeof (evrregs.acc)
462 == register_size (gdbarch, tdep->ppc_acc_regnum));
463 gdb_assert (sizeof (evrregs.spefscr)
464 == register_size (gdbarch, tdep->ppc_spefscr_regnum));
465
466 get_spe_registers (tid, &evrregs);
467
468 if (regno == -1)
469 {
470 int i;
471
472 for (i = 0; i < ppc_num_gprs; i++)
473 regcache_raw_supply (regcache, tdep->ppc_ev0_upper_regnum + i,
474 &evrregs.evr[i]);
475 }
476 else if (tdep->ppc_ev0_upper_regnum <= regno
477 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
478 regcache_raw_supply (regcache, regno,
479 &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]);
480
481 if (regno == -1
482 || regno == tdep->ppc_acc_regnum)
483 regcache_raw_supply (regcache, tdep->ppc_acc_regnum, &evrregs.acc);
484
485 if (regno == -1
486 || regno == tdep->ppc_spefscr_regnum)
487 regcache_raw_supply (regcache, tdep->ppc_spefscr_regnum,
488 &evrregs.spefscr);
489 }
490
491 static void
492 fetch_register (struct regcache *regcache, int tid, int regno)
493 {
494 struct gdbarch *gdbarch = regcache->arch ();
495 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
496 /* This isn't really an address. But ptrace thinks of it as one. */
497 CORE_ADDR regaddr = ppc_register_u_addr (gdbarch, regno);
498 int bytes_transferred;
499 unsigned int offset; /* Offset of registers within the u area. */
500 gdb_byte buf[PPC_MAX_REGISTER_SIZE];
501
502 if (altivec_register_p (gdbarch, regno))
503 {
504 /* If this is the first time through, or if it is not the first
505 time through, and we have comfirmed that there is kernel
506 support for such a ptrace request, then go and fetch the
507 register. */
508 if (have_ptrace_getvrregs)
509 {
510 fetch_altivec_register (regcache, tid, regno);
511 return;
512 }
513 /* If we have discovered that there is no ptrace support for
514 AltiVec registers, fall through and return zeroes, because
515 regaddr will be -1 in this case. */
516 }
517 if (vsx_register_p (gdbarch, regno))
518 {
519 if (have_ptrace_getsetvsxregs)
520 {
521 fetch_vsx_register (regcache, tid, regno);
522 return;
523 }
524 }
525 else if (spe_register_p (gdbarch, regno))
526 {
527 fetch_spe_register (regcache, tid, regno);
528 return;
529 }
530
531 if (regaddr == -1)
532 {
533 memset (buf, '\0', register_size (gdbarch, regno)); /* Supply zeroes */
534 regcache_raw_supply (regcache, regno, buf);
535 return;
536 }
537
538 /* Read the raw register using sizeof(long) sized chunks. On a
539 32-bit platform, 64-bit floating-point registers will require two
540 transfers. */
541 for (bytes_transferred = 0;
542 bytes_transferred < register_size (gdbarch, regno);
543 bytes_transferred += sizeof (long))
544 {
545 long l;
546
547 errno = 0;
548 l = ptrace (PTRACE_PEEKUSER, tid, (PTRACE_TYPE_ARG3) regaddr, 0);
549 regaddr += sizeof (long);
550 if (errno != 0)
551 {
552 char message[128];
553 xsnprintf (message, sizeof (message), "reading register %s (#%d)",
554 gdbarch_register_name (gdbarch, regno), regno);
555 perror_with_name (message);
556 }
557 memcpy (&buf[bytes_transferred], &l, sizeof (l));
558 }
559
560 /* Now supply the register. Keep in mind that the regcache's idea
561 of the register's size may not be a multiple of sizeof
562 (long). */
563 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
564 {
565 /* Little-endian values are always found at the left end of the
566 bytes transferred. */
567 regcache_raw_supply (regcache, regno, buf);
568 }
569 else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
570 {
571 /* Big-endian values are found at the right end of the bytes
572 transferred. */
573 size_t padding = (bytes_transferred - register_size (gdbarch, regno));
574 regcache_raw_supply (regcache, regno, buf + padding);
575 }
576 else
577 internal_error (__FILE__, __LINE__,
578 _("fetch_register: unexpected byte order: %d"),
579 gdbarch_byte_order (gdbarch));
580 }
581
582 static void
583 supply_vsxregset (struct regcache *regcache, gdb_vsxregset_t *vsxregsetp)
584 {
585 int i;
586 struct gdbarch *gdbarch = regcache->arch ();
587 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
588 int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum);
589
590 for (i = 0; i < ppc_num_vshrs; i++)
591 {
592 regcache_raw_supply (regcache, tdep->ppc_vsr0_upper_regnum + i,
593 *vsxregsetp + i * vsxregsize);
594 }
595 }
596
597 static void
598 supply_vrregset (struct regcache *regcache, gdb_vrregset_t *vrregsetp)
599 {
600 int i;
601 struct gdbarch *gdbarch = regcache->arch ();
602 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
603 int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1;
604 int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum);
605 int offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum);
606
607 for (i = 0; i < num_of_vrregs; i++)
608 {
609 /* The last 2 registers of this set are only 32 bit long, not
610 128. However an offset is necessary only for VSCR because it
611 occupies a whole vector, while VRSAVE occupies a full 4 bytes
612 slot. */
613 if (i == (num_of_vrregs - 2))
614 regcache_raw_supply (regcache, tdep->ppc_vr0_regnum + i,
615 *vrregsetp + i * vrregsize + offset);
616 else
617 regcache_raw_supply (regcache, tdep->ppc_vr0_regnum + i,
618 *vrregsetp + i * vrregsize);
619 }
620 }
621
622 static void
623 fetch_vsx_registers (struct regcache *regcache, int tid)
624 {
625 int ret;
626 gdb_vsxregset_t regs;
627
628 ret = ptrace (PTRACE_GETVSXREGS, tid, 0, &regs);
629 if (ret < 0)
630 {
631 if (errno == EIO)
632 {
633 have_ptrace_getsetvsxregs = 0;
634 return;
635 }
636 perror_with_name (_("Unable to fetch VSX registers"));
637 }
638 supply_vsxregset (regcache, &regs);
639 }
640
641 static void
642 fetch_altivec_registers (struct regcache *regcache, int tid)
643 {
644 int ret;
645 gdb_vrregset_t regs;
646
647 ret = ptrace (PTRACE_GETVRREGS, tid, 0, &regs);
648 if (ret < 0)
649 {
650 if (errno == EIO)
651 {
652 have_ptrace_getvrregs = 0;
653 return;
654 }
655 perror_with_name (_("Unable to fetch AltiVec registers"));
656 }
657 supply_vrregset (regcache, &regs);
658 }
659
660 /* This function actually issues the request to ptrace, telling
661 it to get all general-purpose registers and put them into the
662 specified regset.
663
664 If the ptrace request does not exist, this function returns 0
665 and properly sets the have_ptrace_* flag. If the request fails,
666 this function calls perror_with_name. Otherwise, if the request
667 succeeds, then the regcache gets filled and 1 is returned. */
668 static int
669 fetch_all_gp_regs (struct regcache *regcache, int tid)
670 {
671 struct gdbarch *gdbarch = regcache->arch ();
672 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
673 gdb_gregset_t gregset;
674
675 if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0)
676 {
677 if (errno == EIO)
678 {
679 have_ptrace_getsetregs = 0;
680 return 0;
681 }
682 perror_with_name (_("Couldn't get general-purpose registers."));
683 }
684
685 supply_gregset (regcache, (const gdb_gregset_t *) &gregset);
686
687 return 1;
688 }
689
690 /* This is a wrapper for the fetch_all_gp_regs function. It is
691 responsible for verifying if this target has the ptrace request
692 that can be used to fetch all general-purpose registers at one
693 shot. If it doesn't, then we should fetch them using the
694 old-fashioned way, which is to iterate over the registers and
695 request them one by one. */
696 static void
697 fetch_gp_regs (struct regcache *regcache, int tid)
698 {
699 struct gdbarch *gdbarch = regcache->arch ();
700 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
701 int i;
702
703 if (have_ptrace_getsetregs)
704 if (fetch_all_gp_regs (regcache, tid))
705 return;
706
707 /* If we've hit this point, it doesn't really matter which
708 architecture we are using. We just need to read the
709 registers in the "old-fashioned way". */
710 for (i = 0; i < ppc_num_gprs; i++)
711 fetch_register (regcache, tid, tdep->ppc_gp0_regnum + i);
712 }
713
714 /* This function actually issues the request to ptrace, telling
715 it to get all floating-point registers and put them into the
716 specified regset.
717
718 If the ptrace request does not exist, this function returns 0
719 and properly sets the have_ptrace_* flag. If the request fails,
720 this function calls perror_with_name. Otherwise, if the request
721 succeeds, then the regcache gets filled and 1 is returned. */
722 static int
723 fetch_all_fp_regs (struct regcache *regcache, int tid)
724 {
725 gdb_fpregset_t fpregs;
726
727 if (ptrace (PTRACE_GETFPREGS, tid, 0, (void *) &fpregs) < 0)
728 {
729 if (errno == EIO)
730 {
731 have_ptrace_getsetfpregs = 0;
732 return 0;
733 }
734 perror_with_name (_("Couldn't get floating-point registers."));
735 }
736
737 supply_fpregset (regcache, (const gdb_fpregset_t *) &fpregs);
738
739 return 1;
740 }
741
742 /* This is a wrapper for the fetch_all_fp_regs function. It is
743 responsible for verifying if this target has the ptrace request
744 that can be used to fetch all floating-point registers at one
745 shot. If it doesn't, then we should fetch them using the
746 old-fashioned way, which is to iterate over the registers and
747 request them one by one. */
748 static void
749 fetch_fp_regs (struct regcache *regcache, int tid)
750 {
751 struct gdbarch *gdbarch = regcache->arch ();
752 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
753 int i;
754
755 if (have_ptrace_getsetfpregs)
756 if (fetch_all_fp_regs (regcache, tid))
757 return;
758
759 /* If we've hit this point, it doesn't really matter which
760 architecture we are using. We just need to read the
761 registers in the "old-fashioned way". */
762 for (i = 0; i < ppc_num_fprs; i++)
763 fetch_register (regcache, tid, tdep->ppc_fp0_regnum + i);
764 }
765
766 static void
767 fetch_ppc_registers (struct regcache *regcache, int tid)
768 {
769 int i;
770 struct gdbarch *gdbarch = regcache->arch ();
771 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
772
773 fetch_gp_regs (regcache, tid);
774 if (tdep->ppc_fp0_regnum >= 0)
775 fetch_fp_regs (regcache, tid);
776 fetch_register (regcache, tid, gdbarch_pc_regnum (gdbarch));
777 if (tdep->ppc_ps_regnum != -1)
778 fetch_register (regcache, tid, tdep->ppc_ps_regnum);
779 if (tdep->ppc_cr_regnum != -1)
780 fetch_register (regcache, tid, tdep->ppc_cr_regnum);
781 if (tdep->ppc_lr_regnum != -1)
782 fetch_register (regcache, tid, tdep->ppc_lr_regnum);
783 if (tdep->ppc_ctr_regnum != -1)
784 fetch_register (regcache, tid, tdep->ppc_ctr_regnum);
785 if (tdep->ppc_xer_regnum != -1)
786 fetch_register (regcache, tid, tdep->ppc_xer_regnum);
787 if (tdep->ppc_mq_regnum != -1)
788 fetch_register (regcache, tid, tdep->ppc_mq_regnum);
789 if (ppc_linux_trap_reg_p (gdbarch))
790 {
791 fetch_register (regcache, tid, PPC_ORIG_R3_REGNUM);
792 fetch_register (regcache, tid, PPC_TRAP_REGNUM);
793 }
794 if (tdep->ppc_fpscr_regnum != -1)
795 fetch_register (regcache, tid, tdep->ppc_fpscr_regnum);
796 if (have_ptrace_getvrregs)
797 if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
798 fetch_altivec_registers (regcache, tid);
799 if (have_ptrace_getsetvsxregs)
800 if (tdep->ppc_vsr0_upper_regnum != -1)
801 fetch_vsx_registers (regcache, tid);
802 if (tdep->ppc_ev0_upper_regnum >= 0)
803 fetch_spe_register (regcache, tid, -1);
804 }
805
806 /* Fetch registers from the child process. Fetch all registers if
807 regno == -1, otherwise fetch all general registers or all floating
808 point registers depending upon the value of regno. */
809 static void
810 ppc_linux_fetch_inferior_registers (struct target_ops *ops,
811 struct regcache *regcache, int regno)
812 {
813 pid_t tid = get_ptrace_pid (regcache_get_ptid (regcache));
814
815 if (regno == -1)
816 fetch_ppc_registers (regcache, tid);
817 else
818 fetch_register (regcache, tid, regno);
819 }
820
821 /* Store one VSX register. */
822 static void
823 store_vsx_register (const struct regcache *regcache, int tid, int regno)
824 {
825 int ret;
826 gdb_vsxregset_t regs;
827 struct gdbarch *gdbarch = regcache->arch ();
828 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
829 int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum);
830
831 ret = ptrace (PTRACE_GETVSXREGS, tid, 0, &regs);
832 if (ret < 0)
833 {
834 if (errno == EIO)
835 {
836 have_ptrace_getsetvsxregs = 0;
837 return;
838 }
839 perror_with_name (_("Unable to fetch VSX register"));
840 }
841
842 regcache_raw_collect (regcache, regno, regs +
843 (regno - tdep->ppc_vsr0_upper_regnum) * vsxregsize);
844
845 ret = ptrace (PTRACE_SETVSXREGS, tid, 0, &regs);
846 if (ret < 0)
847 perror_with_name (_("Unable to store VSX register"));
848 }
849
850 /* Store one register. */
851 static void
852 store_altivec_register (const struct regcache *regcache, int tid, int regno)
853 {
854 int ret;
855 int offset = 0;
856 gdb_vrregset_t regs;
857 struct gdbarch *gdbarch = regcache->arch ();
858 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
859 int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum);
860
861 ret = ptrace (PTRACE_GETVRREGS, tid, 0, &regs);
862 if (ret < 0)
863 {
864 if (errno == EIO)
865 {
866 have_ptrace_getvrregs = 0;
867 return;
868 }
869 perror_with_name (_("Unable to fetch AltiVec register"));
870 }
871
872 /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes
873 long on the hardware. */
874 if (regno == (tdep->ppc_vrsave_regnum - 1))
875 offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum);
876
877 regcache_raw_collect (regcache, regno,
878 regs + (regno
879 - tdep->ppc_vr0_regnum) * vrregsize + offset);
880
881 ret = ptrace (PTRACE_SETVRREGS, tid, 0, &regs);
882 if (ret < 0)
883 perror_with_name (_("Unable to store AltiVec register"));
884 }
885
886 /* Assuming TID referrs to an SPE process, set the top halves of TID's
887 general-purpose registers and its SPE-specific registers to the
888 values in EVRREGSET. If we don't support PTRACE_SETEVRREGS, do
889 nothing.
890
891 All the logic to deal with whether or not the PTRACE_GETEVRREGS and
892 PTRACE_SETEVRREGS requests are supported is isolated here, and in
893 get_spe_registers. */
894 static void
895 set_spe_registers (int tid, struct gdb_evrregset_t *evrregset)
896 {
897 if (have_ptrace_getsetevrregs)
898 {
899 if (ptrace (PTRACE_SETEVRREGS, tid, 0, evrregset) >= 0)
900 return;
901 else
902 {
903 /* EIO means that the PTRACE_SETEVRREGS request isn't
904 supported; we fail silently, and don't try the call
905 again. */
906 if (errno == EIO)
907 have_ptrace_getsetevrregs = 0;
908 else
909 /* Anything else needs to be reported. */
910 perror_with_name (_("Unable to set SPE registers"));
911 }
912 }
913 }
914
915 /* Write GDB's value for the SPE-specific raw register REGNO to TID.
916 If REGNO is -1, write the values of all the SPE-specific
917 registers. */
918 static void
919 store_spe_register (const struct regcache *regcache, int tid, int regno)
920 {
921 struct gdbarch *gdbarch = regcache->arch ();
922 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
923 struct gdb_evrregset_t evrregs;
924
925 gdb_assert (sizeof (evrregs.evr[0])
926 == register_size (gdbarch, tdep->ppc_ev0_upper_regnum));
927 gdb_assert (sizeof (evrregs.acc)
928 == register_size (gdbarch, tdep->ppc_acc_regnum));
929 gdb_assert (sizeof (evrregs.spefscr)
930 == register_size (gdbarch, tdep->ppc_spefscr_regnum));
931
932 if (regno == -1)
933 /* Since we're going to write out every register, the code below
934 should store to every field of evrregs; if that doesn't happen,
935 make it obvious by initializing it with suspicious values. */
936 memset (&evrregs, 42, sizeof (evrregs));
937 else
938 /* We can only read and write the entire EVR register set at a
939 time, so to write just a single register, we do a
940 read-modify-write maneuver. */
941 get_spe_registers (tid, &evrregs);
942
943 if (regno == -1)
944 {
945 int i;
946
947 for (i = 0; i < ppc_num_gprs; i++)
948 regcache_raw_collect (regcache,
949 tdep->ppc_ev0_upper_regnum + i,
950 &evrregs.evr[i]);
951 }
952 else if (tdep->ppc_ev0_upper_regnum <= regno
953 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
954 regcache_raw_collect (regcache, regno,
955 &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]);
956
957 if (regno == -1
958 || regno == tdep->ppc_acc_regnum)
959 regcache_raw_collect (regcache,
960 tdep->ppc_acc_regnum,
961 &evrregs.acc);
962
963 if (regno == -1
964 || regno == tdep->ppc_spefscr_regnum)
965 regcache_raw_collect (regcache,
966 tdep->ppc_spefscr_regnum,
967 &evrregs.spefscr);
968
969 /* Write back the modified register set. */
970 set_spe_registers (tid, &evrregs);
971 }
972
973 static void
974 store_register (const struct regcache *regcache, int tid, int regno)
975 {
976 struct gdbarch *gdbarch = regcache->arch ();
977 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
978 /* This isn't really an address. But ptrace thinks of it as one. */
979 CORE_ADDR regaddr = ppc_register_u_addr (gdbarch, regno);
980 int i;
981 size_t bytes_to_transfer;
982 gdb_byte buf[PPC_MAX_REGISTER_SIZE];
983
984 if (altivec_register_p (gdbarch, regno))
985 {
986 store_altivec_register (regcache, tid, regno);
987 return;
988 }
989 if (vsx_register_p (gdbarch, regno))
990 {
991 store_vsx_register (regcache, tid, regno);
992 return;
993 }
994 else if (spe_register_p (gdbarch, regno))
995 {
996 store_spe_register (regcache, tid, regno);
997 return;
998 }
999
1000 if (regaddr == -1)
1001 return;
1002
1003 /* First collect the register. Keep in mind that the regcache's
1004 idea of the register's size may not be a multiple of sizeof
1005 (long). */
1006 memset (buf, 0, sizeof buf);
1007 bytes_to_transfer = align_up (register_size (gdbarch, regno), sizeof (long));
1008 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
1009 {
1010 /* Little-endian values always sit at the left end of the buffer. */
1011 regcache_raw_collect (regcache, regno, buf);
1012 }
1013 else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1014 {
1015 /* Big-endian values sit at the right end of the buffer. */
1016 size_t padding = (bytes_to_transfer - register_size (gdbarch, regno));
1017 regcache_raw_collect (regcache, regno, buf + padding);
1018 }
1019
1020 for (i = 0; i < bytes_to_transfer; i += sizeof (long))
1021 {
1022 long l;
1023
1024 memcpy (&l, &buf[i], sizeof (l));
1025 errno = 0;
1026 ptrace (PTRACE_POKEUSER, tid, (PTRACE_TYPE_ARG3) regaddr, l);
1027 regaddr += sizeof (long);
1028
1029 if (errno == EIO
1030 && (regno == tdep->ppc_fpscr_regnum
1031 || regno == PPC_ORIG_R3_REGNUM
1032 || regno == PPC_TRAP_REGNUM))
1033 {
1034 /* Some older kernel versions don't allow fpscr, orig_r3
1035 or trap to be written. */
1036 continue;
1037 }
1038
1039 if (errno != 0)
1040 {
1041 char message[128];
1042 xsnprintf (message, sizeof (message), "writing register %s (#%d)",
1043 gdbarch_register_name (gdbarch, regno), regno);
1044 perror_with_name (message);
1045 }
1046 }
1047 }
1048
1049 static void
1050 fill_vsxregset (const struct regcache *regcache, gdb_vsxregset_t *vsxregsetp)
1051 {
1052 int i;
1053 struct gdbarch *gdbarch = regcache->arch ();
1054 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1055 int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum);
1056
1057 for (i = 0; i < ppc_num_vshrs; i++)
1058 regcache_raw_collect (regcache, tdep->ppc_vsr0_upper_regnum + i,
1059 *vsxregsetp + i * vsxregsize);
1060 }
1061
1062 static void
1063 fill_vrregset (const struct regcache *regcache, gdb_vrregset_t *vrregsetp)
1064 {
1065 int i;
1066 struct gdbarch *gdbarch = regcache->arch ();
1067 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1068 int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1;
1069 int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum);
1070 int offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum);
1071
1072 for (i = 0; i < num_of_vrregs; i++)
1073 {
1074 /* The last 2 registers of this set are only 32 bit long, not
1075 128, but only VSCR is fetched as a 16 bytes quantity. */
1076 if (i == (num_of_vrregs - 2))
1077 regcache_raw_collect (regcache, tdep->ppc_vr0_regnum + i,
1078 *vrregsetp + i * vrregsize + offset);
1079 else
1080 regcache_raw_collect (regcache, tdep->ppc_vr0_regnum + i,
1081 *vrregsetp + i * vrregsize);
1082 }
1083 }
1084
1085 static void
1086 store_vsx_registers (const struct regcache *regcache, int tid)
1087 {
1088 int ret;
1089 gdb_vsxregset_t regs;
1090
1091 ret = ptrace (PTRACE_GETVSXREGS, tid, 0, &regs);
1092 if (ret < 0)
1093 {
1094 if (errno == EIO)
1095 {
1096 have_ptrace_getsetvsxregs = 0;
1097 return;
1098 }
1099 perror_with_name (_("Couldn't get VSX registers"));
1100 }
1101
1102 fill_vsxregset (regcache, &regs);
1103
1104 if (ptrace (PTRACE_SETVSXREGS, tid, 0, &regs) < 0)
1105 perror_with_name (_("Couldn't write VSX registers"));
1106 }
1107
1108 static void
1109 store_altivec_registers (const struct regcache *regcache, int tid)
1110 {
1111 int ret;
1112 gdb_vrregset_t regs;
1113
1114 ret = ptrace (PTRACE_GETVRREGS, tid, 0, &regs);
1115 if (ret < 0)
1116 {
1117 if (errno == EIO)
1118 {
1119 have_ptrace_getvrregs = 0;
1120 return;
1121 }
1122 perror_with_name (_("Couldn't get AltiVec registers"));
1123 }
1124
1125 fill_vrregset (regcache, &regs);
1126
1127 if (ptrace (PTRACE_SETVRREGS, tid, 0, &regs) < 0)
1128 perror_with_name (_("Couldn't write AltiVec registers"));
1129 }
1130
1131 /* This function actually issues the request to ptrace, telling
1132 it to store all general-purpose registers present in the specified
1133 regset.
1134
1135 If the ptrace request does not exist, this function returns 0
1136 and properly sets the have_ptrace_* flag. If the request fails,
1137 this function calls perror_with_name. Otherwise, if the request
1138 succeeds, then the regcache is stored and 1 is returned. */
1139 static int
1140 store_all_gp_regs (const struct regcache *regcache, int tid, int regno)
1141 {
1142 struct gdbarch *gdbarch = regcache->arch ();
1143 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1144 gdb_gregset_t gregset;
1145
1146 if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0)
1147 {
1148 if (errno == EIO)
1149 {
1150 have_ptrace_getsetregs = 0;
1151 return 0;
1152 }
1153 perror_with_name (_("Couldn't get general-purpose registers."));
1154 }
1155
1156 fill_gregset (regcache, &gregset, regno);
1157
1158 if (ptrace (PTRACE_SETREGS, tid, 0, (void *) &gregset) < 0)
1159 {
1160 if (errno == EIO)
1161 {
1162 have_ptrace_getsetregs = 0;
1163 return 0;
1164 }
1165 perror_with_name (_("Couldn't set general-purpose registers."));
1166 }
1167
1168 return 1;
1169 }
1170
1171 /* This is a wrapper for the store_all_gp_regs function. It is
1172 responsible for verifying if this target has the ptrace request
1173 that can be used to store all general-purpose registers at one
1174 shot. If it doesn't, then we should store them using the
1175 old-fashioned way, which is to iterate over the registers and
1176 store them one by one. */
1177 static void
1178 store_gp_regs (const struct regcache *regcache, int tid, int regno)
1179 {
1180 struct gdbarch *gdbarch = regcache->arch ();
1181 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1182 int i;
1183
1184 if (have_ptrace_getsetregs)
1185 if (store_all_gp_regs (regcache, tid, regno))
1186 return;
1187
1188 /* If we hit this point, it doesn't really matter which
1189 architecture we are using. We just need to store the
1190 registers in the "old-fashioned way". */
1191 for (i = 0; i < ppc_num_gprs; i++)
1192 store_register (regcache, tid, tdep->ppc_gp0_regnum + i);
1193 }
1194
1195 /* This function actually issues the request to ptrace, telling
1196 it to store all floating-point registers present in the specified
1197 regset.
1198
1199 If the ptrace request does not exist, this function returns 0
1200 and properly sets the have_ptrace_* flag. If the request fails,
1201 this function calls perror_with_name. Otherwise, if the request
1202 succeeds, then the regcache is stored and 1 is returned. */
1203 static int
1204 store_all_fp_regs (const struct regcache *regcache, int tid, int regno)
1205 {
1206 gdb_fpregset_t fpregs;
1207
1208 if (ptrace (PTRACE_GETFPREGS, tid, 0, (void *) &fpregs) < 0)
1209 {
1210 if (errno == EIO)
1211 {
1212 have_ptrace_getsetfpregs = 0;
1213 return 0;
1214 }
1215 perror_with_name (_("Couldn't get floating-point registers."));
1216 }
1217
1218 fill_fpregset (regcache, &fpregs, regno);
1219
1220 if (ptrace (PTRACE_SETFPREGS, tid, 0, (void *) &fpregs) < 0)
1221 {
1222 if (errno == EIO)
1223 {
1224 have_ptrace_getsetfpregs = 0;
1225 return 0;
1226 }
1227 perror_with_name (_("Couldn't set floating-point registers."));
1228 }
1229
1230 return 1;
1231 }
1232
1233 /* This is a wrapper for the store_all_fp_regs function. It is
1234 responsible for verifying if this target has the ptrace request
1235 that can be used to store all floating-point registers at one
1236 shot. If it doesn't, then we should store them using the
1237 old-fashioned way, which is to iterate over the registers and
1238 store them one by one. */
1239 static void
1240 store_fp_regs (const struct regcache *regcache, int tid, int regno)
1241 {
1242 struct gdbarch *gdbarch = regcache->arch ();
1243 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1244 int i;
1245
1246 if (have_ptrace_getsetfpregs)
1247 if (store_all_fp_regs (regcache, tid, regno))
1248 return;
1249
1250 /* If we hit this point, it doesn't really matter which
1251 architecture we are using. We just need to store the
1252 registers in the "old-fashioned way". */
1253 for (i = 0; i < ppc_num_fprs; i++)
1254 store_register (regcache, tid, tdep->ppc_fp0_regnum + i);
1255 }
1256
1257 static void
1258 store_ppc_registers (const struct regcache *regcache, int tid)
1259 {
1260 int i;
1261 struct gdbarch *gdbarch = regcache->arch ();
1262 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1263
1264 store_gp_regs (regcache, tid, -1);
1265 if (tdep->ppc_fp0_regnum >= 0)
1266 store_fp_regs (regcache, tid, -1);
1267 store_register (regcache, tid, gdbarch_pc_regnum (gdbarch));
1268 if (tdep->ppc_ps_regnum != -1)
1269 store_register (regcache, tid, tdep->ppc_ps_regnum);
1270 if (tdep->ppc_cr_regnum != -1)
1271 store_register (regcache, tid, tdep->ppc_cr_regnum);
1272 if (tdep->ppc_lr_regnum != -1)
1273 store_register (regcache, tid, tdep->ppc_lr_regnum);
1274 if (tdep->ppc_ctr_regnum != -1)
1275 store_register (regcache, tid, tdep->ppc_ctr_regnum);
1276 if (tdep->ppc_xer_regnum != -1)
1277 store_register (regcache, tid, tdep->ppc_xer_regnum);
1278 if (tdep->ppc_mq_regnum != -1)
1279 store_register (regcache, tid, tdep->ppc_mq_regnum);
1280 if (tdep->ppc_fpscr_regnum != -1)
1281 store_register (regcache, tid, tdep->ppc_fpscr_regnum);
1282 if (ppc_linux_trap_reg_p (gdbarch))
1283 {
1284 store_register (regcache, tid, PPC_ORIG_R3_REGNUM);
1285 store_register (regcache, tid, PPC_TRAP_REGNUM);
1286 }
1287 if (have_ptrace_getvrregs)
1288 if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
1289 store_altivec_registers (regcache, tid);
1290 if (have_ptrace_getsetvsxregs)
1291 if (tdep->ppc_vsr0_upper_regnum != -1)
1292 store_vsx_registers (regcache, tid);
1293 if (tdep->ppc_ev0_upper_regnum >= 0)
1294 store_spe_register (regcache, tid, -1);
1295 }
1296
1297 /* Fetch the AT_HWCAP entry from the aux vector. */
1298 static unsigned long
1299 ppc_linux_get_hwcap (void)
1300 {
1301 CORE_ADDR field;
1302
1303 if (target_auxv_search (&current_target, AT_HWCAP, &field))
1304 return (unsigned long) field;
1305
1306 return 0;
1307 }
1308
1309 /* The cached DABR value, to install in new threads.
1310 This variable is used when the PowerPC HWDEBUG ptrace
1311 interface is not available. */
1312 static long saved_dabr_value;
1313
1314 /* Global structure that will store information about the available
1315 features provided by the PowerPC HWDEBUG ptrace interface. */
1316 static struct ppc_debug_info hwdebug_info;
1317
1318 /* Global variable that holds the maximum number of slots that the
1319 kernel will use. This is only used when PowerPC HWDEBUG ptrace interface
1320 is available. */
1321 static size_t max_slots_number = 0;
1322
1323 struct hw_break_tuple
1324 {
1325 long slot;
1326 struct ppc_hw_breakpoint *hw_break;
1327 };
1328
1329 /* This is an internal VEC created to store information about *points inserted
1330 for each thread. This is used when PowerPC HWDEBUG ptrace interface is
1331 available. */
1332 typedef struct thread_points
1333 {
1334 /* The TID to which this *point relates. */
1335 int tid;
1336 /* Information about the *point, such as its address, type, etc.
1337
1338 Each element inside this vector corresponds to a hardware
1339 breakpoint or watchpoint in the thread represented by TID. The maximum
1340 size of these vector is MAX_SLOTS_NUMBER. If the hw_break element of
1341 the tuple is NULL, then the position in the vector is free. */
1342 struct hw_break_tuple *hw_breaks;
1343 } *thread_points_p;
1344 DEF_VEC_P (thread_points_p);
1345
1346 VEC(thread_points_p) *ppc_threads = NULL;
1347
1348 /* The version of the PowerPC HWDEBUG kernel interface that we will use, if
1349 available. */
1350 #define PPC_DEBUG_CURRENT_VERSION 1
1351
1352 /* Returns non-zero if we support the PowerPC HWDEBUG ptrace interface. */
1353 static int
1354 have_ptrace_hwdebug_interface (void)
1355 {
1356 static int have_ptrace_hwdebug_interface = -1;
1357
1358 if (have_ptrace_hwdebug_interface == -1)
1359 {
1360 int tid;
1361
1362 tid = ptid_get_lwp (inferior_ptid);
1363 if (tid == 0)
1364 tid = ptid_get_pid (inferior_ptid);
1365
1366 /* Check for kernel support for PowerPC HWDEBUG ptrace interface. */
1367 if (ptrace (PPC_PTRACE_GETHWDBGINFO, tid, 0, &hwdebug_info) >= 0)
1368 {
1369 /* Check whether PowerPC HWDEBUG ptrace interface is functional and
1370 provides any supported feature. */
1371 if (hwdebug_info.features != 0)
1372 {
1373 have_ptrace_hwdebug_interface = 1;
1374 max_slots_number = hwdebug_info.num_instruction_bps
1375 + hwdebug_info.num_data_bps
1376 + hwdebug_info.num_condition_regs;
1377 return have_ptrace_hwdebug_interface;
1378 }
1379 }
1380 /* Old school interface and no PowerPC HWDEBUG ptrace support. */
1381 have_ptrace_hwdebug_interface = 0;
1382 memset (&hwdebug_info, 0, sizeof (struct ppc_debug_info));
1383 }
1384
1385 return have_ptrace_hwdebug_interface;
1386 }
1387
1388 static int
1389 ppc_linux_can_use_hw_breakpoint (struct target_ops *self,
1390 enum bptype type, int cnt, int ot)
1391 {
1392 int total_hw_wp, total_hw_bp;
1393
1394 if (have_ptrace_hwdebug_interface ())
1395 {
1396 /* When PowerPC HWDEBUG ptrace interface is available, the number of
1397 available hardware watchpoints and breakpoints is stored at the
1398 hwdebug_info struct. */
1399 total_hw_bp = hwdebug_info.num_instruction_bps;
1400 total_hw_wp = hwdebug_info.num_data_bps;
1401 }
1402 else
1403 {
1404 /* When we do not have PowerPC HWDEBUG ptrace interface, we should
1405 consider having 1 hardware watchpoint and no hardware breakpoints. */
1406 total_hw_bp = 0;
1407 total_hw_wp = 1;
1408 }
1409
1410 if (type == bp_hardware_watchpoint || type == bp_read_watchpoint
1411 || type == bp_access_watchpoint || type == bp_watchpoint)
1412 {
1413 if (cnt + ot > total_hw_wp)
1414 return -1;
1415 }
1416 else if (type == bp_hardware_breakpoint)
1417 {
1418 if (total_hw_bp == 0)
1419 {
1420 /* No hardware breakpoint support. */
1421 return 0;
1422 }
1423 if (cnt > total_hw_bp)
1424 return -1;
1425 }
1426
1427 if (!have_ptrace_hwdebug_interface ())
1428 {
1429 int tid;
1430 ptid_t ptid = inferior_ptid;
1431
1432 /* We need to know whether ptrace supports PTRACE_SET_DEBUGREG
1433 and whether the target has DABR. If either answer is no, the
1434 ptrace call will return -1. Fail in that case. */
1435 tid = ptid_get_lwp (ptid);
1436 if (tid == 0)
1437 tid = ptid_get_pid (ptid);
1438
1439 if (ptrace (PTRACE_SET_DEBUGREG, tid, 0, 0) == -1)
1440 return 0;
1441 }
1442
1443 return 1;
1444 }
1445
1446 static int
1447 ppc_linux_region_ok_for_hw_watchpoint (struct target_ops *self,
1448 CORE_ADDR addr, int len)
1449 {
1450 /* Handle sub-8-byte quantities. */
1451 if (len <= 0)
1452 return 0;
1453
1454 /* The PowerPC HWDEBUG ptrace interface tells if there are alignment
1455 restrictions for watchpoints in the processors. In that case, we use that
1456 information to determine the hardcoded watchable region for
1457 watchpoints. */
1458 if (have_ptrace_hwdebug_interface ())
1459 {
1460 int region_size;
1461 /* Embedded DAC-based processors, like the PowerPC 440 have ranged
1462 watchpoints and can watch any access within an arbitrary memory
1463 region. This is useful to watch arrays and structs, for instance. It
1464 takes two hardware watchpoints though. */
1465 if (len > 1
1466 && hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_RANGE
1467 && ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE)
1468 return 2;
1469 /* Check if the processor provides DAWR interface. */
1470 if (hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_DAWR)
1471 /* DAWR interface allows to watch up to 512 byte wide ranges which
1472 can't cross a 512 byte boundary. */
1473 region_size = 512;
1474 else
1475 region_size = hwdebug_info.data_bp_alignment;
1476 /* Server processors provide one hardware watchpoint and addr+len should
1477 fall in the watchable region provided by the ptrace interface. */
1478 if (region_size
1479 && (addr + len > (addr & ~(region_size - 1)) + region_size))
1480 return 0;
1481 }
1482 /* addr+len must fall in the 8 byte watchable region for DABR-based
1483 processors (i.e., server processors). Without the new PowerPC HWDEBUG
1484 ptrace interface, DAC-based processors (i.e., embedded processors) will
1485 use addresses aligned to 4-bytes due to the way the read/write flags are
1486 passed in the old ptrace interface. */
1487 else if (((ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE)
1488 && (addr + len) > (addr & ~3) + 4)
1489 || (addr + len) > (addr & ~7) + 8)
1490 return 0;
1491
1492 return 1;
1493 }
1494
1495 /* This function compares two ppc_hw_breakpoint structs field-by-field. */
1496 static int
1497 hwdebug_point_cmp (struct ppc_hw_breakpoint *a, struct ppc_hw_breakpoint *b)
1498 {
1499 return (a->trigger_type == b->trigger_type
1500 && a->addr_mode == b->addr_mode
1501 && a->condition_mode == b->condition_mode
1502 && a->addr == b->addr
1503 && a->addr2 == b->addr2
1504 && a->condition_value == b->condition_value);
1505 }
1506
1507 /* This function can be used to retrieve a thread_points by the TID of the
1508 related process/thread. If nothing has been found, and ALLOC_NEW is 0,
1509 it returns NULL. If ALLOC_NEW is non-zero, a new thread_points for the
1510 provided TID will be created and returned. */
1511 static struct thread_points *
1512 hwdebug_find_thread_points_by_tid (int tid, int alloc_new)
1513 {
1514 int i;
1515 struct thread_points *t;
1516
1517 for (i = 0; VEC_iterate (thread_points_p, ppc_threads, i, t); i++)
1518 if (t->tid == tid)
1519 return t;
1520
1521 t = NULL;
1522
1523 /* Do we need to allocate a new point_item
1524 if the wanted one does not exist? */
1525 if (alloc_new)
1526 {
1527 t = XNEW (struct thread_points);
1528 t->hw_breaks = XCNEWVEC (struct hw_break_tuple, max_slots_number);
1529 t->tid = tid;
1530 VEC_safe_push (thread_points_p, ppc_threads, t);
1531 }
1532
1533 return t;
1534 }
1535
1536 /* This function is a generic wrapper that is responsible for inserting a
1537 *point (i.e., calling `ptrace' in order to issue the request to the
1538 kernel) and registering it internally in GDB. */
1539 static void
1540 hwdebug_insert_point (struct ppc_hw_breakpoint *b, int tid)
1541 {
1542 int i;
1543 long slot;
1544 gdb::unique_xmalloc_ptr<ppc_hw_breakpoint> p (XDUP (ppc_hw_breakpoint, b));
1545 struct hw_break_tuple *hw_breaks;
1546 struct thread_points *t;
1547 struct hw_break_tuple *tuple;
1548
1549 errno = 0;
1550 slot = ptrace (PPC_PTRACE_SETHWDEBUG, tid, 0, p.get ());
1551 if (slot < 0)
1552 perror_with_name (_("Unexpected error setting breakpoint or watchpoint"));
1553
1554 /* Everything went fine, so we have to register this *point. */
1555 t = hwdebug_find_thread_points_by_tid (tid, 1);
1556 gdb_assert (t != NULL);
1557 hw_breaks = t->hw_breaks;
1558
1559 /* Find a free element in the hw_breaks vector. */
1560 for (i = 0; i < max_slots_number; i++)
1561 if (hw_breaks[i].hw_break == NULL)
1562 {
1563 hw_breaks[i].slot = slot;
1564 hw_breaks[i].hw_break = p.release ();
1565 break;
1566 }
1567
1568 gdb_assert (i != max_slots_number);
1569 }
1570
1571 /* This function is a generic wrapper that is responsible for removing a
1572 *point (i.e., calling `ptrace' in order to issue the request to the
1573 kernel), and unregistering it internally at GDB. */
1574 static void
1575 hwdebug_remove_point (struct ppc_hw_breakpoint *b, int tid)
1576 {
1577 int i;
1578 struct hw_break_tuple *hw_breaks;
1579 struct thread_points *t;
1580
1581 t = hwdebug_find_thread_points_by_tid (tid, 0);
1582 gdb_assert (t != NULL);
1583 hw_breaks = t->hw_breaks;
1584
1585 for (i = 0; i < max_slots_number; i++)
1586 if (hw_breaks[i].hw_break && hwdebug_point_cmp (hw_breaks[i].hw_break, b))
1587 break;
1588
1589 gdb_assert (i != max_slots_number);
1590
1591 /* We have to ignore ENOENT errors because the kernel implements hardware
1592 breakpoints/watchpoints as "one-shot", that is, they are automatically
1593 deleted when hit. */
1594 errno = 0;
1595 if (ptrace (PPC_PTRACE_DELHWDEBUG, tid, 0, hw_breaks[i].slot) < 0)
1596 if (errno != ENOENT)
1597 perror_with_name (_("Unexpected error deleting "
1598 "breakpoint or watchpoint"));
1599
1600 xfree (hw_breaks[i].hw_break);
1601 hw_breaks[i].hw_break = NULL;
1602 }
1603
1604 /* Return the number of registers needed for a ranged breakpoint. */
1605
1606 static int
1607 ppc_linux_ranged_break_num_registers (struct target_ops *target)
1608 {
1609 return ((have_ptrace_hwdebug_interface ()
1610 && hwdebug_info.features & PPC_DEBUG_FEATURE_INSN_BP_RANGE)?
1611 2 : -1);
1612 }
1613
1614 /* Insert the hardware breakpoint described by BP_TGT. Returns 0 for
1615 success, 1 if hardware breakpoints are not supported or -1 for failure. */
1616
1617 static int
1618 ppc_linux_insert_hw_breakpoint (struct target_ops *self,
1619 struct gdbarch *gdbarch,
1620 struct bp_target_info *bp_tgt)
1621 {
1622 struct lwp_info *lp;
1623 struct ppc_hw_breakpoint p;
1624
1625 if (!have_ptrace_hwdebug_interface ())
1626 return -1;
1627
1628 p.version = PPC_DEBUG_CURRENT_VERSION;
1629 p.trigger_type = PPC_BREAKPOINT_TRIGGER_EXECUTE;
1630 p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
1631 p.addr = (uint64_t) (bp_tgt->placed_address = bp_tgt->reqstd_address);
1632 p.condition_value = 0;
1633
1634 if (bp_tgt->length)
1635 {
1636 p.addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE;
1637
1638 /* The breakpoint will trigger if the address of the instruction is
1639 within the defined range, as follows: p.addr <= address < p.addr2. */
1640 p.addr2 = (uint64_t) bp_tgt->placed_address + bp_tgt->length;
1641 }
1642 else
1643 {
1644 p.addr_mode = PPC_BREAKPOINT_MODE_EXACT;
1645 p.addr2 = 0;
1646 }
1647
1648 ALL_LWPS (lp)
1649 hwdebug_insert_point (&p, ptid_get_lwp (lp->ptid));
1650
1651 return 0;
1652 }
1653
1654 static int
1655 ppc_linux_remove_hw_breakpoint (struct target_ops *self,
1656 struct gdbarch *gdbarch,
1657 struct bp_target_info *bp_tgt)
1658 {
1659 struct lwp_info *lp;
1660 struct ppc_hw_breakpoint p;
1661
1662 if (!have_ptrace_hwdebug_interface ())
1663 return -1;
1664
1665 p.version = PPC_DEBUG_CURRENT_VERSION;
1666 p.trigger_type = PPC_BREAKPOINT_TRIGGER_EXECUTE;
1667 p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
1668 p.addr = (uint64_t) bp_tgt->placed_address;
1669 p.condition_value = 0;
1670
1671 if (bp_tgt->length)
1672 {
1673 p.addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE;
1674
1675 /* The breakpoint will trigger if the address of the instruction is within
1676 the defined range, as follows: p.addr <= address < p.addr2. */
1677 p.addr2 = (uint64_t) bp_tgt->placed_address + bp_tgt->length;
1678 }
1679 else
1680 {
1681 p.addr_mode = PPC_BREAKPOINT_MODE_EXACT;
1682 p.addr2 = 0;
1683 }
1684
1685 ALL_LWPS (lp)
1686 hwdebug_remove_point (&p, ptid_get_lwp (lp->ptid));
1687
1688 return 0;
1689 }
1690
1691 static int
1692 get_trigger_type (enum target_hw_bp_type type)
1693 {
1694 int t;
1695
1696 if (type == hw_read)
1697 t = PPC_BREAKPOINT_TRIGGER_READ;
1698 else if (type == hw_write)
1699 t = PPC_BREAKPOINT_TRIGGER_WRITE;
1700 else
1701 t = PPC_BREAKPOINT_TRIGGER_READ | PPC_BREAKPOINT_TRIGGER_WRITE;
1702
1703 return t;
1704 }
1705
1706 /* Insert a new masked watchpoint at ADDR using the mask MASK.
1707 RW may be hw_read for a read watchpoint, hw_write for a write watchpoint
1708 or hw_access for an access watchpoint. Returns 0 on success and throws
1709 an error on failure. */
1710
1711 static int
1712 ppc_linux_insert_mask_watchpoint (struct target_ops *ops, CORE_ADDR addr,
1713 CORE_ADDR mask, enum target_hw_bp_type rw)
1714 {
1715 struct lwp_info *lp;
1716 struct ppc_hw_breakpoint p;
1717
1718 gdb_assert (have_ptrace_hwdebug_interface ());
1719
1720 p.version = PPC_DEBUG_CURRENT_VERSION;
1721 p.trigger_type = get_trigger_type (rw);
1722 p.addr_mode = PPC_BREAKPOINT_MODE_MASK;
1723 p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
1724 p.addr = addr;
1725 p.addr2 = mask;
1726 p.condition_value = 0;
1727
1728 ALL_LWPS (lp)
1729 hwdebug_insert_point (&p, ptid_get_lwp (lp->ptid));
1730
1731 return 0;
1732 }
1733
1734 /* Remove a masked watchpoint at ADDR with the mask MASK.
1735 RW may be hw_read for a read watchpoint, hw_write for a write watchpoint
1736 or hw_access for an access watchpoint. Returns 0 on success and throws
1737 an error on failure. */
1738
1739 static int
1740 ppc_linux_remove_mask_watchpoint (struct target_ops *ops, CORE_ADDR addr,
1741 CORE_ADDR mask, enum target_hw_bp_type rw)
1742 {
1743 struct lwp_info *lp;
1744 struct ppc_hw_breakpoint p;
1745
1746 gdb_assert (have_ptrace_hwdebug_interface ());
1747
1748 p.version = PPC_DEBUG_CURRENT_VERSION;
1749 p.trigger_type = get_trigger_type (rw);
1750 p.addr_mode = PPC_BREAKPOINT_MODE_MASK;
1751 p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
1752 p.addr = addr;
1753 p.addr2 = mask;
1754 p.condition_value = 0;
1755
1756 ALL_LWPS (lp)
1757 hwdebug_remove_point (&p, ptid_get_lwp (lp->ptid));
1758
1759 return 0;
1760 }
1761
1762 /* Check whether we have at least one free DVC register. */
1763 static int
1764 can_use_watchpoint_cond_accel (void)
1765 {
1766 struct thread_points *p;
1767 int tid = ptid_get_lwp (inferior_ptid);
1768 int cnt = hwdebug_info.num_condition_regs, i;
1769 CORE_ADDR tmp_value;
1770
1771 if (!have_ptrace_hwdebug_interface () || cnt == 0)
1772 return 0;
1773
1774 p = hwdebug_find_thread_points_by_tid (tid, 0);
1775
1776 if (p)
1777 {
1778 for (i = 0; i < max_slots_number; i++)
1779 if (p->hw_breaks[i].hw_break != NULL
1780 && (p->hw_breaks[i].hw_break->condition_mode
1781 != PPC_BREAKPOINT_CONDITION_NONE))
1782 cnt--;
1783
1784 /* There are no available slots now. */
1785 if (cnt <= 0)
1786 return 0;
1787 }
1788
1789 return 1;
1790 }
1791
1792 /* Calculate the enable bits and the contents of the Data Value Compare
1793 debug register present in BookE processors.
1794
1795 ADDR is the address to be watched, LEN is the length of watched data
1796 and DATA_VALUE is the value which will trigger the watchpoint.
1797 On exit, CONDITION_MODE will hold the enable bits for the DVC, and
1798 CONDITION_VALUE will hold the value which should be put in the
1799 DVC register. */
1800 static void
1801 calculate_dvc (CORE_ADDR addr, int len, CORE_ADDR data_value,
1802 uint32_t *condition_mode, uint64_t *condition_value)
1803 {
1804 int i, num_byte_enable, align_offset, num_bytes_off_dvc,
1805 rightmost_enabled_byte;
1806 CORE_ADDR addr_end_data, addr_end_dvc;
1807
1808 /* The DVC register compares bytes within fixed-length windows which
1809 are word-aligned, with length equal to that of the DVC register.
1810 We need to calculate where our watch region is relative to that
1811 window and enable comparison of the bytes which fall within it. */
1812
1813 align_offset = addr % hwdebug_info.sizeof_condition;
1814 addr_end_data = addr + len;
1815 addr_end_dvc = (addr - align_offset
1816 + hwdebug_info.sizeof_condition);
1817 num_bytes_off_dvc = (addr_end_data > addr_end_dvc)?
1818 addr_end_data - addr_end_dvc : 0;
1819 num_byte_enable = len - num_bytes_off_dvc;
1820 /* Here, bytes are numbered from right to left. */
1821 rightmost_enabled_byte = (addr_end_data < addr_end_dvc)?
1822 addr_end_dvc - addr_end_data : 0;
1823
1824 *condition_mode = PPC_BREAKPOINT_CONDITION_AND;
1825 for (i = 0; i < num_byte_enable; i++)
1826 *condition_mode
1827 |= PPC_BREAKPOINT_CONDITION_BE (i + rightmost_enabled_byte);
1828
1829 /* Now we need to match the position within the DVC of the comparison
1830 value with where the watch region is relative to the window
1831 (i.e., the ALIGN_OFFSET). */
1832
1833 *condition_value = ((uint64_t) data_value >> num_bytes_off_dvc * 8
1834 << rightmost_enabled_byte * 8);
1835 }
1836
1837 /* Return the number of memory locations that need to be accessed to
1838 evaluate the expression which generated the given value chain.
1839 Returns -1 if there's any register access involved, or if there are
1840 other kinds of values which are not acceptable in a condition
1841 expression (e.g., lval_computed or lval_internalvar). */
1842 static int
1843 num_memory_accesses (struct value *v)
1844 {
1845 int found_memory_cnt = 0;
1846 struct value *head = v;
1847
1848 /* The idea here is that evaluating an expression generates a series
1849 of values, one holding the value of every subexpression. (The
1850 expression a*b+c has five subexpressions: a, b, a*b, c, and
1851 a*b+c.) GDB's values hold almost enough information to establish
1852 the criteria given above --- they identify memory lvalues,
1853 register lvalues, computed values, etcetera. So we can evaluate
1854 the expression, and then scan the chain of values that leaves
1855 behind to determine the memory locations involved in the evaluation
1856 of an expression.
1857
1858 However, I don't think that the values returned by inferior
1859 function calls are special in any way. So this function may not
1860 notice that an expression contains an inferior function call.
1861 FIXME. */
1862
1863 for (; v; v = value_next (v))
1864 {
1865 /* Constants and values from the history are fine. */
1866 if (VALUE_LVAL (v) == not_lval || deprecated_value_modifiable (v) == 0)
1867 continue;
1868 else if (VALUE_LVAL (v) == lval_memory)
1869 {
1870 /* A lazy memory lvalue is one that GDB never needed to fetch;
1871 we either just used its address (e.g., `a' in `a.b') or
1872 we never needed it at all (e.g., `a' in `a,b'). */
1873 if (!value_lazy (v))
1874 found_memory_cnt++;
1875 }
1876 /* Other kinds of values are not fine. */
1877 else
1878 return -1;
1879 }
1880
1881 return found_memory_cnt;
1882 }
1883
1884 /* Verifies whether the expression COND can be implemented using the
1885 DVC (Data Value Compare) register in BookE processors. The expression
1886 must test the watch value for equality with a constant expression.
1887 If the function returns 1, DATA_VALUE will contain the constant against
1888 which the watch value should be compared and LEN will contain the size
1889 of the constant. */
1890 static int
1891 check_condition (CORE_ADDR watch_addr, struct expression *cond,
1892 CORE_ADDR *data_value, int *len)
1893 {
1894 int pc = 1, num_accesses_left, num_accesses_right;
1895 struct value *left_val, *right_val, *left_chain, *right_chain;
1896
1897 if (cond->elts[0].opcode != BINOP_EQUAL)
1898 return 0;
1899
1900 fetch_subexp_value (cond, &pc, &left_val, NULL, &left_chain, 0);
1901 num_accesses_left = num_memory_accesses (left_chain);
1902
1903 if (left_val == NULL || num_accesses_left < 0)
1904 {
1905 free_value_chain (left_chain);
1906
1907 return 0;
1908 }
1909
1910 fetch_subexp_value (cond, &pc, &right_val, NULL, &right_chain, 0);
1911 num_accesses_right = num_memory_accesses (right_chain);
1912
1913 if (right_val == NULL || num_accesses_right < 0)
1914 {
1915 free_value_chain (left_chain);
1916 free_value_chain (right_chain);
1917
1918 return 0;
1919 }
1920
1921 if (num_accesses_left == 1 && num_accesses_right == 0
1922 && VALUE_LVAL (left_val) == lval_memory
1923 && value_address (left_val) == watch_addr)
1924 {
1925 *data_value = value_as_long (right_val);
1926
1927 /* DATA_VALUE is the constant in RIGHT_VAL, but actually has
1928 the same type as the memory region referenced by LEFT_VAL. */
1929 *len = TYPE_LENGTH (check_typedef (value_type (left_val)));
1930 }
1931 else if (num_accesses_left == 0 && num_accesses_right == 1
1932 && VALUE_LVAL (right_val) == lval_memory
1933 && value_address (right_val) == watch_addr)
1934 {
1935 *data_value = value_as_long (left_val);
1936
1937 /* DATA_VALUE is the constant in LEFT_VAL, but actually has
1938 the same type as the memory region referenced by RIGHT_VAL. */
1939 *len = TYPE_LENGTH (check_typedef (value_type (right_val)));
1940 }
1941 else
1942 {
1943 free_value_chain (left_chain);
1944 free_value_chain (right_chain);
1945
1946 return 0;
1947 }
1948
1949 free_value_chain (left_chain);
1950 free_value_chain (right_chain);
1951
1952 return 1;
1953 }
1954
1955 /* Return non-zero if the target is capable of using hardware to evaluate
1956 the condition expression, thus only triggering the watchpoint when it is
1957 true. */
1958 static int
1959 ppc_linux_can_accel_watchpoint_condition (struct target_ops *self,
1960 CORE_ADDR addr, int len, int rw,
1961 struct expression *cond)
1962 {
1963 CORE_ADDR data_value;
1964
1965 return (have_ptrace_hwdebug_interface ()
1966 && hwdebug_info.num_condition_regs > 0
1967 && check_condition (addr, cond, &data_value, &len));
1968 }
1969
1970 /* Set up P with the parameters necessary to request a watchpoint covering
1971 LEN bytes starting at ADDR and if possible with condition expression COND
1972 evaluated by hardware. INSERT tells if we are creating a request for
1973 inserting or removing the watchpoint. */
1974
1975 static void
1976 create_watchpoint_request (struct ppc_hw_breakpoint *p, CORE_ADDR addr,
1977 int len, enum target_hw_bp_type type,
1978 struct expression *cond, int insert)
1979 {
1980 if (len == 1
1981 || !(hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_RANGE))
1982 {
1983 int use_condition;
1984 CORE_ADDR data_value;
1985
1986 use_condition = (insert? can_use_watchpoint_cond_accel ()
1987 : hwdebug_info.num_condition_regs > 0);
1988 if (cond && use_condition && check_condition (addr, cond,
1989 &data_value, &len))
1990 calculate_dvc (addr, len, data_value, &p->condition_mode,
1991 &p->condition_value);
1992 else
1993 {
1994 p->condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
1995 p->condition_value = 0;
1996 }
1997
1998 p->addr_mode = PPC_BREAKPOINT_MODE_EXACT;
1999 p->addr2 = 0;
2000 }
2001 else
2002 {
2003 p->addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE;
2004 p->condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
2005 p->condition_value = 0;
2006
2007 /* The watchpoint will trigger if the address of the memory access is
2008 within the defined range, as follows: p->addr <= address < p->addr2.
2009
2010 Note that the above sentence just documents how ptrace interprets
2011 its arguments; the watchpoint is set to watch the range defined by
2012 the user _inclusively_, as specified by the user interface. */
2013 p->addr2 = (uint64_t) addr + len;
2014 }
2015
2016 p->version = PPC_DEBUG_CURRENT_VERSION;
2017 p->trigger_type = get_trigger_type (type);
2018 p->addr = (uint64_t) addr;
2019 }
2020
2021 static int
2022 ppc_linux_insert_watchpoint (struct target_ops *self, CORE_ADDR addr, int len,
2023 enum target_hw_bp_type type,
2024 struct expression *cond)
2025 {
2026 struct lwp_info *lp;
2027 int ret = -1;
2028
2029 if (have_ptrace_hwdebug_interface ())
2030 {
2031 struct ppc_hw_breakpoint p;
2032
2033 create_watchpoint_request (&p, addr, len, type, cond, 1);
2034
2035 ALL_LWPS (lp)
2036 hwdebug_insert_point (&p, ptid_get_lwp (lp->ptid));
2037
2038 ret = 0;
2039 }
2040 else
2041 {
2042 long dabr_value;
2043 long read_mode, write_mode;
2044
2045 if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE)
2046 {
2047 /* PowerPC 440 requires only the read/write flags to be passed
2048 to the kernel. */
2049 read_mode = 1;
2050 write_mode = 2;
2051 }
2052 else
2053 {
2054 /* PowerPC 970 and other DABR-based processors are required to pass
2055 the Breakpoint Translation bit together with the flags. */
2056 read_mode = 5;
2057 write_mode = 6;
2058 }
2059
2060 dabr_value = addr & ~(read_mode | write_mode);
2061 switch (type)
2062 {
2063 case hw_read:
2064 /* Set read and translate bits. */
2065 dabr_value |= read_mode;
2066 break;
2067 case hw_write:
2068 /* Set write and translate bits. */
2069 dabr_value |= write_mode;
2070 break;
2071 case hw_access:
2072 /* Set read, write and translate bits. */
2073 dabr_value |= read_mode | write_mode;
2074 break;
2075 }
2076
2077 saved_dabr_value = dabr_value;
2078
2079 ALL_LWPS (lp)
2080 if (ptrace (PTRACE_SET_DEBUGREG, ptid_get_lwp (lp->ptid), 0,
2081 saved_dabr_value) < 0)
2082 return -1;
2083
2084 ret = 0;
2085 }
2086
2087 return ret;
2088 }
2089
2090 static int
2091 ppc_linux_remove_watchpoint (struct target_ops *self, CORE_ADDR addr, int len,
2092 enum target_hw_bp_type type,
2093 struct expression *cond)
2094 {
2095 struct lwp_info *lp;
2096 int ret = -1;
2097
2098 if (have_ptrace_hwdebug_interface ())
2099 {
2100 struct ppc_hw_breakpoint p;
2101
2102 create_watchpoint_request (&p, addr, len, type, cond, 0);
2103
2104 ALL_LWPS (lp)
2105 hwdebug_remove_point (&p, ptid_get_lwp (lp->ptid));
2106
2107 ret = 0;
2108 }
2109 else
2110 {
2111 saved_dabr_value = 0;
2112 ALL_LWPS (lp)
2113 if (ptrace (PTRACE_SET_DEBUGREG, ptid_get_lwp (lp->ptid), 0,
2114 saved_dabr_value) < 0)
2115 return -1;
2116
2117 ret = 0;
2118 }
2119
2120 return ret;
2121 }
2122
2123 static void
2124 ppc_linux_new_thread (struct lwp_info *lp)
2125 {
2126 int tid = ptid_get_lwp (lp->ptid);
2127
2128 if (have_ptrace_hwdebug_interface ())
2129 {
2130 int i;
2131 struct thread_points *p;
2132 struct hw_break_tuple *hw_breaks;
2133
2134 if (VEC_empty (thread_points_p, ppc_threads))
2135 return;
2136
2137 /* Get a list of breakpoints from any thread. */
2138 p = VEC_last (thread_points_p, ppc_threads);
2139 hw_breaks = p->hw_breaks;
2140
2141 /* Copy that thread's breakpoints and watchpoints to the new thread. */
2142 for (i = 0; i < max_slots_number; i++)
2143 if (hw_breaks[i].hw_break)
2144 {
2145 /* Older kernels did not make new threads inherit their parent
2146 thread's debug state, so we always clear the slot and replicate
2147 the debug state ourselves, ensuring compatibility with all
2148 kernels. */
2149
2150 /* The ppc debug resource accounting is done through "slots".
2151 Ask the kernel the deallocate this specific *point's slot. */
2152 ptrace (PPC_PTRACE_DELHWDEBUG, tid, 0, hw_breaks[i].slot);
2153
2154 hwdebug_insert_point (hw_breaks[i].hw_break, tid);
2155 }
2156 }
2157 else
2158 ptrace (PTRACE_SET_DEBUGREG, tid, 0, saved_dabr_value);
2159 }
2160
2161 static void
2162 ppc_linux_thread_exit (struct thread_info *tp, int silent)
2163 {
2164 int i;
2165 int tid = ptid_get_lwp (tp->ptid);
2166 struct hw_break_tuple *hw_breaks;
2167 struct thread_points *t = NULL, *p;
2168
2169 if (!have_ptrace_hwdebug_interface ())
2170 return;
2171
2172 for (i = 0; VEC_iterate (thread_points_p, ppc_threads, i, p); i++)
2173 if (p->tid == tid)
2174 {
2175 t = p;
2176 break;
2177 }
2178
2179 if (t == NULL)
2180 return;
2181
2182 VEC_unordered_remove (thread_points_p, ppc_threads, i);
2183
2184 hw_breaks = t->hw_breaks;
2185
2186 for (i = 0; i < max_slots_number; i++)
2187 if (hw_breaks[i].hw_break)
2188 xfree (hw_breaks[i].hw_break);
2189
2190 xfree (t->hw_breaks);
2191 xfree (t);
2192 }
2193
2194 static int
2195 ppc_linux_stopped_data_address (struct target_ops *target, CORE_ADDR *addr_p)
2196 {
2197 siginfo_t siginfo;
2198
2199 if (!linux_nat_get_siginfo (inferior_ptid, &siginfo))
2200 return 0;
2201
2202 if (siginfo.si_signo != SIGTRAP
2203 || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */)
2204 return 0;
2205
2206 if (have_ptrace_hwdebug_interface ())
2207 {
2208 int i;
2209 struct thread_points *t;
2210 struct hw_break_tuple *hw_breaks;
2211 /* The index (or slot) of the *point is passed in the si_errno field. */
2212 int slot = siginfo.si_errno;
2213
2214 t = hwdebug_find_thread_points_by_tid (ptid_get_lwp (inferior_ptid), 0);
2215
2216 /* Find out if this *point is a hardware breakpoint.
2217 If so, we should return 0. */
2218 if (t)
2219 {
2220 hw_breaks = t->hw_breaks;
2221 for (i = 0; i < max_slots_number; i++)
2222 if (hw_breaks[i].hw_break && hw_breaks[i].slot == slot
2223 && hw_breaks[i].hw_break->trigger_type
2224 == PPC_BREAKPOINT_TRIGGER_EXECUTE)
2225 return 0;
2226 }
2227 }
2228
2229 *addr_p = (CORE_ADDR) (uintptr_t) siginfo.si_addr;
2230 return 1;
2231 }
2232
2233 static int
2234 ppc_linux_stopped_by_watchpoint (struct target_ops *ops)
2235 {
2236 CORE_ADDR addr;
2237 return ppc_linux_stopped_data_address (ops, &addr);
2238 }
2239
2240 static int
2241 ppc_linux_watchpoint_addr_within_range (struct target_ops *target,
2242 CORE_ADDR addr,
2243 CORE_ADDR start, int length)
2244 {
2245 int mask;
2246
2247 if (have_ptrace_hwdebug_interface ()
2248 && ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE)
2249 return start <= addr && start + length >= addr;
2250 else if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE)
2251 mask = 3;
2252 else
2253 mask = 7;
2254
2255 addr &= ~mask;
2256
2257 /* Check whether [start, start+length-1] intersects [addr, addr+mask]. */
2258 return start <= addr + mask && start + length - 1 >= addr;
2259 }
2260
2261 /* Return the number of registers needed for a masked hardware watchpoint. */
2262
2263 static int
2264 ppc_linux_masked_watch_num_registers (struct target_ops *target,
2265 CORE_ADDR addr, CORE_ADDR mask)
2266 {
2267 if (!have_ptrace_hwdebug_interface ()
2268 || (hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_MASK) == 0)
2269 return -1;
2270 else if ((mask & 0xC0000000) != 0xC0000000)
2271 {
2272 warning (_("The given mask covers kernel address space "
2273 "and cannot be used.\n"));
2274
2275 return -2;
2276 }
2277 else
2278 return 2;
2279 }
2280
2281 static void
2282 ppc_linux_store_inferior_registers (struct target_ops *ops,
2283 struct regcache *regcache, int regno)
2284 {
2285 pid_t tid = get_ptrace_pid (regcache_get_ptid (regcache));
2286
2287 if (regno >= 0)
2288 store_register (regcache, tid, regno);
2289 else
2290 store_ppc_registers (regcache, tid);
2291 }
2292
2293 /* Functions for transferring registers between a gregset_t or fpregset_t
2294 (see sys/ucontext.h) and gdb's regcache. The word size is that used
2295 by the ptrace interface, not the current program's ABI. Eg. if a
2296 powerpc64-linux gdb is being used to debug a powerpc32-linux app, we
2297 read or write 64-bit gregsets. This is to suit the host libthread_db. */
2298
2299 void
2300 supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp)
2301 {
2302 const struct regset *regset = ppc_linux_gregset (sizeof (long));
2303
2304 ppc_supply_gregset (regset, regcache, -1, gregsetp, sizeof (*gregsetp));
2305 }
2306
2307 void
2308 fill_gregset (const struct regcache *regcache,
2309 gdb_gregset_t *gregsetp, int regno)
2310 {
2311 const struct regset *regset = ppc_linux_gregset (sizeof (long));
2312
2313 if (regno == -1)
2314 memset (gregsetp, 0, sizeof (*gregsetp));
2315 ppc_collect_gregset (regset, regcache, regno, gregsetp, sizeof (*gregsetp));
2316 }
2317
2318 void
2319 supply_fpregset (struct regcache *regcache, const gdb_fpregset_t * fpregsetp)
2320 {
2321 const struct regset *regset = ppc_linux_fpregset ();
2322
2323 ppc_supply_fpregset (regset, regcache, -1,
2324 fpregsetp, sizeof (*fpregsetp));
2325 }
2326
2327 void
2328 fill_fpregset (const struct regcache *regcache,
2329 gdb_fpregset_t *fpregsetp, int regno)
2330 {
2331 const struct regset *regset = ppc_linux_fpregset ();
2332
2333 ppc_collect_fpregset (regset, regcache, regno,
2334 fpregsetp, sizeof (*fpregsetp));
2335 }
2336
2337 static int
2338 ppc_linux_target_wordsize (void)
2339 {
2340 int wordsize = 4;
2341
2342 /* Check for 64-bit inferior process. This is the case when the host is
2343 64-bit, and in addition the top bit of the MSR register is set. */
2344 #ifdef __powerpc64__
2345 long msr;
2346
2347 int tid = ptid_get_lwp (inferior_ptid);
2348 if (tid == 0)
2349 tid = ptid_get_pid (inferior_ptid);
2350
2351 errno = 0;
2352 msr = (long) ptrace (PTRACE_PEEKUSER, tid, PT_MSR * 8, 0);
2353 if (errno == 0 && ppc64_64bit_inferior_p (msr))
2354 wordsize = 8;
2355 #endif
2356
2357 return wordsize;
2358 }
2359
2360 static int
2361 ppc_linux_auxv_parse (struct target_ops *ops, gdb_byte **readptr,
2362 gdb_byte *endptr, CORE_ADDR *typep, CORE_ADDR *valp)
2363 {
2364 int sizeof_auxv_field = ppc_linux_target_wordsize ();
2365 enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ());
2366 gdb_byte *ptr = *readptr;
2367
2368 if (endptr == ptr)
2369 return 0;
2370
2371 if (endptr - ptr < sizeof_auxv_field * 2)
2372 return -1;
2373
2374 *typep = extract_unsigned_integer (ptr, sizeof_auxv_field, byte_order);
2375 ptr += sizeof_auxv_field;
2376 *valp = extract_unsigned_integer (ptr, sizeof_auxv_field, byte_order);
2377 ptr += sizeof_auxv_field;
2378
2379 *readptr = ptr;
2380 return 1;
2381 }
2382
2383 static const struct target_desc *
2384 ppc_linux_read_description (struct target_ops *ops)
2385 {
2386 int altivec = 0;
2387 int vsx = 0;
2388 int isa205 = 0;
2389 int cell = 0;
2390
2391 int tid = ptid_get_lwp (inferior_ptid);
2392 if (tid == 0)
2393 tid = ptid_get_pid (inferior_ptid);
2394
2395 if (have_ptrace_getsetevrregs)
2396 {
2397 struct gdb_evrregset_t evrregset;
2398
2399 if (ptrace (PTRACE_GETEVRREGS, tid, 0, &evrregset) >= 0)
2400 return tdesc_powerpc_e500l;
2401
2402 /* EIO means that the PTRACE_GETEVRREGS request isn't supported.
2403 Anything else needs to be reported. */
2404 else if (errno != EIO)
2405 perror_with_name (_("Unable to fetch SPE registers"));
2406 }
2407
2408 if (have_ptrace_getsetvsxregs
2409 && (ppc_linux_get_hwcap () & PPC_FEATURE_HAS_VSX))
2410 {
2411 gdb_vsxregset_t vsxregset;
2412
2413 if (ptrace (PTRACE_GETVSXREGS, tid, 0, &vsxregset) >= 0)
2414 vsx = 1;
2415
2416 /* EIO means that the PTRACE_GETVSXREGS request isn't supported.
2417 Anything else needs to be reported. */
2418 else if (errno != EIO)
2419 perror_with_name (_("Unable to fetch VSX registers"));
2420 }
2421
2422 if (have_ptrace_getvrregs
2423 && (ppc_linux_get_hwcap () & PPC_FEATURE_HAS_ALTIVEC))
2424 {
2425 gdb_vrregset_t vrregset;
2426
2427 if (ptrace (PTRACE_GETVRREGS, tid, 0, &vrregset) >= 0)
2428 altivec = 1;
2429
2430 /* EIO means that the PTRACE_GETVRREGS request isn't supported.
2431 Anything else needs to be reported. */
2432 else if (errno != EIO)
2433 perror_with_name (_("Unable to fetch AltiVec registers"));
2434 }
2435
2436 /* Power ISA 2.05 (implemented by Power 6 and newer processors) increases
2437 the FPSCR from 32 bits to 64 bits. Even though Power 7 supports this
2438 ISA version, it doesn't have PPC_FEATURE_ARCH_2_05 set, only
2439 PPC_FEATURE_ARCH_2_06. Since for now the only bits used in the higher
2440 half of the register are for Decimal Floating Point, we check if that
2441 feature is available to decide the size of the FPSCR. */
2442 if (ppc_linux_get_hwcap () & PPC_FEATURE_HAS_DFP)
2443 isa205 = 1;
2444
2445 if (ppc_linux_get_hwcap () & PPC_FEATURE_CELL)
2446 cell = 1;
2447
2448 if (ppc_linux_target_wordsize () == 8)
2449 {
2450 if (cell)
2451 return tdesc_powerpc_cell64l;
2452 else if (vsx)
2453 return isa205? tdesc_powerpc_isa205_vsx64l : tdesc_powerpc_vsx64l;
2454 else if (altivec)
2455 return isa205
2456 ? tdesc_powerpc_isa205_altivec64l : tdesc_powerpc_altivec64l;
2457
2458 return isa205? tdesc_powerpc_isa205_64l : tdesc_powerpc_64l;
2459 }
2460
2461 if (cell)
2462 return tdesc_powerpc_cell32l;
2463 else if (vsx)
2464 return isa205? tdesc_powerpc_isa205_vsx32l : tdesc_powerpc_vsx32l;
2465 else if (altivec)
2466 return isa205? tdesc_powerpc_isa205_altivec32l : tdesc_powerpc_altivec32l;
2467
2468 return isa205? tdesc_powerpc_isa205_32l : tdesc_powerpc_32l;
2469 }
2470
2471 void
2472 _initialize_ppc_linux_nat (void)
2473 {
2474 struct target_ops *t;
2475
2476 /* Fill in the generic GNU/Linux methods. */
2477 t = linux_target ();
2478
2479 /* Add our register access methods. */
2480 t->to_fetch_registers = ppc_linux_fetch_inferior_registers;
2481 t->to_store_registers = ppc_linux_store_inferior_registers;
2482
2483 /* Add our breakpoint/watchpoint methods. */
2484 t->to_can_use_hw_breakpoint = ppc_linux_can_use_hw_breakpoint;
2485 t->to_insert_hw_breakpoint = ppc_linux_insert_hw_breakpoint;
2486 t->to_remove_hw_breakpoint = ppc_linux_remove_hw_breakpoint;
2487 t->to_region_ok_for_hw_watchpoint = ppc_linux_region_ok_for_hw_watchpoint;
2488 t->to_insert_watchpoint = ppc_linux_insert_watchpoint;
2489 t->to_remove_watchpoint = ppc_linux_remove_watchpoint;
2490 t->to_insert_mask_watchpoint = ppc_linux_insert_mask_watchpoint;
2491 t->to_remove_mask_watchpoint = ppc_linux_remove_mask_watchpoint;
2492 t->to_stopped_by_watchpoint = ppc_linux_stopped_by_watchpoint;
2493 t->to_stopped_data_address = ppc_linux_stopped_data_address;
2494 t->to_watchpoint_addr_within_range = ppc_linux_watchpoint_addr_within_range;
2495 t->to_can_accel_watchpoint_condition
2496 = ppc_linux_can_accel_watchpoint_condition;
2497 t->to_masked_watch_num_registers = ppc_linux_masked_watch_num_registers;
2498 t->to_ranged_break_num_registers = ppc_linux_ranged_break_num_registers;
2499
2500 t->to_read_description = ppc_linux_read_description;
2501 t->to_auxv_parse = ppc_linux_auxv_parse;
2502
2503 observer_attach_thread_exit (ppc_linux_thread_exit);
2504
2505 /* Register the target. */
2506 linux_nat_add_target (t);
2507 linux_nat_set_new_thread (t, ppc_linux_new_thread);
2508 }
target_gdbarch
struct gdbarch * target_gdbarch(void)
Definition: gdbarch.c:5467
gdbarch
Definition: gdbarch.c:127
bp_target_info::reqstd_address
CORE_ADDR reqstd_address
Definition: breakpoint.h:251
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union exp_element elts[1]
Definition: expression.h:84
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uint32_t num_condition_regs
Definition: ppc-linux-nat.c:80
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static int ppc_linux_can_accel_watchpoint_condition(struct target_ops *self, CORE_ADDR addr, int len, int rw, struct expression *cond)
Definition: ppc-linux-nat.c:1959
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#define PTRACE_SET_DEBUGREG
Definition: ppc-linux-nat.c:56
PPC_PTRACE_GETHWDBGINFO
#define PPC_PTRACE_GETHWDBGINFO
Definition: ppc-linux-nat.c:71
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struct ppc_hw_breakpoint * hw_break
Definition: ppc-linux-nat.c:1326
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static void hwdebug_remove_point(struct ppc_hw_breakpoint *b, int tid)
Definition: ppc-linux-nat.c:1575
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static int ppc_linux_insert_mask_watchpoint(struct target_ops *ops, CORE_ADDR addr, CORE_ADDR mask, enum target_hw_bp_type rw)
Definition: ppc-linux-nat.c:1712
selftests::ptid::tid
static constexpr ptid_t tid
Definition: ptid-selftests.c:43
value_next
struct value * value_next(const struct value *value)
Definition: value.c:1089
ppc_linux_new_thread
static void ppc_linux_new_thread(struct lwp_info *lp)
Definition: ppc-linux-nat.c:2124
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struct observer * observer_attach_thread_exit(observer_thread_exit_ftype *f)
target_ops::to_read_description
const struct target_desc *(* to_read_description)(struct target_ops *ops) TARGET_DEFAULT_RETURN(NULL)
Definition: target.h:790
supply_vsxregset
static void supply_vsxregset(struct regcache *regcache, gdb_vsxregset_t *vsxregsetp)
Definition: ppc-linux-nat.c:583
have_ptrace_getsetevrregs
int have_ptrace_getsetevrregs
Definition: ppc-linux-nat.c:256
hwdebug_point_cmp
static int hwdebug_point_cmp(struct ppc_hw_breakpoint *a, struct ppc_hw_breakpoint *b)
Definition: ppc-linux-nat.c:1497
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static int fetch_all_gp_regs(struct regcache *regcache, int tid)
Definition: ppc-linux-nat.c:669
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uint64_t features
Definition: ppc-linux-nat.c:83
ppc_debug_info::sizeof_condition
uint32_t sizeof_condition
Definition: ppc-linux-nat.c:82
exp_element::opcode
enum exp_opcode opcode
Definition: expression.h:64
PT_ORIG_R3
#define PT_ORIG_R3
Definition: ppc-linux.h:26
CORE_ADDR
bfd_vma CORE_ADDR
Definition: common-types.h:41
target_ops::to_insert_mask_watchpoint
int(* to_insert_mask_watchpoint)(struct target_ops *, CORE_ADDR, CORE_ADDR, enum target_hw_bp_type) TARGET_DEFAULT_RETURN(1)
Definition: target.h:523
thread_points_p
struct thread_points * thread_points_p
ppc_linux_auxv_parse
static int ppc_linux_auxv_parse(struct target_ops *ops, gdb_byte **readptr, gdb_byte *endptr, CORE_ADDR *typep, CORE_ADDR *valp)
Definition: ppc-linux-nat.c:2361
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static int can_use_watchpoint_cond_accel(void)
Definition: ppc-linux-nat.c:1764
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int ptid_get_pid(const ptid_t &ptid)
Definition: ptid.c:47
fill_vrregset
static void fill_vrregset(const struct regcache *regcache, gdb_vrregset_t *vrregsetp)
Definition: ppc-linux-nat.c:1063
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void xfree(void *)
lwp_info
Definition: linux-nat.h:30
store_vsx_registers
static void store_vsx_registers(const struct regcache *regcache, int tid)
Definition: ppc-linux-nat.c:1086
tdesc_powerpc_isa205_vsx32l
struct target_desc * tdesc_powerpc_isa205_vsx32l
Definition: powerpc-isa205-vsx32l.c:8
hw_break_tuple::slot
long slot
Definition: ppc-linux-nat.c:1325
ALL_LWPS
#define ALL_LWPS(LP)
Definition: linux-nat.h:119
gdbarch_tdep::ppc_lr_regnum
int ppc_lr_regnum
Definition: ppc-tdep.h:231
value_as_long
LONGEST value_as_long(struct value *val)
Definition: value.c:2749
PPC_ORIG_R3_REGNUM
Definition: ppc-linux-tdep.h:36
ppc_num_fprs
Definition: ppc-tdep.h:284
if
if(!(yy_init))
Definition: ada-lex.c:1075
linux_nat_set_new_thread
void linux_nat_set_new_thread(struct target_ops *t, void(*new_thread)(struct lwp_info *))
Definition: linux-nat.c:4873
ppc_supply_fpregset
void ppc_supply_fpregset(const struct regset *regset, struct regcache *regcache, int regnum, const void *fpregs, size_t len)
Definition: rs6000-tdep.c:561
warning
void warning(const char *fmt,...)
Definition: errors.c:26
gdbarch_tdep::gregset
const struct regset * gregset
Definition: sparc-tdep.h:73
deprecated_value_modifiable
int deprecated_value_modifiable(const struct value *value)
Definition: value.c:1580
lwp_info::ptid
ptid_t ptid
Definition: linux-nat.h:34
fetch_gp_regs
static void fetch_gp_regs(struct regcache *regcache, int tid)
Definition: ppc-linux-nat.c:697
tdesc_powerpc_e500l
struct target_desc * tdesc_powerpc_e500l
Definition: powerpc-e500l.c:8
store_altivec_registers
static void store_altivec_registers(const struct regcache *regcache, int tid)
Definition: ppc-linux-nat.c:1109
gdbarch_tdep::ppc_fpscr_regnum
int ppc_fpscr_regnum
Definition: ppc-tdep.h:241
regcache_get_ptid
ptid_t regcache_get_ptid(const struct regcache *regcache)
Definition: regcache.c:229
ppc-tdep.h
memset
void * memset(T *s, int c, size_t n)=delete
internal_error
void internal_error(const char *file, int line, const char *fmt,...)
Definition: errors.c:50
store_all_fp_regs
static int store_all_fp_regs(const struct regcache *regcache, int tid, int regno)
Definition: ppc-linux-nat.c:1204
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static struct ppc_debug_info hwdebug_info
Definition: ppc-linux-nat.c:1316
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Definition: aarch64-tdep.h:55
have_ptrace_getsetvsxregs
int have_ptrace_getsetvsxregs
Definition: ppc-linux-nat.c:244
VEC_unordered_remove
#define VEC_unordered_remove(T, V, I)
Definition: vec.h:367
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static int ppc_register_u_addr(struct gdbarch *gdbarch, int regno)
Definition: ppc-linux-nat.c:288
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int value_lazy(const struct value *value)
Definition: value.c:1383
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static void supply_vrregset(struct regcache *regcache, gdb_vrregset_t *vrregsetp)
Definition: ppc-linux-nat.c:598
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Definition: breakpoint.h:75
auxv.h
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int ppc_spefscr_regnum
Definition: ppc-tdep.h:259
tdesc_powerpc_32l
struct target_desc * tdesc_powerpc_32l
Definition: powerpc-32l.c:8
tdesc_powerpc_isa205_64l
struct target_desc * tdesc_powerpc_isa205_64l
Definition: powerpc-isa205-64l.c:8
VEC_safe_push
#define VEC_safe_push(T, V, O)
Definition: vec.h:276
PTRACE_GETEVRREGS
#define PTRACE_GETEVRREGS
Definition: ppc-linux.h:81
ppc_linux_store_inferior_registers
static void ppc_linux_store_inferior_registers(struct target_ops *ops, struct regcache *regcache, int regno)
Definition: ppc-linux-nat.c:2282
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int(* to_remove_watchpoint)(struct target_ops *, CORE_ADDR, int, enum target_hw_bp_type, struct expression *) TARGET_DEFAULT_RETURN(-1)
Definition: target.h:516
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const struct regset * ppc_linux_gregset(int wordsize)
Definition: ppc-linux-tdep.c:506
target_ops::to_region_ok_for_hw_watchpoint
int(* to_region_ok_for_hw_watchpoint)(struct target_ops *, CORE_ADDR, int) TARGET_DEFAULT_FUNC(default_region_ok_for_hw_watchpoint)
Definition: target.h:543
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static int ppc_linux_stopped_data_address(struct target_ops *target, CORE_ADDR *addr_p)
Definition: ppc-linux-nat.c:2195
_initialize_ppc_linux_nat
void _initialize_ppc_linux_nat(void)
Definition: ppc-linux-nat.c:2472
PTRACE_SETFPREGS
#define PTRACE_SETFPREGS
Definition: ppc-linux-nat.c:145
target_ops::to_can_use_hw_breakpoint
int(* to_can_use_hw_breakpoint)(struct target_ops *, enum bptype, int, int) TARGET_DEFAULT_RETURN(0)
Definition: target.h:502
_
#define _(String)
Definition: gdb_locale.h:35
ppc_linux_masked_watch_num_registers
static int ppc_linux_masked_watch_num_registers(struct target_ops *target, CORE_ADDR addr, CORE_ADDR mask)
Definition: ppc-linux-nat.c:2264
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int vsx_register_p(struct gdbarch *gdbarch, int regno)
Definition: rs6000-tdep.c:162
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int linux_nat_get_siginfo(ptid_t ptid, siginfo_t *siginfo)
Definition: linux-nat.c:4948
defs.h
gdbarch_tdep::ppc_cr_regnum
int ppc_cr_regnum
Definition: ppc-tdep.h:230
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struct gdbarch_tdep * gdbarch_tdep(struct gdbarch *gdbarch)
Definition: gdbarch.c:1491
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void supply_gregset(struct regcache *regcache, const gdb_gregset_t *gregsetp)
Definition: ppc-linux-nat.c:2300
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uint32_t version
Definition: ppc-linux-nat.c:94
PPC_BREAKPOINT_MODE_MASK
#define PPC_BREAKPOINT_MODE_MASK
Definition: ppc-linux-nat.c:113
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Definition: ppc-linux-nat.c:232
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struct target_desc * tdesc_powerpc_cell32l
Definition: powerpc-cell32l.c:8
fetch_spe_register
static void fetch_spe_register(struct regcache *regcache, int tid, int regno)
Definition: ppc-linux-nat.c:453
VALUE_LVAL
#define VALUE_LVAL(val)
Definition: value.h:414
PPC_DEBUG_FEATURE_DATA_BP_DAWR
#define PPC_DEBUG_FEATURE_DATA_BP_DAWR
Definition: ppc-linux-nat.c:130
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static int ppc_linux_ranged_break_num_registers(struct target_ops *target)
Definition: ppc-linux-nat.c:1607
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PTRACE_TYPE_RET ptrace()
hw_write
Definition: break-common.h:24
ppc_linux_read_description
static const struct target_desc * ppc_linux_read_description(struct target_ops *ops)
Definition: ppc-linux-nat.c:2384
XNEW
#define XNEW(T)
Definition: poison.h:109
gdb_evrregset_t::evr
unsigned long evr[32]
Definition: ppc-linux-nat.c:234
observer.h
check_condition
static int check_condition(CORE_ADDR watch_addr, struct expression *cond, CORE_ADDR *data_value, int *len)
Definition: ppc-linux-nat.c:1891
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struct target_desc * tdesc_powerpc_64l
Definition: powerpc-64l.c:8
regset
Definition: regset.h:34
PPC_FEATURE_HAS_DFP
#define PPC_FEATURE_HAS_DFP
Definition: ppc-linux.h:43
XCNEWVEC
#define XCNEWVEC(T, N)
Definition: poison.h:157
num_memory_accesses
static int num_memory_accesses(struct value *v)
Definition: ppc-linux-nat.c:1843
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Definition: breakpoint.h:238
free_value_chain
void free_value_chain(struct value *v)
Definition: value.c:1678
lval_memory
Definition: defs.h:383
hw_break_tuple
Definition: ppc-linux-nat.c:1323
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#define VEC_iterate(T, V, I, P)
Definition: vec.h:181
max_slots_number
static size_t max_slots_number
Definition: ppc-linux-nat.c:1321
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struct type * check_typedef(struct type *type)
Definition: gdbtypes.c:2421
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void ppc_collect_gregset(const struct regset *regset, const struct regcache *regcache, int regnum, void *gregs, size_t len)
Definition: rs6000-tdep.c:675
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int ppc_vsr0_upper_regnum
Definition: ppc-tdep.h:248
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struct target_desc * tdesc_powerpc_cell64l
Definition: powerpc-cell64l.c:8
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uint64_t addr2
Definition: ppc-linux-nat.c:99
PPC_DEBUG_FEATURE_DATA_BP_RANGE
#define PPC_DEBUG_FEATURE_DATA_BP_RANGE
Definition: ppc-linux-nat.c:89
PPC_MAX_REGISTER_SIZE
#define PPC_MAX_REGISTER_SIZE
Definition: ppc-tdep.h:321
PTRACE_SETEVRREGS
#define PTRACE_SETEVRREGS
Definition: ppc-linux.h:82
PTRACE_GETFPREGS
#define PTRACE_GETFPREGS
Definition: ppc-linux-nat.c:142
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std::unique_ptr< T, xfree_deleter< T > > unique_xmalloc_ptr
Definition: gdb_unique_ptr.h:48
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uint32_t trigger_type
Definition: ppc-linux-nat.c:95
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static void store_fp_regs(const struct regcache *regcache, int tid, int regno)
Definition: ppc-linux-nat.c:1240
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struct target_ops current_target
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static void fetch_altivec_registers(struct regcache *regcache, int tid)
Definition: ppc-linux-nat.c:642
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#define PPC_PTRACE_SETHWDEBUG
Definition: ppc-linux-nat.c:72
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int ppc_vrsave_regnum
Definition: ppc-tdep.h:253
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Definition: target.h:412
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struct target_desc * tdesc_powerpc_altivec32l
Definition: powerpc-altivec32l.c:8
PPC_BREAKPOINT_CONDITION_AND
#define PPC_BREAKPOINT_CONDITION_AND
Definition: ppc-linux-nat.c:117
PPC_BREAKPOINT_TRIGGER_READ
#define PPC_BREAKPOINT_TRIGGER_READ
Definition: ppc-linux-nat.c:105
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int(* to_watchpoint_addr_within_range)(struct target_ops *, CORE_ADDR, CORE_ADDR, int) TARGET_DEFAULT_FUNC(default_watchpoint_addr_within_range)
Definition: target.h:537
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uint32_t data_bp_alignment
Definition: ppc-linux-nat.c:81
PPC_FEATURE_CELL
#define PPC_FEATURE_CELL
Definition: ppc-linux.h:37
PPC_BREAKPOINT_MODE_EXACT
#define PPC_BREAKPOINT_MODE_EXACT
Definition: ppc-linux-nat.c:110
extract_unsigned_integer
static ULONGEST extract_unsigned_integer(const gdb_byte *addr, int len, enum bfd_endian byte_order)
Definition: defs.h:577
gdb_gregset_t
GDB_GREGSET_T gdb_gregset_t
Definition: gregset.h:34
regcache.h
hwdebug_find_thread_points_by_tid
static struct thread_points * hwdebug_find_thread_points_by_tid(int tid, int alloc_new)
Definition: ppc-linux-nat.c:1512
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Definition: ptid.h:35
PT_TRAP
#define PT_TRAP
Definition: ppc-linux.h:29
PPC_FEATURE_BOOKE
#define PPC_FEATURE_BOOKE
Definition: ppc-linux.h:40
gdbarch_tdep::ppc_gp0_regnum
int ppc_gp0_regnum
Definition: ppc-tdep.h:227
target_auxv_search
int target_auxv_search(struct target_ops *ops, CORE_ADDR match, CORE_ADDR *valp)
Definition: auxv.c:375
ppc_linux_trap_reg_p
int ppc_linux_trap_reg_p(struct gdbarch *gdbarch)
Definition: ppc-linux-tdep.c:707
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static void fetch_register(struct regcache *regcache, int tid, int regno)
Definition: ppc-linux-nat.c:492
gdbarch_tdep::ppc_acc_regnum
int ppc_acc_regnum
Definition: ppc-tdep.h:258
expression
Definition: expression.h:78
frame.h
calculate_dvc
static void calculate_dvc(CORE_ADDR addr, int len, CORE_ADDR data_value, uint32_t *condition_mode, uint64_t *condition_value)
Definition: ppc-linux-nat.c:1801
have_ptrace_getvrregs
int have_ptrace_getvrregs
Definition: ppc-linux-nat.c:250
gdb_fpregset_t
GDB_FPREGSET_T gdb_fpregset_t
Definition: gregset.h:35
ppc_debug_info
Definition: ppc-linux-nat.c:75
thread_points::tid
int tid
Definition: ppc-linux-nat.c:1335
set_spe_registers
static void set_spe_registers(int tid, struct gdb_evrregset_t *evrregset)
Definition: ppc-linux-nat.c:895
gdbarch_byte_order
enum bfd_endian gdbarch_byte_order(struct gdbarch *gdbarch)
Definition: gdbarch.c:1509
fetch_all_fp_regs
static int fetch_all_fp_regs(struct regcache *regcache, int tid)
Definition: ppc-linux-nat.c:723
gdbthread.h
fill_fpregset
void fill_fpregset(const struct regcache *regcache, gdb_fpregset_t *fpregsetp, int regno)
Definition: ppc-linux-nat.c:2328
inferior.h
PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE
#define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE
Definition: ppc-linux-nat.c:111
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int(* to_masked_watch_num_registers)(struct target_ops *, CORE_ADDR, CORE_ADDR) TARGET_DEFAULT_RETURN(-1)
Definition: target.h:551
PPC_FEATURE_HAS_ALTIVEC
#define PPC_FEATURE_HAS_ALTIVEC
Definition: ppc-linux.h:49
target_ops::to_remove_mask_watchpoint
int(* to_remove_mask_watchpoint)(struct target_ops *, CORE_ADDR, CORE_ADDR, enum target_hw_bp_type) TARGET_DEFAULT_RETURN(1)
Definition: target.h:527
hw_read
Definition: break-common.h:25
type
Definition: gdbtypes.h:749
PPC_BREAKPOINT_TRIGGER_WRITE
#define PPC_BREAKPOINT_TRIGGER_WRITE
Definition: ppc-linux-nat.c:106
store_all_gp_regs
static int store_all_gp_regs(const struct regcache *regcache, int tid, int regno)
Definition: ppc-linux-nat.c:1140
PPC_PTRACE_DELHWDEBUG
#define PPC_PTRACE_DELHWDEBUG
Definition: ppc-linux-nat.c:73
get_spe_registers
static void get_spe_registers(int tid, struct gdb_evrregset_t *evrregset)
Definition: ppc-linux-nat.c:427
ppc_linux_watchpoint_addr_within_range
static int ppc_linux_watchpoint_addr_within_range(struct target_ops *target, CORE_ADDR addr, CORE_ADDR start, int length)
Definition: ppc-linux-nat.c:2241
saved_dabr_value
static long saved_dabr_value
Definition: ppc-linux-nat.c:1312
gdb_vrregset_t
char gdb_vrregset_t[SIZEOF_VRREGS]
Definition: ppc-linux-nat.c:177
tdesc_powerpc_isa205_altivec64l
struct target_desc * tdesc_powerpc_isa205_altivec64l
Definition: powerpc-isa205-altivec64l.c:8
ppc_collect_fpregset
void ppc_collect_fpregset(const struct regset *regset, const struct regcache *regcache, int regnum, void *fpregs, size_t len)
Definition: rs6000-tdep.c:726
field
Definition: gdbtypes.h:517
gdbarch_register_name
const char * gdbarch_register_name(struct gdbarch *gdbarch, int regnr)
Definition: gdbarch.c:2282
linux_nat_add_target
void linux_nat_add_target(struct target_ops *t)
Definition: linux-nat.c:4804
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int(* to_insert_watchpoint)(struct target_ops *, CORE_ADDR, int, enum target_hw_bp_type, struct expression *) TARGET_DEFAULT_RETURN(-1)
Definition: target.h:519
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static void fetch_ppc_registers(struct regcache *regcache, int tid)
Definition: ppc-linux-nat.c:767
ppc_linux_stopped_by_watchpoint
static int ppc_linux_stopped_by_watchpoint(struct target_ops *ops)
Definition: ppc-linux-nat.c:2234
fetch_altivec_register
static void fetch_altivec_register(struct regcache *regcache, int tid, int regno)
Definition: ppc-linux-nat.c:386
thread_info::ptid
ptid_t ptid
Definition: gdbthread.h:219
gdb.printer.bound_registers.long
long
Definition: bound_registers.py:24
ppc-linux.h
bp_target_info::placed_address
CORE_ADDR placed_address
Definition: breakpoint.h:248
bp_read_watchpoint
Definition: breakpoint.h:77
linux_target
struct target_ops * linux_target(void)
Definition: linux-nat.c:4377
create_watchpoint_request
static void create_watchpoint_request(struct ppc_hw_breakpoint *p, CORE_ADDR addr, int len, enum target_hw_bp_type type, struct expression *cond, int insert)
Definition: ppc-linux-nat.c:1976
ptid_get_lwp
long ptid_get_lwp(const ptid_t &ptid)
Definition: ptid.c:55
gregset.h
PPC_TRAP_REGNUM
Definition: ppc-linux-tdep.h:37
target_ops::to_insert_hw_breakpoint
int(* to_insert_hw_breakpoint)(struct target_ops *, struct gdbarch *, struct bp_target_info *) TARGET_DEFAULT_RETURN(-1)
Definition: target.h:507
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static int get_trigger_type(enum target_hw_bp_type type)
Definition: ppc-linux-nat.c:1692
bptype
bptype
Definition: breakpoint.h:67
ppc_linux_remove_mask_watchpoint
static int ppc_linux_remove_mask_watchpoint(struct target_ops *ops, CORE_ADDR addr, CORE_ADDR mask, enum target_hw_bp_type rw)
Definition: ppc-linux-nat.c:1740
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static int ppc_linux_insert_watchpoint(struct target_ops *self, CORE_ADDR addr, int len, enum target_hw_bp_type type, struct expression *cond)
Definition: ppc-linux-nat.c:2022
VEC_last
#define VEC_last(T, V)
Definition: vec.h:158
gdb_assert
#define gdb_assert(expr)
Definition: gdb_assert.h:32
ppc_linux_thread_exit
static void ppc_linux_thread_exit(struct thread_info *tp, int silent)
Definition: ppc-linux-nat.c:2162
PPC_DEBUG_FEATURE_DATA_BP_MASK
#define PPC_DEBUG_FEATURE_DATA_BP_MASK
Definition: ppc-linux-nat.c:90
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int have_ptrace_getsetfpregs
Definition: ppc-linux-nat.c:268
VEC_empty
#define VEC_empty(T, V)
Definition: vec.h:148
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Definition: regcache.c:221
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Definition: ppc-linux-nat.c:1332
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Definition: powerpc-isa205-32l.c:8
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Definition: ppc-linux-nat.c:2319
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Definition: regcache.c:1004
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Definition: powerpc-vsx64l.c:8
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Definition: regcache.c:164
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Definition: regcache.h:232
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Definition: value.c:1095
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Definition: regcache.c:1085
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Definition: ppc-linux-nat.c:77
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Definition: gdbarch.c:2163
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Definition: config.h:642
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Definition: break-common.h:26
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Definition: powerpc-isa205-vsx64l.c:8
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Definition: ppc-linux-nat.c:1258
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Definition: ppc-linux-nat.c:79
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Definition: ppc-linux.h:74
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Definition: rs6000-tdep.c:174
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Definition: ppc-linux-nat.c:2091
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Definition: ppc-linux-nat.c:236
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Definition: ppc-linux-nat.c:974
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Definition: ppc-linux-nat.c:623
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Definition: rs6000-tdep.c:186
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Definition: target.h:535
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static void store_vsx_register(const struct regcache *regcache, int tid, int regno)
Definition: ppc-linux-nat.c:823
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Definition: value.c:1529
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struct target_desc * tdesc_powerpc_altivec64l
Definition: powerpc-altivec64l.c:8
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static void hwdebug_insert_point(struct ppc_hw_breakpoint *b, int tid)
Definition: ppc-linux-nat.c:1540
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void(* to_store_registers)(struct target_ops *, struct regcache *, int) TARGET_DEFAULT_NORETURN(noprocess())
Definition: target.h:459
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Definition: defs.h:381
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Definition: ppc-linux-nat.c:104
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static int ppc_linux_remove_hw_breakpoint(struct target_ops *self, struct gdbarch *gdbarch, struct bp_target_info *bp_tgt)
Definition: ppc-linux-nat.c:1655
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static int ppc_linux_region_ok_for_hw_watchpoint(struct target_ops *self, CORE_ADDR addr, int len)
Definition: ppc-linux-nat.c:1447
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uint32_t num_instruction_bps
Definition: ppc-linux-nat.c:78
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Definition: gdbthread.h:205
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int ppc_fp0_regnum
Definition: ppc-tdep.h:240
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#define PPC_FEATURE_HAS_VSX
Definition: ppc-linux.h:46
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Definition: breakpoint.h:78
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static void store_altivec_register(const struct regcache *regcache, int tid, int regno)
Definition: ppc-linux-nat.c:852
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Definition: rs6000-tdep.c:511
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Definition: ppc-tdep.h:283
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#define PPC_BREAKPOINT_CONDITION_BE(n)
Definition: ppc-linux-nat.c:123
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#define wordsize
ppc-linux-tdep.h
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struct target_desc * tdesc_powerpc_isa205_altivec32l
Definition: powerpc-isa205-altivec32l.c:8
DEF_VEC_P
DEF_VEC_P(thread_points_p)
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#define PTRACE_GETREGS
Definition: ppc-linux-nat.c:136
linux-nat.h
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static void fetch_vsx_register(struct regcache *regcache, int tid, int regno)
Definition: ppc-linux-nat.c:358
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char gdb_vsxregset_t[SIZEOF_VSXREGS]
Definition: ppc-linux-nat.c:213
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#define PPC_BREAKPOINT_CONDITION_NONE
Definition: ppc-linux-nat.c:116
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Definition: ppc-linux-nat.c:2308
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Definition: ppc-linux-nat.c:98