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/tmp/gdb-8.1/gdb/sparc-tdep.c
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1 /* Target-dependent code for SPARC.
2
3 Copyright (C) 2003-2018 Free Software Foundation, Inc.
4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19
20 #include "defs.h"
21 #include "arch-utils.h"
22 #include "dis-asm.h"
23 #include "dwarf2.h"
24 #include "dwarf2-frame.h"
25 #include "frame.h"
26 #include "frame-base.h"
27 #include "frame-unwind.h"
28 #include "gdbcore.h"
29 #include "gdbtypes.h"
30 #include "inferior.h"
31 #include "symtab.h"
32 #include "objfiles.h"
33 #include "osabi.h"
34 #include "regcache.h"
35 #include "target.h"
36 #include "target-descriptions.h"
37 #include "value.h"
38
39 #include "sparc-tdep.h"
40 #include "sparc-ravenscar-thread.h"
41 #include <algorithm>
42
43 struct regset;
44
45 /* This file implements the SPARC 32-bit ABI as defined by the section
46 "Low-Level System Information" of the SPARC Compliance Definition
47 (SCD) 2.4.1, which is the 32-bit System V psABI for SPARC. The SCD
48 lists changes with respect to the original 32-bit psABI as defined
49 in the "System V ABI, SPARC Processor Supplement".
50
51 Note that if we talk about SunOS, we mean SunOS 4.x, which was
52 BSD-based, which is sometimes (retroactively?) referred to as
53 Solaris 1.x. If we talk about Solaris we mean Solaris 2.x and
54 above (Solaris 7, 8 and 9 are nothing but Solaris 2.7, 2.8 and 2.9
55 suffering from severe version number inflation). Solaris 2.x is
56 also known as SunOS 5.x, since that's what uname(1) says. Solaris
57 2.x is SVR4-based. */
58
59 /* Please use the sparc32_-prefix for 32-bit specific code, the
60 sparc64_-prefix for 64-bit specific code and the sparc_-prefix for
61 code that can handle both. The 64-bit specific code lives in
62 sparc64-tdep.c; don't add any here. */
63
64 /* The SPARC Floating-Point Quad-Precision format is similar to
65 big-endian IA-64 Quad-Precision format. */
66 #define floatformats_sparc_quad floatformats_ia64_quad
67
68 /* The stack pointer is offset from the stack frame by a BIAS of 2047
69 (0x7ff) for 64-bit code. BIAS is likely to be defined on SPARC
70 hosts, so undefine it first. */
71 #undef BIAS
72 #define BIAS 2047
73
74 /* Macros to extract fields from SPARC instructions. */
75 #define X_OP(i) (((i) >> 30) & 0x3)
76 #define X_RD(i) (((i) >> 25) & 0x1f)
77 #define X_A(i) (((i) >> 29) & 1)
78 #define X_COND(i) (((i) >> 25) & 0xf)
79 #define X_OP2(i) (((i) >> 22) & 0x7)
80 #define X_IMM22(i) ((i) & 0x3fffff)
81 #define X_OP3(i) (((i) >> 19) & 0x3f)
82 #define X_RS1(i) (((i) >> 14) & 0x1f)
83 #define X_RS2(i) ((i) & 0x1f)
84 #define X_I(i) (((i) >> 13) & 1)
85 /* Sign extension macros. */
86 #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000)
87 #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000)
88 #define X_DISP10(i) ((((((i) >> 11) && 0x300) | (((i) >> 5) & 0xff)) ^ 0x200) - 0x200)
89 #define X_SIMM13(i) ((((i) & 0x1fff) ^ 0x1000) - 0x1000)
90 /* Macros to identify some instructions. */
91 /* RETURN (RETT in V8) */
92 #define X_RETTURN(i) ((X_OP (i) == 0x2) && (X_OP3 (i) == 0x39))
93
94 /* Fetch the instruction at PC. Instructions are always big-endian
95 even if the processor operates in little-endian mode. */
96
97 unsigned long
98 sparc_fetch_instruction (CORE_ADDR pc)
99 {
100 gdb_byte buf[4];
101 unsigned long insn;
102 int i;
103
104 /* If we can't read the instruction at PC, return zero. */
105 if (target_read_memory (pc, buf, sizeof (buf)))
106 return 0;
107
108 insn = 0;
109 for (i = 0; i < sizeof (buf); i++)
110 insn = (insn << 8) | buf[i];
111 return insn;
112 }
113
114
115 /* Return non-zero if the instruction corresponding to PC is an "unimp"
116 instruction. */
117
118 static int
119 sparc_is_unimp_insn (CORE_ADDR pc)
120 {
121 const unsigned long insn = sparc_fetch_instruction (pc);
122
123 return ((insn & 0xc1c00000) == 0);
124 }
125
126 /* Return non-zero if the instruction corresponding to PC is an
127 "annulled" branch, i.e. the annul bit is set. */
128
129 int
130 sparc_is_annulled_branch_insn (CORE_ADDR pc)
131 {
132 /* The branch instructions featuring an annul bit can be identified
133 by the following bit patterns:
134
135 OP=0
136 OP2=1: Branch on Integer Condition Codes with Prediction (BPcc).
137 OP2=2: Branch on Integer Condition Codes (Bcc).
138 OP2=5: Branch on FP Condition Codes with Prediction (FBfcc).
139 OP2=6: Branch on FP Condition Codes (FBcc).
140 OP2=3 && Bit28=0:
141 Branch on Integer Register with Prediction (BPr).
142
143 This leaves out ILLTRAP (OP2=0), SETHI/NOP (OP2=4) and the V8
144 coprocessor branch instructions (Op2=7). */
145
146 const unsigned long insn = sparc_fetch_instruction (pc);
147 const unsigned op2 = X_OP2 (insn);
148
149 if ((X_OP (insn) == 0)
150 && ((op2 == 1) || (op2 == 2) || (op2 == 5) || (op2 == 6)
151 || ((op2 == 3) && ((insn & 0x10000000) == 0))))
152 return X_A (insn);
153 else
154 return 0;
155 }
156
157 /* OpenBSD/sparc includes StackGhost, which according to the author's
158 website http://stackghost.cerias.purdue.edu "... transparently and
159 automatically protects applications' stack frames; more
160 specifically, it guards the return pointers. The protection
161 mechanisms require no application source or binary modification and
162 imposes only a negligible performance penalty."
163
164 The same website provides the following description of how
165 StackGhost works:
166
167 "StackGhost interfaces with the kernel trap handler that would
168 normally write out registers to the stack and the handler that
169 would read them back in. By XORing a cookie into the
170 return-address saved in the user stack when it is actually written
171 to the stack, and then XOR it out when the return-address is pulled
172 from the stack, StackGhost can cause attacker corrupted return
173 pointers to behave in a manner the attacker cannot predict.
174 StackGhost can also use several unused bits in the return pointer
175 to detect a smashed return pointer and abort the process."
176
177 For GDB this means that whenever we're reading %i7 from a stack
178 frame's window save area, we'll have to XOR the cookie.
179
180 More information on StackGuard can be found on in:
181
182 Mike Frantzen and Mike Shuey. "StackGhost: Hardware Facilitated
183 Stack Protection." 2001. Published in USENIX Security Symposium
184 '01. */
185
186 /* Fetch StackGhost Per-Process XOR cookie. */
187
188 ULONGEST
189 sparc_fetch_wcookie (struct gdbarch *gdbarch)
190 {
191 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
192 struct target_ops *ops = &current_target;
193 gdb_byte buf[8];
194 int len;
195
196 len = target_read (ops, TARGET_OBJECT_WCOOKIE, NULL, buf, 0, 8);
197 if (len == -1)
198 return 0;
199
200 /* We should have either an 32-bit or an 64-bit cookie. */
201 gdb_assert (len == 4 || len == 8);
202
203 return extract_unsigned_integer (buf, len, byte_order);
204 }
205
206
207 /* The functions on this page are intended to be used to classify
208 function arguments. */
209
210 /* Check whether TYPE is "Integral or Pointer". */
211
212 static int
213 sparc_integral_or_pointer_p (const struct type *type)
214 {
215 int len = TYPE_LENGTH (type);
216
217 switch (TYPE_CODE (type))
218 {
219 case TYPE_CODE_INT:
220 case TYPE_CODE_BOOL:
221 case TYPE_CODE_CHAR:
222 case TYPE_CODE_ENUM:
223 case TYPE_CODE_RANGE:
224 /* We have byte, half-word, word and extended-word/doubleword
225 integral types. The doubleword is an extension to the
226 original 32-bit ABI by the SCD 2.4.x. */
227 return (len == 1 || len == 2 || len == 4 || len == 8);
228 case TYPE_CODE_PTR:
229 case TYPE_CODE_REF:
230 case TYPE_CODE_RVALUE_REF:
231 /* Allow either 32-bit or 64-bit pointers. */
232 return (len == 4 || len == 8);
233 default:
234 break;
235 }
236
237 return 0;
238 }
239
240 /* Check whether TYPE is "Floating". */
241
242 static int
243 sparc_floating_p (const struct type *type)
244 {
245 switch (TYPE_CODE (type))
246 {
247 case TYPE_CODE_FLT:
248 {
249 int len = TYPE_LENGTH (type);
250 return (len == 4 || len == 8 || len == 16);
251 }
252 default:
253 break;
254 }
255
256 return 0;
257 }
258
259 /* Check whether TYPE is "Complex Floating". */
260
261 static int
262 sparc_complex_floating_p (const struct type *type)
263 {
264 switch (TYPE_CODE (type))
265 {
266 case TYPE_CODE_COMPLEX:
267 {
268 int len = TYPE_LENGTH (type);
269 return (len == 8 || len == 16 || len == 32);
270 }
271 default:
272 break;
273 }
274
275 return 0;
276 }
277
278 /* Check whether TYPE is "Structure or Union".
279
280 In terms of Ada subprogram calls, arrays are treated the same as
281 struct and union types. So this function also returns non-zero
282 for array types. */
283
284 static int
285 sparc_structure_or_union_p (const struct type *type)
286 {
287 switch (TYPE_CODE (type))
288 {
289 case TYPE_CODE_STRUCT:
290 case TYPE_CODE_UNION:
291 case TYPE_CODE_ARRAY:
292 return 1;
293 default:
294 break;
295 }
296
297 return 0;
298 }
299
300 /* Check whether TYPE is returned on registers. */
301
302 static bool
303 sparc_structure_return_p (const struct type *type)
304 {
305 if (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_LENGTH (type) <= 8)
306 {
307 struct type *t = check_typedef (TYPE_TARGET_TYPE (type));
308
309 if (sparc_floating_p (t) && TYPE_LENGTH (t) == 8)
310 return true;
311 return false;
312 }
313 if (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)
314 return true;
315 return sparc_structure_or_union_p (type);
316 }
317
318 /* Check whether TYPE is passed on registers. */
319
320 static bool
321 sparc_arg_on_registers_p (const struct type *type)
322 {
323 if (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_LENGTH (type) <= 8)
324 {
325 struct type *t = check_typedef (TYPE_TARGET_TYPE (type));
326
327 if (sparc_floating_p (t) && TYPE_LENGTH (t) == 8)
328 return false;
329 return true;
330 }
331 if (sparc_structure_or_union_p (type) || sparc_complex_floating_p (type)
332 || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16))
333 return false;
334 return true;
335 }
336
337 /* Register information. */
338 #define SPARC32_FPU_REGISTERS \
339 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
340 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \
341 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", \
342 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
343 #define SPARC32_CP0_REGISTERS \
344 "y", "psr", "wim", "tbr", "pc", "npc", "fsr", "csr"
345
346 static const char *sparc_core_register_names[] = { SPARC_CORE_REGISTERS };
347 static const char *sparc32_fpu_register_names[] = { SPARC32_FPU_REGISTERS };
348 static const char *sparc32_cp0_register_names[] = { SPARC32_CP0_REGISTERS };
349
350 static const char *sparc32_register_names[] =
351 {
352 SPARC_CORE_REGISTERS,
353 SPARC32_FPU_REGISTERS,
354 SPARC32_CP0_REGISTERS
355 };
356
357 /* Total number of registers. */
358 #define SPARC32_NUM_REGS ARRAY_SIZE (sparc32_register_names)
359
360 /* We provide the aliases %d0..%d30 for the floating registers as
361 "psuedo" registers. */
362
363 static const char *sparc32_pseudo_register_names[] =
364 {
365 "d0", "d2", "d4", "d6", "d8", "d10", "d12", "d14",
366 "d16", "d18", "d20", "d22", "d24", "d26", "d28", "d30"
367 };
368
369 /* Total number of pseudo registers. */
370 #define SPARC32_NUM_PSEUDO_REGS ARRAY_SIZE (sparc32_pseudo_register_names)
371
372 /* Return the name of pseudo register REGNUM. */
373
374 static const char *
375 sparc32_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
376 {
377 regnum -= gdbarch_num_regs (gdbarch);
378
379 if (regnum < SPARC32_NUM_PSEUDO_REGS)
380 return sparc32_pseudo_register_names[regnum];
381
382 internal_error (__FILE__, __LINE__,
383 _("sparc32_pseudo_register_name: bad register number %d"),
384 regnum);
385 }
386
387 /* Return the name of register REGNUM. */
388
389 static const char *
390 sparc32_register_name (struct gdbarch *gdbarch, int regnum)
391 {
392 if (tdesc_has_registers (gdbarch_target_desc (gdbarch)))
393 return tdesc_register_name (gdbarch, regnum);
394
395 if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch))
396 return sparc32_register_names[regnum];
397
398 return sparc32_pseudo_register_name (gdbarch, regnum);
399 }
400
401 /* Construct types for ISA-specific registers. */
402
403 static struct type *
404 sparc_psr_type (struct gdbarch *gdbarch)
405 {
406 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
407
408 if (!tdep->sparc_psr_type)
409 {
410 struct type *type;
411
412 type = arch_flags_type (gdbarch, "builtin_type_sparc_psr", 32);
413 append_flags_type_flag (type, 5, "ET");
414 append_flags_type_flag (type, 6, "PS");
415 append_flags_type_flag (type, 7, "S");
416 append_flags_type_flag (type, 12, "EF");
417 append_flags_type_flag (type, 13, "EC");
418
419 tdep->sparc_psr_type = type;
420 }
421
422 return tdep->sparc_psr_type;
423 }
424
425 static struct type *
426 sparc_fsr_type (struct gdbarch *gdbarch)
427 {
428 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
429
430 if (!tdep->sparc_fsr_type)
431 {
432 struct type *type;
433
434 type = arch_flags_type (gdbarch, "builtin_type_sparc_fsr", 32);
435 append_flags_type_flag (type, 0, "NXA");
436 append_flags_type_flag (type, 1, "DZA");
437 append_flags_type_flag (type, 2, "UFA");
438 append_flags_type_flag (type, 3, "OFA");
439 append_flags_type_flag (type, 4, "NVA");
440 append_flags_type_flag (type, 5, "NXC");
441 append_flags_type_flag (type, 6, "DZC");
442 append_flags_type_flag (type, 7, "UFC");
443 append_flags_type_flag (type, 8, "OFC");
444 append_flags_type_flag (type, 9, "NVC");
445 append_flags_type_flag (type, 22, "NS");
446 append_flags_type_flag (type, 23, "NXM");
447 append_flags_type_flag (type, 24, "DZM");
448 append_flags_type_flag (type, 25, "UFM");
449 append_flags_type_flag (type, 26, "OFM");
450 append_flags_type_flag (type, 27, "NVM");
451
452 tdep->sparc_fsr_type = type;
453 }
454
455 return tdep->sparc_fsr_type;
456 }
457
458 /* Return the GDB type object for the "standard" data type of data in
459 pseudo register REGNUM. */
460
461 static struct type *
462 sparc32_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
463 {
464 regnum -= gdbarch_num_regs (gdbarch);
465
466 if (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM)
467 return builtin_type (gdbarch)->builtin_double;
468
469 internal_error (__FILE__, __LINE__,
470 _("sparc32_pseudo_register_type: bad register number %d"),
471 regnum);
472 }
473
474 /* Return the GDB type object for the "standard" data type of data in
475 register REGNUM. */
476
477 static struct type *
478 sparc32_register_type (struct gdbarch *gdbarch, int regnum)
479 {
480 if (tdesc_has_registers (gdbarch_target_desc (gdbarch)))
481 return tdesc_register_type (gdbarch, regnum);
482
483 if (regnum >= SPARC_F0_REGNUM && regnum <= SPARC_F31_REGNUM)
484 return builtin_type (gdbarch)->builtin_float;
485
486 if (regnum == SPARC_SP_REGNUM || regnum == SPARC_FP_REGNUM)
487 return builtin_type (gdbarch)->builtin_data_ptr;
488
489 if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM)
490 return builtin_type (gdbarch)->builtin_func_ptr;
491
492 if (regnum == SPARC32_PSR_REGNUM)
493 return sparc_psr_type (gdbarch);
494
495 if (regnum == SPARC32_FSR_REGNUM)
496 return sparc_fsr_type (gdbarch);
497
498 if (regnum >= gdbarch_num_regs (gdbarch))
499 return sparc32_pseudo_register_type (gdbarch, regnum);
500
501 return builtin_type (gdbarch)->builtin_int32;
502 }
503
504 static enum register_status
505 sparc32_pseudo_register_read (struct gdbarch *gdbarch,
506 struct regcache *regcache,
507 int regnum, gdb_byte *buf)
508 {
509 enum register_status status;
510
511 regnum -= gdbarch_num_regs (gdbarch);
512 gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM);
513
514 regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM);
515 status = regcache_raw_read (regcache, regnum, buf);
516 if (status == REG_VALID)
517 status = regcache_raw_read (regcache, regnum + 1, buf + 4);
518 return status;
519 }
520
521 static void
522 sparc32_pseudo_register_write (struct gdbarch *gdbarch,
523 struct regcache *regcache,
524 int regnum, const gdb_byte *buf)
525 {
526 regnum -= gdbarch_num_regs (gdbarch);
527 gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM);
528
529 regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM);
530 regcache_raw_write (regcache, regnum, buf);
531 regcache_raw_write (regcache, regnum + 1, buf + 4);
532 }
533
534 /* Implement the stack_frame_destroyed_p gdbarch method. */
535
536 int
537 sparc_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
538 {
539 /* This function must return true if we are one instruction after an
540 instruction that destroyed the stack frame of the current
541 function. The SPARC instructions used to restore the callers
542 stack frame are RESTORE and RETURN/RETT.
543
544 Of these RETURN/RETT is a branch instruction and thus we return
545 true if we are in its delay slot.
546
547 RESTORE is almost always found in the delay slot of a branch
548 instruction that transfers control to the caller, such as JMPL.
549 Thus the next instruction is in the caller frame and we don't
550 need to do anything about it. */
551
552 unsigned int insn = sparc_fetch_instruction (pc - 4);
553
554 return X_RETTURN (insn);
555 }
556
557
558 static CORE_ADDR
559 sparc32_frame_align (struct gdbarch *gdbarch, CORE_ADDR address)
560 {
561 /* The ABI requires double-word alignment. */
562 return address & ~0x7;
563 }
564
565 static CORE_ADDR
566 sparc32_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp,
567 CORE_ADDR funcaddr,
568 struct value **args, int nargs,
569 struct type *value_type,
570 CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
571 struct regcache *regcache)
572 {
573 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
574
575 *bp_addr = sp - 4;
576 *real_pc = funcaddr;
577
578 if (using_struct_return (gdbarch, NULL, value_type))
579 {
580 gdb_byte buf[4];
581
582 /* This is an UNIMP instruction. */
583 store_unsigned_integer (buf, 4, byte_order,
584 TYPE_LENGTH (value_type) & 0x1fff);
585 write_memory (sp - 8, buf, 4);
586 return sp - 8;
587 }
588
589 return sp - 4;
590 }
591
592 static CORE_ADDR
593 sparc32_store_arguments (struct regcache *regcache, int nargs,
594 struct value **args, CORE_ADDR sp,
595 int struct_return, CORE_ADDR struct_addr)
596 {
597 struct gdbarch *gdbarch = regcache->arch ();
598 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
599 /* Number of words in the "parameter array". */
600 int num_elements = 0;
601 int element = 0;
602 int i;
603
604 for (i = 0; i < nargs; i++)
605 {
606 struct type *type = value_type (args[i]);
607 int len = TYPE_LENGTH (type);
608
609 if (!sparc_arg_on_registers_p (type))
610 {
611 /* Structure, Union and Quad-Precision Arguments. */
612 sp -= len;
613
614 /* Use doubleword alignment for these values. That's always
615 correct, and wasting a few bytes shouldn't be a problem. */
616 sp &= ~0x7;
617
618 write_memory (sp, value_contents (args[i]), len);
619 args[i] = value_from_pointer (lookup_pointer_type (type), sp);
620 num_elements++;
621 }
622 else if (sparc_floating_p (type))
623 {
624 /* Floating arguments. */
625 gdb_assert (len == 4 || len == 8);
626 num_elements += (len / 4);
627 }
628 else
629 {
630 /* Integral and pointer arguments. */
631 gdb_assert (sparc_integral_or_pointer_p (type)
632 || (TYPE_CODE (type) == TYPE_CODE_ARRAY && len <= 8));
633 num_elements += ((len + 3) / 4);
634 }
635 }
636
637 /* Always allocate at least six words. */
638 sp -= std::max (6, num_elements) * 4;
639
640 /* The psABI says that "Software convention requires space for the
641 struct/union return value pointer, even if the word is unused." */
642 sp -= 4;
643
644 /* The psABI says that "Although software convention and the
645 operating system require every stack frame to be doubleword
646 aligned." */
647 sp &= ~0x7;
648
649 for (i = 0; i < nargs; i++)
650 {
651 const bfd_byte *valbuf = value_contents (args[i]);
652 struct type *type = value_type (args[i]);
653 int len = TYPE_LENGTH (type);
654 gdb_byte buf[4];
655
656 if (len < 4)
657 {
658 memset (buf, 0, 4 - len);
659 memcpy (buf + 4 - len, valbuf, len);
660 valbuf = buf;
661 len = 4;
662 }
663
664 gdb_assert (len == 4 || len == 8);
665
666 if (element < 6)
667 {
668 int regnum = SPARC_O0_REGNUM + element;
669
670 regcache_cooked_write (regcache, regnum, valbuf);
671 if (len > 4 && element < 5)
672 regcache_cooked_write (regcache, regnum + 1, valbuf + 4);
673 }
674
675 /* Always store the argument in memory. */
676 write_memory (sp + 4 + element * 4, valbuf, len);
677 element += len / 4;
678 }
679
680 gdb_assert (element == num_elements);
681
682 if (struct_return)
683 {
684 gdb_byte buf[4];
685
686 store_unsigned_integer (buf, 4, byte_order, struct_addr);
687 write_memory (sp, buf, 4);
688 }
689
690 return sp;
691 }
692
693 static CORE_ADDR
694 sparc32_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
695 struct regcache *regcache, CORE_ADDR bp_addr,
696 int nargs, struct value **args, CORE_ADDR sp,
697 int struct_return, CORE_ADDR struct_addr)
698 {
699 CORE_ADDR call_pc = (struct_return ? (bp_addr - 12) : (bp_addr - 8));
700
701 /* Set return address. */
702 regcache_cooked_write_unsigned (regcache, SPARC_O7_REGNUM, call_pc);
703
704 /* Set up function arguments. */
705 sp = sparc32_store_arguments (regcache, nargs, args, sp,
706 struct_return, struct_addr);
707
708 /* Allocate the 16-word window save area. */
709 sp -= 16 * 4;
710
711 /* Stack should be doubleword aligned at this point. */
712 gdb_assert (sp % 8 == 0);
713
714 /* Finally, update the stack pointer. */
715 regcache_cooked_write_unsigned (regcache, SPARC_SP_REGNUM, sp);
716
717 return sp;
718 }
719
720
721 /* Use the program counter to determine the contents and size of a
722 breakpoint instruction. Return a pointer to a string of bytes that
723 encode a breakpoint instruction, store the length of the string in
724 *LEN and optionally adjust *PC to point to the correct memory
725 location for inserting the breakpoint. */
726 constexpr gdb_byte sparc_break_insn[] = { 0x91, 0xd0, 0x20, 0x01 };
727
728 typedef BP_MANIPULATION (sparc_break_insn) sparc_breakpoint;
729
730
731 /* Allocate and initialize a frame cache. */
732
733 static struct sparc_frame_cache *
734 sparc_alloc_frame_cache (void)
735 {
736 struct sparc_frame_cache *cache;
737
738 cache = FRAME_OBSTACK_ZALLOC (struct sparc_frame_cache);
739
740 /* Base address. */
741 cache->base = 0;
742 cache->pc = 0;
743
744 /* Frameless until proven otherwise. */
745 cache->frameless_p = 1;
746 cache->frame_offset = 0;
747 cache->saved_regs_mask = 0;
748 cache->copied_regs_mask = 0;
749 cache->struct_return_p = 0;
750
751 return cache;
752 }
753
754 /* GCC generates several well-known sequences of instructions at the begining
755 of each function prologue when compiling with -fstack-check. If one of
756 such sequences starts at START_PC, then return the address of the
757 instruction immediately past this sequence. Otherwise, return START_PC. */
758
759 static CORE_ADDR
760 sparc_skip_stack_check (const CORE_ADDR start_pc)
761 {
762 CORE_ADDR pc = start_pc;
763 unsigned long insn;
764 int probing_loop = 0;
765
766 /* With GCC, all stack checking sequences begin with the same two
767 instructions, plus an optional one in the case of a probing loop:
768
769 sethi <some immediate>, %g1
770 sub %sp, %g1, %g1
771
772 or:
773
774 sethi <some immediate>, %g1
775 sethi <some immediate>, %g4
776 sub %sp, %g1, %g1
777
778 or:
779
780 sethi <some immediate>, %g1
781 sub %sp, %g1, %g1
782 sethi <some immediate>, %g4
783
784 If the optional instruction is found (setting g4), assume that a
785 probing loop will follow. */
786
787 /* sethi <some immediate>, %g1 */
788 insn = sparc_fetch_instruction (pc);
789 pc = pc + 4;
790 if (!(X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 1))
791 return start_pc;
792
793 /* optional: sethi <some immediate>, %g4 */
794 insn = sparc_fetch_instruction (pc);
795 pc = pc + 4;
796 if (X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 4)
797 {
798 probing_loop = 1;
799 insn = sparc_fetch_instruction (pc);
800 pc = pc + 4;
801 }
802
803 /* sub %sp, %g1, %g1 */
804 if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn)
805 && X_RD (insn) == 1 && X_RS1 (insn) == 14 && X_RS2 (insn) == 1))
806 return start_pc;
807
808 insn = sparc_fetch_instruction (pc);
809 pc = pc + 4;
810
811 /* optional: sethi <some immediate>, %g4 */
812 if (X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 4)
813 {
814 probing_loop = 1;
815 insn = sparc_fetch_instruction (pc);
816 pc = pc + 4;
817 }
818
819 /* First possible sequence:
820 [first two instructions above]
821 clr [%g1 - some immediate] */
822
823 /* clr [%g1 - some immediate] */
824 if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn)
825 && X_RS1 (insn) == 1 && X_RD (insn) == 0)
826 {
827 /* Valid stack-check sequence, return the new PC. */
828 return pc;
829 }
830
831 /* Second possible sequence: A small number of probes.
832 [first two instructions above]
833 clr [%g1]
834 add %g1, -<some immediate>, %g1
835 clr [%g1]
836 [repeat the two instructions above any (small) number of times]
837 clr [%g1 - some immediate] */
838
839 /* clr [%g1] */
840 else if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn)
841 && X_RS1 (insn) == 1 && X_RD (insn) == 0)
842 {
843 while (1)
844 {
845 /* add %g1, -<some immediate>, %g1 */
846 insn = sparc_fetch_instruction (pc);
847 pc = pc + 4;
848 if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn)
849 && X_RS1 (insn) == 1 && X_RD (insn) == 1))
850 break;
851
852 /* clr [%g1] */
853 insn = sparc_fetch_instruction (pc);
854 pc = pc + 4;
855 if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn)
856 && X_RD (insn) == 0 && X_RS1 (insn) == 1))
857 return start_pc;
858 }
859
860 /* clr [%g1 - some immediate] */
861 if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn)
862 && X_RS1 (insn) == 1 && X_RD (insn) == 0))
863 return start_pc;
864
865 /* We found a valid stack-check sequence, return the new PC. */
866 return pc;
867 }
868
869 /* Third sequence: A probing loop.
870 [first three instructions above]
871 sub %g1, %g4, %g4
872 cmp %g1, %g4
873 be <disp>
874 add %g1, -<some immediate>, %g1
875 ba <disp>
876 clr [%g1]
877
878 And an optional last probe for the remainder:
879
880 clr [%g4 - some immediate] */
881
882 if (probing_loop)
883 {
884 /* sub %g1, %g4, %g4 */
885 if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn)
886 && X_RD (insn) == 4 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4))
887 return start_pc;
888
889 /* cmp %g1, %g4 */
890 insn = sparc_fetch_instruction (pc);
891 pc = pc + 4;
892 if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x14 && !X_I(insn)
893 && X_RD (insn) == 0 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4))
894 return start_pc;
895
896 /* be <disp> */
897 insn = sparc_fetch_instruction (pc);
898 pc = pc + 4;
899 if (!(X_OP (insn) == 0 && X_COND (insn) == 0x1))
900 return start_pc;
901
902 /* add %g1, -<some immediate>, %g1 */
903 insn = sparc_fetch_instruction (pc);
904 pc = pc + 4;
905 if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn)
906 && X_RS1 (insn) == 1 && X_RD (insn) == 1))
907 return start_pc;
908
909 /* ba <disp> */
910 insn = sparc_fetch_instruction (pc);
911 pc = pc + 4;
912 if (!(X_OP (insn) == 0 && X_COND (insn) == 0x8))
913 return start_pc;
914
915 /* clr [%g1] (st %g0, [%g1] or st %g0, [%g1+0]) */
916 insn = sparc_fetch_instruction (pc);
917 pc = pc + 4;
918 if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4
919 && X_RD (insn) == 0 && X_RS1 (insn) == 1
920 && (!X_I(insn) || X_SIMM13 (insn) == 0)))
921 return start_pc;
922
923 /* We found a valid stack-check sequence, return the new PC. */
924
925 /* optional: clr [%g4 - some immediate] */
926 insn = sparc_fetch_instruction (pc);
927 pc = pc + 4;
928 if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn)
929 && X_RS1 (insn) == 4 && X_RD (insn) == 0))
930 return pc - 4;
931 else
932 return pc;
933 }
934
935 /* No stack check code in our prologue, return the start_pc. */
936 return start_pc;
937 }
938
939 /* Record the effect of a SAVE instruction on CACHE. */
940
941 void
942 sparc_record_save_insn (struct sparc_frame_cache *cache)
943 {
944 /* The frame is set up. */
945 cache->frameless_p = 0;
946
947 /* The frame pointer contains the CFA. */
948 cache->frame_offset = 0;
949
950 /* The `local' and `in' registers are all saved. */
951 cache->saved_regs_mask = 0xffff;
952
953 /* The `out' registers are all renamed. */
954 cache->copied_regs_mask = 0xff;
955 }
956
957 /* Do a full analysis of the prologue at PC and update CACHE accordingly.
958 Bail out early if CURRENT_PC is reached. Return the address where
959 the analysis stopped.
960
961 We handle both the traditional register window model and the single
962 register window (aka flat) model. */
963
964 CORE_ADDR
965 sparc_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,
966 CORE_ADDR current_pc, struct sparc_frame_cache *cache)
967 {
968 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
969 unsigned long insn;
970 int offset = 0;
971 int dest = -1;
972
973 pc = sparc_skip_stack_check (pc);
974
975 if (current_pc <= pc)
976 return current_pc;
977
978 /* We have to handle to "Procedure Linkage Table" (PLT) special. On
979 SPARC the linker usually defines a symbol (typically
980 _PROCEDURE_LINKAGE_TABLE_) at the start of the .plt section.
981 This symbol makes us end up here with PC pointing at the start of
982 the PLT and CURRENT_PC probably pointing at a PLT entry. If we
983 would do our normal prologue analysis, we would probably conclude
984 that we've got a frame when in reality we don't, since the
985 dynamic linker patches up the first PLT with some code that
986 starts with a SAVE instruction. Patch up PC such that it points
987 at the start of our PLT entry. */
988 if (tdep->plt_entry_size > 0 && in_plt_section (current_pc))
989 pc = current_pc - ((current_pc - pc) % tdep->plt_entry_size);
990
991 insn = sparc_fetch_instruction (pc);
992
993 /* Recognize store insns and record their sources. */
994 while (X_OP (insn) == 3
995 && (X_OP3 (insn) == 0x4 /* stw */
996 || X_OP3 (insn) == 0x7 /* std */
997 || X_OP3 (insn) == 0xe) /* stx */
998 && X_RS1 (insn) == SPARC_SP_REGNUM)
999 {
1000 int regnum = X_RD (insn);
1001
1002 /* Recognize stores into the corresponding stack slots. */
1003 if (regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM
1004 && ((X_I (insn)
1005 && X_SIMM13 (insn) == (X_OP3 (insn) == 0xe
1006 ? (regnum - SPARC_L0_REGNUM) * 8 + BIAS
1007 : (regnum - SPARC_L0_REGNUM) * 4))
1008 || (!X_I (insn) && regnum == SPARC_L0_REGNUM)))
1009 {
1010 cache->saved_regs_mask |= (1 << (regnum - SPARC_L0_REGNUM));
1011 if (X_OP3 (insn) == 0x7)
1012 cache->saved_regs_mask |= (1 << (regnum + 1 - SPARC_L0_REGNUM));
1013 }
1014
1015 offset += 4;
1016
1017 insn = sparc_fetch_instruction (pc + offset);
1018 }
1019
1020 /* Recognize a SETHI insn and record its destination. */
1021 if (X_OP (insn) == 0 && X_OP2 (insn) == 0x04)
1022 {
1023 dest = X_RD (insn);
1024 offset += 4;
1025
1026 insn = sparc_fetch_instruction (pc + offset);
1027 }
1028
1029 /* Allow for an arithmetic operation on DEST or %g1. */
1030 if (X_OP (insn) == 2 && X_I (insn)
1031 && (X_RD (insn) == 1 || X_RD (insn) == dest))
1032 {
1033 offset += 4;
1034
1035 insn = sparc_fetch_instruction (pc + offset);
1036 }
1037
1038 /* Check for the SAVE instruction that sets up the frame. */
1039 if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3c)
1040 {
1041 sparc_record_save_insn (cache);
1042 offset += 4;
1043 return pc + offset;
1044 }
1045
1046 /* Check for an arithmetic operation on %sp. */
1047 if (X_OP (insn) == 2
1048 && (X_OP3 (insn) == 0 || X_OP3 (insn) == 0x4)
1049 && X_RS1 (insn) == SPARC_SP_REGNUM
1050 && X_RD (insn) == SPARC_SP_REGNUM)
1051 {
1052 if (X_I (insn))
1053 {
1054 cache->frame_offset = X_SIMM13 (insn);
1055 if (X_OP3 (insn) == 0)
1056 cache->frame_offset = -cache->frame_offset;
1057 }
1058 offset += 4;
1059
1060 insn = sparc_fetch_instruction (pc + offset);
1061
1062 /* Check for an arithmetic operation that sets up the frame. */
1063 if (X_OP (insn) == 2
1064 && (X_OP3 (insn) == 0 || X_OP3 (insn) == 0x4)
1065 && X_RS1 (insn) == SPARC_SP_REGNUM
1066 && X_RD (insn) == SPARC_FP_REGNUM)
1067 {
1068 cache->frameless_p = 0;
1069 cache->frame_offset = 0;
1070 /* We could check that the amount subtracted to %sp above is the
1071 same as the one added here, but this seems superfluous. */
1072 cache->copied_regs_mask |= 0x40;
1073 offset += 4;
1074
1075 insn = sparc_fetch_instruction (pc + offset);
1076 }
1077
1078 /* Check for a move (or) operation that copies the return register. */
1079 if (X_OP (insn) == 2
1080 && X_OP3 (insn) == 0x2
1081 && !X_I (insn)
1082 && X_RS1 (insn) == SPARC_G0_REGNUM
1083 && X_RS2 (insn) == SPARC_O7_REGNUM
1084 && X_RD (insn) == SPARC_I7_REGNUM)
1085 {
1086 cache->copied_regs_mask |= 0x80;
1087 offset += 4;
1088 }
1089
1090 return pc + offset;
1091 }
1092
1093 return pc;
1094 }
1095
1096 static CORE_ADDR
1097 sparc_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame)
1098 {
1099 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1100 return frame_unwind_register_unsigned (this_frame, tdep->pc_regnum);
1101 }
1102
1103 /* Return PC of first real instruction of the function starting at
1104 START_PC. */
1105
1106 static CORE_ADDR
1107 sparc32_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
1108 {
1109 struct symtab_and_line sal;
1110 CORE_ADDR func_start, func_end;
1111 struct sparc_frame_cache cache;
1112
1113 /* This is the preferred method, find the end of the prologue by
1114 using the debugging information. */
1115 if (find_pc_partial_function (start_pc, NULL, &func_start, &func_end))
1116 {
1117 sal = find_pc_line (func_start, 0);
1118
1119 if (sal.end < func_end
1120 && start_pc <= sal.end)
1121 return sal.end;
1122 }
1123
1124 start_pc = sparc_analyze_prologue (gdbarch, start_pc, 0xffffffffUL, &cache);
1125
1126 /* The psABI says that "Although the first 6 words of arguments
1127 reside in registers, the standard stack frame reserves space for
1128 them.". It also suggests that a function may use that space to
1129 "write incoming arguments 0 to 5" into that space, and that's
1130 indeed what GCC seems to be doing. In that case GCC will
1131 generate debug information that points to the stack slots instead
1132 of the registers, so we should consider the instructions that
1133 write out these incoming arguments onto the stack. */
1134
1135 while (1)
1136 {
1137 unsigned long insn = sparc_fetch_instruction (start_pc);
1138
1139 /* Recognize instructions that store incoming arguments into the
1140 corresponding stack slots. */
1141 if (X_OP (insn) == 3 && (X_OP3 (insn) & 0x3c) == 0x04
1142 && X_I (insn) && X_RS1 (insn) == SPARC_FP_REGNUM)
1143 {
1144 int regnum = X_RD (insn);
1145
1146 /* Case of arguments still in %o[0..5]. */
1147 if (regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O5_REGNUM
1148 && !(cache.copied_regs_mask & (1 << (regnum - SPARC_O0_REGNUM)))
1149 && X_SIMM13 (insn) == 68 + (regnum - SPARC_O0_REGNUM) * 4)
1150 {
1151 start_pc += 4;
1152 continue;
1153 }
1154
1155 /* Case of arguments copied into %i[0..5]. */
1156 if (regnum >= SPARC_I0_REGNUM && regnum <= SPARC_I5_REGNUM
1157 && (cache.copied_regs_mask & (1 << (regnum - SPARC_I0_REGNUM)))
1158 && X_SIMM13 (insn) == 68 + (regnum - SPARC_I0_REGNUM) * 4)
1159 {
1160 start_pc += 4;
1161 continue;
1162 }
1163 }
1164
1165 break;
1166 }
1167
1168 return start_pc;
1169 }
1170
1171 /* Normal frames. */
1172
1173 struct sparc_frame_cache *
1174 sparc_frame_cache (struct frame_info *this_frame, void **this_cache)
1175 {
1176 struct sparc_frame_cache *cache;
1177
1178 if (*this_cache)
1179 return (struct sparc_frame_cache *) *this_cache;
1180
1181 cache = sparc_alloc_frame_cache ();
1182 *this_cache = cache;
1183
1184 cache->pc = get_frame_func (this_frame);
1185 if (cache->pc != 0)
1186 sparc_analyze_prologue (get_frame_arch (this_frame), cache->pc,
1187 get_frame_pc (this_frame), cache);
1188
1189 if (cache->frameless_p)
1190 {
1191 /* This function is frameless, so %fp (%i6) holds the frame
1192 pointer for our calling frame. Use %sp (%o6) as this frame's
1193 base address. */
1194 cache->base =
1195 get_frame_register_unsigned (this_frame, SPARC_SP_REGNUM);
1196 }
1197 else
1198 {
1199 /* For normal frames, %fp (%i6) holds the frame pointer, the
1200 base address for the current stack frame. */
1201 cache->base =
1202 get_frame_register_unsigned (this_frame, SPARC_FP_REGNUM);
1203 }
1204
1205 cache->base += cache->frame_offset;
1206
1207 if (cache->base & 1)
1208 cache->base += BIAS;
1209
1210 return cache;
1211 }
1212
1213 static int
1214 sparc32_struct_return_from_sym (struct symbol *sym)
1215 {
1216 struct type *type = check_typedef (SYMBOL_TYPE (sym));
1217 enum type_code code = TYPE_CODE (type);
1218
1219 if (code == TYPE_CODE_FUNC || code == TYPE_CODE_METHOD)
1220 {
1221 type = check_typedef (TYPE_TARGET_TYPE (type));
1222 if (sparc_structure_or_union_p (type)
1223 || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16))
1224 return 1;
1225 }
1226
1227 return 0;
1228 }
1229
1230 struct sparc_frame_cache *
1231 sparc32_frame_cache (struct frame_info *this_frame, void **this_cache)
1232 {
1233 struct sparc_frame_cache *cache;
1234 struct symbol *sym;
1235
1236 if (*this_cache)
1237 return (struct sparc_frame_cache *) *this_cache;
1238
1239 cache = sparc_frame_cache (this_frame, this_cache);
1240
1241 sym = find_pc_function (cache->pc);
1242 if (sym)
1243 {
1244 cache->struct_return_p = sparc32_struct_return_from_sym (sym);
1245 }
1246 else
1247 {
1248 /* There is no debugging information for this function to
1249 help us determine whether this function returns a struct
1250 or not. So we rely on another heuristic which is to check
1251 the instruction at the return address and see if this is
1252 an "unimp" instruction. If it is, then it is a struct-return
1253 function. */
1254 CORE_ADDR pc;
1255 int regnum =
1256 (cache->copied_regs_mask & 0x80) ? SPARC_I7_REGNUM : SPARC_O7_REGNUM;
1257
1258 pc = get_frame_register_unsigned (this_frame, regnum) + 8;
1259 if (sparc_is_unimp_insn (pc))
1260 cache->struct_return_p = 1;
1261 }
1262
1263 return cache;
1264 }
1265
1266 static void
1267 sparc32_frame_this_id (struct frame_info *this_frame, void **this_cache,
1268 struct frame_id *this_id)
1269 {
1270 struct sparc_frame_cache *cache =
1271 sparc32_frame_cache (this_frame, this_cache);
1272
1273 /* This marks the outermost frame. */
1274 if (cache->base == 0)
1275 return;
1276
1277 (*this_id) = frame_id_build (cache->base, cache->pc);
1278 }
1279
1280 static struct value *
1281 sparc32_frame_prev_register (struct frame_info *this_frame,
1282 void **this_cache, int regnum)
1283 {
1284 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1285 struct sparc_frame_cache *cache =
1286 sparc32_frame_cache (this_frame, this_cache);
1287
1288 if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM)
1289 {
1290 CORE_ADDR pc = (regnum == SPARC32_NPC_REGNUM) ? 4 : 0;
1291
1292 /* If this functions has a Structure, Union or Quad-Precision
1293 return value, we have to skip the UNIMP instruction that encodes
1294 the size of the structure. */
1295 if (cache->struct_return_p)
1296 pc += 4;
1297
1298 regnum =
1299 (cache->copied_regs_mask & 0x80) ? SPARC_I7_REGNUM : SPARC_O7_REGNUM;
1300 pc += get_frame_register_unsigned (this_frame, regnum) + 8;
1301 return frame_unwind_got_constant (this_frame, regnum, pc);
1302 }
1303
1304 /* Handle StackGhost. */
1305 {
1306 ULONGEST wcookie = sparc_fetch_wcookie (gdbarch);
1307
1308 if (wcookie != 0 && !cache->frameless_p && regnum == SPARC_I7_REGNUM)
1309 {
1310 CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4;
1311 ULONGEST i7;
1312
1313 /* Read the value in from memory. */
1314 i7 = get_frame_memory_unsigned (this_frame, addr, 4);
1315 return frame_unwind_got_constant (this_frame, regnum, i7 ^ wcookie);
1316 }
1317 }
1318
1319 /* The previous frame's `local' and `in' registers may have been saved
1320 in the register save area. */
1321 if (regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM
1322 && (cache->saved_regs_mask & (1 << (regnum - SPARC_L0_REGNUM))))
1323 {
1324 CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4;
1325
1326 return frame_unwind_got_memory (this_frame, regnum, addr);
1327 }
1328
1329 /* The previous frame's `out' registers may be accessible as the current
1330 frame's `in' registers. */
1331 if (regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O7_REGNUM
1332 && (cache->copied_regs_mask & (1 << (regnum - SPARC_O0_REGNUM))))
1333 regnum += (SPARC_I0_REGNUM - SPARC_O0_REGNUM);
1334
1335 return frame_unwind_got_register (this_frame, regnum, regnum);
1336 }
1337
1338 static const struct frame_unwind sparc32_frame_unwind =
1339 {
1340 NORMAL_FRAME,
1341 default_frame_unwind_stop_reason,
1342 sparc32_frame_this_id,
1343 sparc32_frame_prev_register,
1344 NULL,
1345 default_frame_sniffer
1346 };
1347
1348
1349 static CORE_ADDR
1350 sparc32_frame_base_address (struct frame_info *this_frame, void **this_cache)
1351 {
1352 struct sparc_frame_cache *cache =
1353 sparc32_frame_cache (this_frame, this_cache);
1354
1355 return cache->base;
1356 }
1357
1358 static const struct frame_base sparc32_frame_base =
1359 {
1360 &sparc32_frame_unwind,
1361 sparc32_frame_base_address,
1362 sparc32_frame_base_address,
1363 sparc32_frame_base_address
1364 };
1365
1366 static struct frame_id
1367 sparc_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1368 {
1369 CORE_ADDR sp;
1370
1371 sp = get_frame_register_unsigned (this_frame, SPARC_SP_REGNUM);
1372 if (sp & 1)
1373 sp += BIAS;
1374 return frame_id_build (sp, get_frame_pc (this_frame));
1375 }
1376
1377
1378 /* Extract a function return value of TYPE from REGCACHE, and copy
1379 that into VALBUF. */
1380
1381 static void
1382 sparc32_extract_return_value (struct type *type, struct regcache *regcache,
1383 gdb_byte *valbuf)
1384 {
1385 int len = TYPE_LENGTH (type);
1386 gdb_byte buf[32];
1387
1388 gdb_assert (!sparc_structure_return_p (type));
1389
1390 if (sparc_floating_p (type) || sparc_complex_floating_p (type)
1391 || TYPE_CODE (type) == TYPE_CODE_ARRAY)
1392 {
1393 /* Floating return values. */
1394 regcache_cooked_read (regcache, SPARC_F0_REGNUM, buf);
1395 if (len > 4)
1396 regcache_cooked_read (regcache, SPARC_F1_REGNUM, buf + 4);
1397 if (len > 8)
1398 {
1399 regcache_cooked_read (regcache, SPARC_F2_REGNUM, buf + 8);
1400 regcache_cooked_read (regcache, SPARC_F3_REGNUM, buf + 12);
1401 }
1402 if (len > 16)
1403 {
1404 regcache_cooked_read (regcache, SPARC_F4_REGNUM, buf + 16);
1405 regcache_cooked_read (regcache, SPARC_F5_REGNUM, buf + 20);
1406 regcache_cooked_read (regcache, SPARC_F6_REGNUM, buf + 24);
1407 regcache_cooked_read (regcache, SPARC_F7_REGNUM, buf + 28);
1408 }
1409 memcpy (valbuf, buf, len);
1410 }
1411 else
1412 {
1413 /* Integral and pointer return values. */
1414 gdb_assert (sparc_integral_or_pointer_p (type));
1415
1416 regcache_cooked_read (regcache, SPARC_O0_REGNUM, buf);
1417 if (len > 4)
1418 {
1419 regcache_cooked_read (regcache, SPARC_O1_REGNUM, buf + 4);
1420 gdb_assert (len == 8);
1421 memcpy (valbuf, buf, 8);
1422 }
1423 else
1424 {
1425 /* Just stripping off any unused bytes should preserve the
1426 signed-ness just fine. */
1427 memcpy (valbuf, buf + 4 - len, len);
1428 }
1429 }
1430 }
1431
1432 /* Store the function return value of type TYPE from VALBUF into
1433 REGCACHE. */
1434
1435 static void
1436 sparc32_store_return_value (struct type *type, struct regcache *regcache,
1437 const gdb_byte *valbuf)
1438 {
1439 int len = TYPE_LENGTH (type);
1440 gdb_byte buf[32];
1441
1442 gdb_assert (!sparc_structure_return_p (type));
1443
1444 if (sparc_floating_p (type) || sparc_complex_floating_p (type))
1445 {
1446 /* Floating return values. */
1447 memcpy (buf, valbuf, len);
1448 regcache_cooked_write (regcache, SPARC_F0_REGNUM, buf);
1449 if (len > 4)
1450 regcache_cooked_write (regcache, SPARC_F1_REGNUM, buf + 4);
1451 if (len > 8)
1452 {
1453 regcache_cooked_write (regcache, SPARC_F2_REGNUM, buf + 8);
1454 regcache_cooked_write (regcache, SPARC_F3_REGNUM, buf + 12);
1455 }
1456 if (len > 16)
1457 {
1458 regcache_cooked_write (regcache, SPARC_F4_REGNUM, buf + 16);
1459 regcache_cooked_write (regcache, SPARC_F5_REGNUM, buf + 20);
1460 regcache_cooked_write (regcache, SPARC_F6_REGNUM, buf + 24);
1461 regcache_cooked_write (regcache, SPARC_F7_REGNUM, buf + 28);
1462 }
1463 }
1464 else
1465 {
1466 /* Integral and pointer return values. */
1467 gdb_assert (sparc_integral_or_pointer_p (type));
1468
1469 if (len > 4)
1470 {
1471 gdb_assert (len == 8);
1472 memcpy (buf, valbuf, 8);
1473 regcache_cooked_write (regcache, SPARC_O1_REGNUM, buf + 4);
1474 }
1475 else
1476 {
1477 /* ??? Do we need to do any sign-extension here? */
1478 memcpy (buf + 4 - len, valbuf, len);
1479 }
1480 regcache_cooked_write (regcache, SPARC_O0_REGNUM, buf);
1481 }
1482 }
1483
1484 static enum return_value_convention
1485 sparc32_return_value (struct gdbarch *gdbarch, struct value *function,
1486 struct type *type, struct regcache *regcache,
1487 gdb_byte *readbuf, const gdb_byte *writebuf)
1488 {
1489 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1490
1491 /* The psABI says that "...every stack frame reserves the word at
1492 %fp+64. If a function returns a structure, union, or
1493 quad-precision value, this word should hold the address of the
1494 object into which the return value should be copied." This
1495 guarantees that we can always find the return value, not just
1496 before the function returns. */
1497
1498 if (sparc_structure_return_p (type))
1499 {
1500 ULONGEST sp;
1501 CORE_ADDR addr;
1502
1503 if (readbuf)
1504 {
1505 regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp);
1506 addr = read_memory_unsigned_integer (sp + 64, 4, byte_order);
1507 read_memory (addr, readbuf, TYPE_LENGTH (type));
1508 }
1509 if (writebuf)
1510 {
1511 regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp);
1512 addr = read_memory_unsigned_integer (sp + 64, 4, byte_order);
1513 write_memory (addr, writebuf, TYPE_LENGTH (type));
1514 }
1515
1516 return RETURN_VALUE_ABI_PRESERVES_ADDRESS;
1517 }
1518
1519 if (readbuf)
1520 sparc32_extract_return_value (type, regcache, readbuf);
1521 if (writebuf)
1522 sparc32_store_return_value (type, regcache, writebuf);
1523
1524 return RETURN_VALUE_REGISTER_CONVENTION;
1525 }
1526
1527 static int
1528 sparc32_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type)
1529 {
1530 return (sparc_structure_or_union_p (type)
1531 || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)
1532 || sparc_complex_floating_p (type));
1533 }
1534
1535 static int
1536 sparc32_dwarf2_struct_return_p (struct frame_info *this_frame)
1537 {
1538 CORE_ADDR pc = get_frame_address_in_block (this_frame);
1539 struct symbol *sym = find_pc_function (pc);
1540
1541 if (sym)
1542 return sparc32_struct_return_from_sym (sym);
1543 return 0;
1544 }
1545
1546 static void
1547 sparc32_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
1548 struct dwarf2_frame_state_reg *reg,
1549 struct frame_info *this_frame)
1550 {
1551 int off;
1552
1553 switch (regnum)
1554 {
1555 case SPARC_G0_REGNUM:
1556 /* Since %g0 is always zero, there is no point in saving it, and
1557 people will be inclined omit it from the CFI. Make sure we
1558 don't warn about that. */
1559 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
1560 break;
1561 case SPARC_SP_REGNUM:
1562 reg->how = DWARF2_FRAME_REG_CFA;
1563 break;
1564 case SPARC32_PC_REGNUM:
1565 case SPARC32_NPC_REGNUM:
1566 reg->how = DWARF2_FRAME_REG_RA_OFFSET;
1567 off = 8;
1568 if (sparc32_dwarf2_struct_return_p (this_frame))
1569 off += 4;
1570 if (regnum == SPARC32_NPC_REGNUM)
1571 off += 4;
1572 reg->loc.offset = off;
1573 break;
1574 }
1575 }
1576
1577 /* Implement the execute_dwarf_cfa_vendor_op method. */
1578
1579 static bool
1580 sparc_execute_dwarf_cfa_vendor_op (struct gdbarch *gdbarch, gdb_byte op,
1581 struct dwarf2_frame_state *fs)
1582 {
1583 /* Only DW_CFA_GNU_window_save is expected on SPARC. */
1584 if (op != DW_CFA_GNU_window_save)
1585 return false;
1586
1587 uint64_t reg;
1588 int size = register_size (gdbarch, 0);
1589
1590 fs->regs.alloc_regs (32);
1591 for (reg = 8; reg < 16; reg++)
1592 {
1593 fs->regs.reg[reg].how = DWARF2_FRAME_REG_SAVED_REG;
1594 fs->regs.reg[reg].loc.reg = reg + 16;
1595 }
1596 for (reg = 16; reg < 32; reg++)
1597 {
1598 fs->regs.reg[reg].how = DWARF2_FRAME_REG_SAVED_OFFSET;
1599 fs->regs.reg[reg].loc.offset = (reg - 16) * size;
1600 }
1601
1602 return true;
1603 }
1604
1605
1606 /* The SPARC Architecture doesn't have hardware single-step support,
1607 and most operating systems don't implement it either, so we provide
1608 software single-step mechanism. */
1609
1610 static CORE_ADDR
1611 sparc_analyze_control_transfer (struct regcache *regcache,
1612 CORE_ADDR pc, CORE_ADDR *npc)
1613 {
1614 unsigned long insn = sparc_fetch_instruction (pc);
1615 int conditional_p = X_COND (insn) & 0x7;
1616 int branch_p = 0, fused_p = 0;
1617 long offset = 0; /* Must be signed for sign-extend. */
1618
1619 if (X_OP (insn) == 0 && X_OP2 (insn) == 3)
1620 {
1621 if ((insn & 0x10000000) == 0)
1622 {
1623 /* Branch on Integer Register with Prediction (BPr). */
1624 branch_p = 1;
1625 conditional_p = 1;
1626 }
1627 else
1628 {
1629 /* Compare and Branch */
1630 branch_p = 1;
1631 fused_p = 1;
1632 offset = 4 * X_DISP10 (insn);
1633 }
1634 }
1635 else if (X_OP (insn) == 0 && X_OP2 (insn) == 6)
1636 {
1637 /* Branch on Floating-Point Condition Codes (FBfcc). */
1638 branch_p = 1;
1639 offset = 4 * X_DISP22 (insn);
1640 }
1641 else if (X_OP (insn) == 0 && X_OP2 (insn) == 5)
1642 {
1643 /* Branch on Floating-Point Condition Codes with Prediction
1644 (FBPfcc). */
1645 branch_p = 1;
1646 offset = 4 * X_DISP19 (insn);
1647 }
1648 else if (X_OP (insn) == 0 && X_OP2 (insn) == 2)
1649 {
1650 /* Branch on Integer Condition Codes (Bicc). */
1651 branch_p = 1;
1652 offset = 4 * X_DISP22 (insn);
1653 }
1654 else if (X_OP (insn) == 0 && X_OP2 (insn) == 1)
1655 {
1656 /* Branch on Integer Condition Codes with Prediction (BPcc). */
1657 branch_p = 1;
1658 offset = 4 * X_DISP19 (insn);
1659 }
1660 else if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3a)
1661 {
1662 struct frame_info *frame = get_current_frame ();
1663
1664 /* Trap instruction (TRAP). */
1665 return gdbarch_tdep (regcache->arch ())->step_trap (frame,
1666 insn);
1667 }
1668
1669 /* FIXME: Handle DONE and RETRY instructions. */
1670
1671 if (branch_p)
1672 {
1673 if (fused_p)
1674 {
1675 /* Fused compare-and-branch instructions are non-delayed,
1676 and do not have an annuling capability. So we need to
1677 always set a breakpoint on both the NPC and the branch
1678 target address. */
1679 gdb_assert (offset != 0);
1680 return pc + offset;
1681 }
1682 else if (conditional_p)
1683 {
1684 /* For conditional branches, return nPC + 4 iff the annul
1685 bit is 1. */
1686 return (X_A (insn) ? *npc + 4 : 0);
1687 }
1688 else
1689 {
1690 /* For unconditional branches, return the target if its
1691 specified condition is "always" and return nPC + 4 if the
1692 condition is "never". If the annul bit is 1, set *NPC to
1693 zero. */
1694 if (X_COND (insn) == 0x0)
1695 pc = *npc, offset = 4;
1696 if (X_A (insn))
1697 *npc = 0;
1698
1699 return pc + offset;
1700 }
1701 }
1702
1703 return 0;
1704 }
1705
1706 static CORE_ADDR
1707 sparc_step_trap (struct frame_info *frame, unsigned long insn)
1708 {
1709 return 0;
1710 }
1711
1712 static std::vector<CORE_ADDR>
1713 sparc_software_single_step (struct regcache *regcache)
1714 {
1715 struct gdbarch *arch = regcache->arch ();
1716 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
1717 CORE_ADDR npc, nnpc;
1718
1719 CORE_ADDR pc, orig_npc;
1720 std::vector<CORE_ADDR> next_pcs;
1721
1722 pc = regcache_raw_get_unsigned (regcache, tdep->pc_regnum);
1723 orig_npc = npc = regcache_raw_get_unsigned (regcache, tdep->npc_regnum);
1724
1725 /* Analyze the instruction at PC. */
1726 nnpc = sparc_analyze_control_transfer (regcache, pc, &npc);
1727 if (npc != 0)
1728 next_pcs.push_back (npc);
1729
1730 if (nnpc != 0)
1731 next_pcs.push_back (nnpc);
1732
1733 /* Assert that we have set at least one breakpoint, and that
1734 they're not set at the same spot - unless we're going
1735 from here straight to NULL, i.e. a call or jump to 0. */
1736 gdb_assert (npc != 0 || nnpc != 0 || orig_npc == 0);
1737 gdb_assert (nnpc != npc || orig_npc == 0);
1738
1739 return next_pcs;
1740 }
1741
1742 static void
1743 sparc_write_pc (struct regcache *regcache, CORE_ADDR pc)
1744 {
1745 struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ());
1746
1747 regcache_cooked_write_unsigned (regcache, tdep->pc_regnum, pc);
1748 regcache_cooked_write_unsigned (regcache, tdep->npc_regnum, pc + 4);
1749 }
1750
1751
1752 /* Iterate over core file register note sections. */
1753
1754 static void
1755 sparc_iterate_over_regset_sections (struct gdbarch *gdbarch,
1756 iterate_over_regset_sections_cb *cb,
1757 void *cb_data,
1758 const struct regcache *regcache)
1759 {
1760 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1761
1762 cb (".reg", tdep->sizeof_gregset, tdep->gregset, NULL, cb_data);
1763 cb (".reg2", tdep->sizeof_fpregset, tdep->fpregset, NULL, cb_data);
1764 }
1765
1766
1767 static int
1768 validate_tdesc_registers (const struct target_desc *tdesc,
1769 struct tdesc_arch_data *tdesc_data,
1770 const char *feature_name,
1771 const char *register_names[],
1772 unsigned int registers_num,
1773 unsigned int reg_start)
1774 {
1775 int valid_p = 1;
1776 const struct tdesc_feature *feature;
1777
1778 feature = tdesc_find_feature (tdesc, feature_name);
1779 if (feature == NULL)
1780 return 0;
1781
1782 for (unsigned int i = 0; i < registers_num; i++)
1783 valid_p &= tdesc_numbered_register (feature, tdesc_data,
1784 reg_start + i,
1785 register_names[i]);
1786
1787 return valid_p;
1788 }
1789
1790 static struct gdbarch *
1791 sparc32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1792 {
1793 struct gdbarch_tdep *tdep;
1794 const struct target_desc *tdesc = info.target_desc;
1795 struct gdbarch *gdbarch;
1796 int valid_p = 1;
1797
1798 /* If there is already a candidate, use it. */
1799 arches = gdbarch_list_lookup_by_info (arches, &info);
1800 if (arches != NULL)
1801 return arches->gdbarch;
1802
1803 /* Allocate space for the new architecture. */
1804 tdep = XCNEW (struct gdbarch_tdep);
1805 gdbarch = gdbarch_alloc (&info, tdep);
1806
1807 tdep->pc_regnum = SPARC32_PC_REGNUM;
1808 tdep->npc_regnum = SPARC32_NPC_REGNUM;
1809 tdep->step_trap = sparc_step_trap;
1810 tdep->fpu_register_names = sparc32_fpu_register_names;
1811 tdep->fpu_registers_num = ARRAY_SIZE (sparc32_fpu_register_names);
1812 tdep->cp0_register_names = sparc32_cp0_register_names;
1813 tdep->cp0_registers_num = ARRAY_SIZE (sparc32_cp0_register_names);
1814
1815 set_gdbarch_long_double_bit (gdbarch, 128);
1816 set_gdbarch_long_double_format (gdbarch, floatformats_sparc_quad);
1817
1818 set_gdbarch_wchar_bit (gdbarch, 16);
1819 set_gdbarch_wchar_signed (gdbarch, 1);
1820
1821 set_gdbarch_num_regs (gdbarch, SPARC32_NUM_REGS);
1822 set_gdbarch_register_name (gdbarch, sparc32_register_name);
1823 set_gdbarch_register_type (gdbarch, sparc32_register_type);
1824 set_gdbarch_num_pseudo_regs (gdbarch, SPARC32_NUM_PSEUDO_REGS);
1825 set_tdesc_pseudo_register_name (gdbarch, sparc32_pseudo_register_name);
1826 set_tdesc_pseudo_register_type (gdbarch, sparc32_pseudo_register_type);
1827 set_gdbarch_pseudo_register_read (gdbarch, sparc32_pseudo_register_read);
1828 set_gdbarch_pseudo_register_write (gdbarch, sparc32_pseudo_register_write);
1829
1830 /* Register numbers of various important registers. */
1831 set_gdbarch_sp_regnum (gdbarch, SPARC_SP_REGNUM); /* %sp */
1832 set_gdbarch_pc_regnum (gdbarch, SPARC32_PC_REGNUM); /* %pc */
1833 set_gdbarch_fp0_regnum (gdbarch, SPARC_F0_REGNUM); /* %f0 */
1834
1835 /* Call dummy code. */
1836 set_gdbarch_frame_align (gdbarch, sparc32_frame_align);
1837 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
1838 set_gdbarch_push_dummy_code (gdbarch, sparc32_push_dummy_code);
1839 set_gdbarch_push_dummy_call (gdbarch, sparc32_push_dummy_call);
1840
1841 set_gdbarch_return_value (gdbarch, sparc32_return_value);
1842 set_gdbarch_stabs_argument_has_addr
1843 (gdbarch, sparc32_stabs_argument_has_addr);
1844
1845 set_gdbarch_skip_prologue (gdbarch, sparc32_skip_prologue);
1846
1847 /* Stack grows downward. */
1848 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1849
1850 set_gdbarch_breakpoint_kind_from_pc (gdbarch,
1851 sparc_breakpoint::kind_from_pc);
1852 set_gdbarch_sw_breakpoint_from_kind (gdbarch,
1853 sparc_breakpoint::bp_from_kind);
1854
1855 set_gdbarch_frame_args_skip (gdbarch, 8);
1856
1857 set_gdbarch_software_single_step (gdbarch, sparc_software_single_step);
1858 set_gdbarch_write_pc (gdbarch, sparc_write_pc);
1859
1860 set_gdbarch_dummy_id (gdbarch, sparc_dummy_id);
1861
1862 set_gdbarch_unwind_pc (gdbarch, sparc_unwind_pc);
1863
1864 frame_base_set_default (gdbarch, &sparc32_frame_base);
1865
1866 /* Hook in the DWARF CFI frame unwinder. */
1867 dwarf2_frame_set_init_reg (gdbarch, sparc32_dwarf2_frame_init_reg);
1868 /* Register DWARF vendor CFI handler. */
1869 set_gdbarch_execute_dwarf_cfa_vendor_op (gdbarch,
1870 sparc_execute_dwarf_cfa_vendor_op);
1871 /* FIXME: kettenis/20050423: Don't enable the unwinder until the
1872 StackGhost issues have been resolved. */
1873
1874 /* Hook in ABI-specific overrides, if they have been registered. */
1875 gdbarch_init_osabi (info, gdbarch);
1876
1877 frame_unwind_append_unwinder (gdbarch, &sparc32_frame_unwind);
1878
1879 if (tdesc_has_registers (tdesc))
1880 {
1881 struct tdesc_arch_data *tdesc_data = tdesc_data_alloc ();
1882
1883 /* Validate that the descriptor provides the mandatory registers
1884 and allocate their numbers. */
1885 valid_p &= validate_tdesc_registers (tdesc, tdesc_data,
1886 "org.gnu.gdb.sparc.cpu",
1887 sparc_core_register_names,
1888 ARRAY_SIZE (sparc_core_register_names),
1889 SPARC_G0_REGNUM);
1890 valid_p &= validate_tdesc_registers (tdesc, tdesc_data,
1891 "org.gnu.gdb.sparc.fpu",
1892 tdep->fpu_register_names,
1893 tdep->fpu_registers_num,
1894 SPARC_F0_REGNUM);
1895 valid_p &= validate_tdesc_registers (tdesc, tdesc_data,
1896 "org.gnu.gdb.sparc.cp0",
1897 tdep->cp0_register_names,
1898 tdep->cp0_registers_num,
1899 SPARC_F0_REGNUM
1900 + tdep->fpu_registers_num);
1901 if (!valid_p)
1902 {
1903 tdesc_data_cleanup (tdesc_data);
1904 return NULL;
1905 }
1906
1907 /* Target description may have changed. */
1908 info.tdesc_data = tdesc_data;
1909 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
1910 }
1911
1912 /* If we have register sets, enable the generic core file support. */
1913 if (tdep->gregset)
1914 set_gdbarch_iterate_over_regset_sections
1915 (gdbarch, sparc_iterate_over_regset_sections);
1916
1917 register_sparc_ravenscar_ops (gdbarch);
1918
1919 return gdbarch;
1920 }
1921
1922 /* Helper functions for dealing with register windows. */
1923
1924 void
1925 sparc_supply_rwindow (struct regcache *regcache, CORE_ADDR sp, int regnum)
1926 {
1927 struct gdbarch *gdbarch = regcache->arch ();
1928 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1929 int offset = 0;
1930 gdb_byte buf[8];
1931 int i;
1932
1933 if (sp & 1)
1934 {
1935 /* Registers are 64-bit. */
1936 sp += BIAS;
1937
1938 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1939 {
1940 if (regnum == i || regnum == -1)
1941 {
1942 target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8);
1943
1944 /* Handle StackGhost. */
1945 if (i == SPARC_I7_REGNUM)
1946 {
1947 ULONGEST wcookie = sparc_fetch_wcookie (gdbarch);
1948 ULONGEST i7;
1949
1950 i7 = extract_unsigned_integer (buf + offset, 8, byte_order);
1951 store_unsigned_integer (buf + offset, 8, byte_order,
1952 i7 ^ wcookie);
1953 }
1954
1955 regcache_raw_supply (regcache, i, buf);
1956 }
1957 }
1958 }
1959 else
1960 {
1961 /* Registers are 32-bit. Toss any sign-extension of the stack
1962 pointer. */
1963 sp &= 0xffffffffUL;
1964
1965 /* Clear out the top half of the temporary buffer, and put the
1966 register value in the bottom half if we're in 64-bit mode. */
1967 if (gdbarch_ptr_bit (regcache->arch ()) == 64)
1968 {
1969 memset (buf, 0, 4);
1970 offset = 4;
1971 }
1972
1973 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1974 {
1975 if (regnum == i || regnum == -1)
1976 {
1977 target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 4),
1978 buf + offset, 4);
1979
1980 /* Handle StackGhost. */
1981 if (i == SPARC_I7_REGNUM)
1982 {
1983 ULONGEST wcookie = sparc_fetch_wcookie (gdbarch);
1984 ULONGEST i7;
1985
1986 i7 = extract_unsigned_integer (buf + offset, 4, byte_order);
1987 store_unsigned_integer (buf + offset, 4, byte_order,
1988 i7 ^ wcookie);
1989 }
1990
1991 regcache_raw_supply (regcache, i, buf);
1992 }
1993 }
1994 }
1995 }
1996
1997 void
1998 sparc_collect_rwindow (const struct regcache *regcache,
1999 CORE_ADDR sp, int regnum)
2000 {
2001 struct gdbarch *gdbarch = regcache->arch ();
2002 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2003 int offset = 0;
2004 gdb_byte buf[8];
2005 int i;
2006
2007 if (sp & 1)
2008 {
2009 /* Registers are 64-bit. */
2010 sp += BIAS;
2011
2012 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
2013 {
2014 if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i)
2015 {
2016 regcache_raw_collect (regcache, i, buf);
2017
2018 /* Handle StackGhost. */
2019 if (i == SPARC_I7_REGNUM)
2020 {
2021 ULONGEST wcookie = sparc_fetch_wcookie (gdbarch);
2022 ULONGEST i7;
2023
2024 i7 = extract_unsigned_integer (buf + offset, 8, byte_order);
2025 store_unsigned_integer (buf, 8, byte_order, i7 ^ wcookie);
2026 }
2027
2028 target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8);
2029 }
2030 }
2031 }
2032 else
2033 {
2034 /* Registers are 32-bit. Toss any sign-extension of the stack
2035 pointer. */
2036 sp &= 0xffffffffUL;
2037
2038 /* Only use the bottom half if we're in 64-bit mode. */
2039 if (gdbarch_ptr_bit (regcache->arch ()) == 64)
2040 offset = 4;
2041
2042 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
2043 {
2044 if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i)
2045 {
2046 regcache_raw_collect (regcache, i, buf);
2047
2048 /* Handle StackGhost. */
2049 if (i == SPARC_I7_REGNUM)
2050 {
2051 ULONGEST wcookie = sparc_fetch_wcookie (gdbarch);
2052 ULONGEST i7;
2053
2054 i7 = extract_unsigned_integer (buf + offset, 4, byte_order);
2055 store_unsigned_integer (buf + offset, 4, byte_order,
2056 i7 ^ wcookie);
2057 }
2058
2059 target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 4),
2060 buf + offset, 4);
2061 }
2062 }
2063 }
2064 }
2065
2066 /* Helper functions for dealing with register sets. */
2067
2068 void
2069 sparc32_supply_gregset (const struct sparc_gregmap *gregmap,
2070 struct regcache *regcache,
2071 int regnum, const void *gregs)
2072 {
2073 const gdb_byte *regs = (const gdb_byte *) gregs;
2074 gdb_byte zero[4] = { 0 };
2075 int i;
2076
2077 if (regnum == SPARC32_PSR_REGNUM || regnum == -1)
2078 regcache_raw_supply (regcache, SPARC32_PSR_REGNUM,
2079 regs + gregmap->r_psr_offset);
2080
2081 if (regnum == SPARC32_PC_REGNUM || regnum == -1)
2082 regcache_raw_supply (regcache, SPARC32_PC_REGNUM,
2083 regs + gregmap->r_pc_offset);
2084
2085 if (regnum == SPARC32_NPC_REGNUM || regnum == -1)
2086 regcache_raw_supply (regcache, SPARC32_NPC_REGNUM,
2087 regs + gregmap->r_npc_offset);
2088
2089 if (regnum == SPARC32_Y_REGNUM || regnum == -1)
2090 regcache_raw_supply (regcache, SPARC32_Y_REGNUM,
2091 regs + gregmap->r_y_offset);
2092
2093 if (regnum == SPARC_G0_REGNUM || regnum == -1)
2094 regcache_raw_supply (regcache, SPARC_G0_REGNUM, &zero);
2095
2096 if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1)
2097 {
2098 int offset = gregmap->r_g1_offset;
2099
2100 for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++)
2101 {
2102 if (regnum == i || regnum == -1)
2103 regcache_raw_supply (regcache, i, regs + offset);
2104 offset += 4;
2105 }
2106 }
2107
2108 if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1)
2109 {
2110 /* Not all of the register set variants include Locals and
2111 Inputs. For those that don't, we read them off the stack. */
2112 if (gregmap->r_l0_offset == -1)
2113 {
2114 ULONGEST sp;
2115
2116 regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp);
2117 sparc_supply_rwindow (regcache, sp, regnum);
2118 }
2119 else
2120 {
2121 int offset = gregmap->r_l0_offset;
2122
2123 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
2124 {
2125 if (regnum == i || regnum == -1)
2126 regcache_raw_supply (regcache, i, regs + offset);
2127 offset += 4;
2128 }
2129 }
2130 }
2131 }
2132
2133 void
2134 sparc32_collect_gregset (const struct sparc_gregmap *gregmap,
2135 const struct regcache *regcache,
2136 int regnum, void *gregs)
2137 {
2138 gdb_byte *regs = (gdb_byte *) gregs;
2139 int i;
2140
2141 if (regnum == SPARC32_PSR_REGNUM || regnum == -1)
2142 regcache_raw_collect (regcache, SPARC32_PSR_REGNUM,
2143 regs + gregmap->r_psr_offset);
2144
2145 if (regnum == SPARC32_PC_REGNUM || regnum == -1)
2146 regcache_raw_collect (regcache, SPARC32_PC_REGNUM,
2147 regs + gregmap->r_pc_offset);
2148
2149 if (regnum == SPARC32_NPC_REGNUM || regnum == -1)
2150 regcache_raw_collect (regcache, SPARC32_NPC_REGNUM,
2151 regs + gregmap->r_npc_offset);
2152
2153 if (regnum == SPARC32_Y_REGNUM || regnum == -1)
2154 regcache_raw_collect (regcache, SPARC32_Y_REGNUM,
2155 regs + gregmap->r_y_offset);
2156
2157 if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1)
2158 {
2159 int offset = gregmap->r_g1_offset;
2160
2161 /* %g0 is always zero. */
2162 for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++)
2163 {
2164 if (regnum == i || regnum == -1)
2165 regcache_raw_collect (regcache, i, regs + offset);
2166 offset += 4;
2167 }
2168 }
2169
2170 if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1)
2171 {
2172 /* Not all of the register set variants include Locals and
2173 Inputs. For those that don't, we read them off the stack. */
2174 if (gregmap->r_l0_offset != -1)
2175 {
2176 int offset = gregmap->r_l0_offset;
2177
2178 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
2179 {
2180 if (regnum == i || regnum == -1)
2181 regcache_raw_collect (regcache, i, regs + offset);
2182 offset += 4;
2183 }
2184 }
2185 }
2186 }
2187
2188 void
2189 sparc32_supply_fpregset (const struct sparc_fpregmap *fpregmap,
2190 struct regcache *regcache,
2191 int regnum, const void *fpregs)
2192 {
2193 const gdb_byte *regs = (const gdb_byte *) fpregs;
2194 int i;
2195
2196 for (i = 0; i < 32; i++)
2197 {
2198 if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1)
2199 regcache_raw_supply (regcache, SPARC_F0_REGNUM + i,
2200 regs + fpregmap->r_f0_offset + (i * 4));
2201 }
2202
2203 if (regnum == SPARC32_FSR_REGNUM || regnum == -1)
2204 regcache_raw_supply (regcache, SPARC32_FSR_REGNUM,
2205 regs + fpregmap->r_fsr_offset);
2206 }
2207
2208 void
2209 sparc32_collect_fpregset (const struct sparc_fpregmap *fpregmap,
2210 const struct regcache *regcache,
2211 int regnum, void *fpregs)
2212 {
2213 gdb_byte *regs = (gdb_byte *) fpregs;
2214 int i;
2215
2216 for (i = 0; i < 32; i++)
2217 {
2218 if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1)
2219 regcache_raw_collect (regcache, SPARC_F0_REGNUM + i,
2220 regs + fpregmap->r_f0_offset + (i * 4));
2221 }
2222
2223 if (regnum == SPARC32_FSR_REGNUM || regnum == -1)
2224 regcache_raw_collect (regcache, SPARC32_FSR_REGNUM,
2225 regs + fpregmap->r_fsr_offset);
2226 }
2227
2228
2229 /* SunOS 4. */
2230
2231 /* From <machine/reg.h>. */
2232 const struct sparc_gregmap sparc32_sunos4_gregmap =
2233 {
2234 0 * 4, /* %psr */
2235 1 * 4, /* %pc */
2236 2 * 4, /* %npc */
2237 3 * 4, /* %y */
2238 -1, /* %wim */
2239 -1, /* %tbr */
2240 4 * 4, /* %g1 */
2241 -1 /* %l0 */
2242 };
2243
2244 const struct sparc_fpregmap sparc32_sunos4_fpregmap =
2245 {
2246 0 * 4, /* %f0 */
2247 33 * 4, /* %fsr */
2248 };
2249
2250 const struct sparc_fpregmap sparc32_bsd_fpregmap =
2251 {
2252 0 * 4, /* %f0 */
2253 32 * 4, /* %fsr */
2254 };
2255
2256 void
2257 _initialize_sparc_tdep (void)
2258 {
2259 register_gdbarch_init (bfd_arch_sparc, sparc32_gdbarch_init);
2260 }
set_gdbarch_num_regs
void set_gdbarch_num_regs(struct gdbarch *gdbarch, int num_regs)
Definition: gdbarch.c:2050
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Definition: gdbarch.c:127
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Definition: gdbarch.c:3151
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Definition: sparc-tdep.c:390
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Definition: gdbtypes.h:164
X_A
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Definition: sparc-tdep.c:77
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Definition: sparc-tdep.h:23
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Definition: gdbtypes.h:80
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Definition: gdbtypes.h:104
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Definition: common-regcache.c:26
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Definition: frame.c:624
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Definition: sparc-tdep.c:537
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Definition: frame.c:2407
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Definition: sparc-tdep.c:1436
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Definition: sparc-tdep.h:45
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Definition: sparc-tdep.c:338
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Definition: common-regcache.h:32
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Definition: gdbtypes.h:1565
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Definition: target-descriptions.c:1341
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Definition: osabi.c:334
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Definition: sparc-tdep.h:171
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Definition: frame-unwind.c:79
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Definition: sparc-tdep.c:559
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Definition: regcache.c:777
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const struct sparc_fpregmap sparc32_sunos4_fpregmap
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Definition: gdbarch.c:1509
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Definition: sparc-tdep.h:50
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const char ** cp0_register_names
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Definition: dwarf2-frame.h:188
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Definition: frame-unwind.c:174
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Definition: sparc-tdep.h:102
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Definition: sparc-tdep.c:363
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Definition: sparc-tdep.h:149
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struct gdbarch * gdbarch
Definition: gdbarch.h:1622
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Definition: target-descriptions.c:516
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Definition: aarch64-tdep.c:77
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Definition: frame-base.h:58
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Definition: corefile.c:258
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Definition: defs.h:270
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Definition: frame.c:1308
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Definition: gdbtypes.h:106
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const struct sparc_gregmap sparc32_sunos4_gregmap
Definition: sparc-tdep.c:2232
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Definition: gdbarch.c:3055
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Definition: dwarf2-frame.h:53
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Definition: sparc-tdep.h:138
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TYPE_CODE_FUNC
Definition: gdbtypes.h:110
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static int sparc32_dwarf2_struct_return_p(struct frame_info *this_frame)
Definition: sparc-tdep.c:1536
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Definition: regdef.h:22
_initialize_sparc_tdep
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Definition: sparc-tdep.c:2257
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Definition: gdb_assert.h:32
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const struct target_desc * target_desc
Definition: gdbarch.h:1660
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Definition: value.c:169
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Definition: frv-tdep.c:88
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Definition: sparc-tdep.c:66
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Definition: sparc-tdep.c:130
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static CORE_ADDR sparc32_push_dummy_code(struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funcaddr, struct value **args, int nargs, struct type *value_type, CORE_ADDR *real_pc, CORE_ADDR *bp_addr, struct regcache *regcache)
Definition: sparc-tdep.c:566
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Definition: gdbarch.c:3258
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CORE_ADDR sparc_analyze_prologue(struct gdbarch *gdbarch, CORE_ADDR pc, CORE_ADDR current_pc, struct sparc_frame_cache *cache)
Definition: sparc-tdep.c:965
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Definition: gdbarch.c:2422
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Definition: symtab.h:1746
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Definition: gdbtypes.h:84
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const struct sparc_fpregmap sparc32_bsd_fpregmap
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Definition: sparc-tdep.c:76
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Definition: sparc-tdep.h:41
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Definition: gdbtypes.h:1511
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Definition: sparc-tdep.h:110
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Definition: sparc-tdep.h:109
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static struct type * sparc32_register_type(struct gdbarch *gdbarch, int regnum)
Definition: sparc-tdep.c:478
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Definition: poison.h:121
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Definition: regcache.c:565
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Definition: regcache.c:806
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Definition: sparc-tdep.h:137
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Definition: target.c:1370
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Definition: target-descriptions.c:591
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Definition: sparc-tdep.c:87
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Definition: gdbtypes.h:1554
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static int in_plt_section(CORE_ADDR pc)
Definition: objfiles.h:542
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Definition: agent.c:65
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Definition: ser-unix.c:239
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Definition: sparc-tdep.c:343
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Definition: sparc-tdep.h:140
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Definition: gdbarch.c:2067
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static enum return_value_convention sparc32_return_value(struct gdbarch *gdbarch, struct value *function, struct type *type, struct regcache *regcache, gdb_byte *readbuf, const gdb_byte *writebuf)
Definition: sparc-tdep.c:1485
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Definition: sparc-tdep.c:92
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gdbarch * arch() const
Definition: regcache.c:221
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enum register_status regcache_cooked_read(struct regcache *regcache, int regnum, gdb_byte *buf)
Definition: regcache.c:661
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size_t fpu_registers_num
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Definition: sparc-tdep.h:39
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Definition: i386-tdep.h:204
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static struct type * sparc_psr_type(struct gdbarch *gdbarch)
Definition: sparc-tdep.c:404
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Definition: sparc-tdep.h:52
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Definition: sparc-tdep.c:82
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const struct regset * fpregset
Definition: i386-tdep.h:253
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struct tdesc_arch_data * tdesc_data_alloc(void)
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Definition: gdbarch.c:2398
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ULONGEST
unsigned long long ULONGEST
Definition: common-types.h:53
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Definition: sparc-tdep.h:134
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enum unwind_stop_reason default_frame_unwind_stop_reason(struct frame_info *this_frame, void **this_cache)
Definition: frame-unwind.c:184
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const struct tdesc_feature * tdesc_find_feature(const struct target_desc *target_desc, const char *name)
Definition: target-descriptions.c:942
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Definition: target-descriptions.c:670
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Definition: regcache.c:164
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Definition: regcache.h:232
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Definition: gdbarch.h:1626
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Definition: gdbarch.c:1756
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Definition: sparc-tdep.h:186
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Definition: value.c:1095
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Definition: frame.c:128
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Definition: sparc-tdep.h:131
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#define SYMBOL_TYPE(symbol)
Definition: symtab.h:1161
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Definition: symtab.h:1049
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Definition: gdbarch.c:2738
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LONGEST target_read(struct target_ops *ops, enum target_object object, const char *annex, gdb_byte *buf, ULONGEST offset, LONGEST len)
Definition: target.c:1562
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Definition: regcache.c:1085
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void dwarf2_frame_set_init_reg(struct gdbarch *gdbarch, void(*init_reg)(struct gdbarch *, int, struct dwarf2_frame_state_reg *, struct frame_info *))
Definition: dwarf2-frame.c:743
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Definition: gdbarch.c:1772
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Definition: gdbtypes.h:1235
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void set_gdbarch_push_dummy_call(struct gdbarch *gdbarch, gdbarch_push_dummy_call_ftype push_dummy_call)
Definition: gdbarch.c:2381
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Definition: sparc-tdep.c:78
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ULONGEST read_memory_unsigned_integer(CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
Definition: corefile.c:326
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void set_gdbarch_sw_breakpoint_from_kind(struct gdbarch *gdbarch, gdbarch_sw_breakpoint_from_kind_ftype sw_breakpoint_from_kind)
Definition: gdbarch.c:2888
set_gdbarch_iterate_over_regset_sections
void set_gdbarch_iterate_over_regset_sections(struct gdbarch *gdbarch, gdbarch_iterate_over_regset_sections_ftype iterate_over_regset_sections)
Definition: gdbarch.c:3647
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void register_gdbarch_init(enum bfd_architecture bfd_architecture, gdbarch_init_ftype *init)
Definition: gdbarch.c:5299
sparc-ravenscar-thread.h
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int frameless_p
Definition: sparc-tdep.h:174
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Definition: corefile.c:394
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Definition: gdbarch.c:2772
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static void sparc_iterate_over_regset_sections(struct gdbarch *gdbarch, iterate_over_regset_sections_cb *cb, void *cb_data, const struct regcache *regcache)
Definition: sparc-tdep.c:1755
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static CORE_ADDR sparc32_push_dummy_call(struct gdbarch *gdbarch, struct value *function, struct regcache *regcache, CORE_ADDR bp_addr, int nargs, struct value **args, CORE_ADDR sp, int struct_return, CORE_ADDR struct_addr)
Definition: sparc-tdep.c:694
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static struct gdbarch_data * tdesc_data
Definition: target-descriptions.c:725
TYPE_CODE_METHOD
Definition: gdbtypes.h:141
gdbarch_tdep::plt_entry_size
size_t plt_entry_size
Definition: sparc-tdep.h:83
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static enum register_status sparc32_pseudo_register_read(struct gdbarch *gdbarch, struct regcache *regcache, int regnum, gdb_byte *buf)
Definition: sparc-tdep.c:505
DWARF2_FRAME_REG_RA_OFFSET
Definition: dwarf2-frame.h:63
sparc_floating_p
static int sparc_floating_p(const struct type *type)
Definition: sparc-tdep.c:243
sparc32_gdbarch_init
static struct gdbarch * sparc32_gdbarch_init(struct gdbarch_info info, struct gdbarch_list *arches)
Definition: sparc-tdep.c:1791
SPARC_F6_REGNUM
Definition: sparc-tdep.h:139
sparc_frame_cache
Definition: sparc-tdep.h:167
RETURN_VALUE_REGISTER_CONVENTION
Definition: defs.h:251
gdbarch_info::tdesc_data
struct tdesc_arch_data * tdesc_data
Definition: gdbarch.h:1648
gdbarch::byte_order
enum bfd_endian byte_order
Definition: gdbarch.c:137
set_gdbarch_pc_regnum
void set_gdbarch_pc_regnum(struct gdbarch *gdbarch, int pc_regnum)
Definition: gdbarch.c:2173
sparc_software_single_step
static std::vector< CORE_ADDR > sparc_software_single_step(struct regcache *regcache)
Definition: sparc-tdep.c:1713
tdesc_has_registers
int tdesc_has_registers(const struct target_desc *target_desc)
Definition: target-descriptions.c:926
set_gdbarch_register_name
void set_gdbarch_register_name(struct gdbarch *gdbarch, gdbarch_register_name_ftype register_name)
Definition: gdbarch.c:2292
get_frame_func
CORE_ADDR get_frame_func(struct frame_info *this_frame)
Definition: frame.c:1001
size
size_t size
Definition: go32-nat.c:242
SPARC32_Y_REGNUM
Definition: sparc-tdep.h:147
gdbarch_alloc
struct gdbarch * gdbarch_alloc(const struct gdbarch_info *info, struct gdbarch_tdep *tdep)
Definition: gdbarch.c:361
set_gdbarch_inner_than
void set_gdbarch_inner_than(struct gdbarch *gdbarch, gdbarch_inner_than_ftype inner_than)
Definition: gdbarch.c:2837
lookup_pointer_type
struct type * lookup_pointer_type(struct type *type)
Definition: gdbtypes.c:381
frame_id
Definition: frame.h:111
get_frame_arch
struct gdbarch * get_frame_arch(struct frame_info *this_frame)
Definition: frame.c:2691
sparc32_skip_prologue
static CORE_ADDR sparc32_skip_prologue(struct gdbarch *gdbarch, CORE_ADDR start_pc)
Definition: sparc-tdep.c:1107
X_OP
#define X_OP(i)
Definition: sparc-tdep.c:75
regcache_cooked_write
void regcache_cooked_write(struct regcache *regcache, int regnum, const gdb_byte *buf)
Definition: regcache.c:873
sparc_break_insn
constexpr gdb_byte sparc_break_insn[]
Definition: sparc-tdep.c:726
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static const char * sparc32_register_names[]
Definition: sparc-tdep.c:350
builtin_type::builtin_float
struct type * builtin_float
Definition: gdbtypes.h:1510
TYPE_CODE_COMPLEX
Definition: gdbtypes.h:167
store_unsigned_integer
static void store_unsigned_integer(gdb_byte *addr, int len, enum bfd_endian byte_order, ULONGEST val)
Definition: defs.h:604
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const struct target_desc * gdbarch_target_desc(struct gdbarch *gdbarch)
Definition: gdbarch.c:1536
sparc32_dwarf2_frame_init_reg
static void sparc32_dwarf2_frame_init_reg(struct gdbarch *gdbarch, int regnum, struct dwarf2_frame_state_reg *reg, struct frame_info *this_frame)
Definition: sparc-tdep.c:1547
regcache_raw_write
void regcache_raw_write(struct regcache *regcache, int regnum, const gdb_byte *buf)
Definition: regcache.c:831
gdbarch_list
Definition: gdbarch.h:1620