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/tmp/gdb-8.1/gdb/amd64-tdep.c
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1 /* Target-dependent code for AMD64.
2
3 Copyright (C) 2001-2018 Free Software Foundation, Inc.
4
5 Contributed by Jiri Smid, SuSE Labs.
6
7 This file is part of GDB.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21
22 #include "defs.h"
23 #include "opcode/i386.h"
24 #include "dis-asm.h"
25 #include "arch-utils.h"
26 #include "block.h"
27 #include "dummy-frame.h"
28 #include "frame.h"
29 #include "frame-base.h"
30 #include "frame-unwind.h"
31 #include "inferior.h"
32 #include "infrun.h"
33 #include "gdbcmd.h"
34 #include "gdbcore.h"
35 #include "objfiles.h"
36 #include "regcache.h"
37 #include "regset.h"
38 #include "symfile.h"
39 #include "disasm.h"
40 #include "amd64-tdep.h"
41 #include "i387-tdep.h"
42 #include "x86-xstate.h"
43 #include <algorithm>
44 #include "target-descriptions.h"
45 #include "arch/amd64.h"
46 #include "producer.h"
47 #include "ax.h"
48 #include "ax-gdb.h"
49 #include "common/byte-vector.h"
50
51 /* Note that the AMD64 architecture was previously known as x86-64.
52 The latter is (forever) engraved into the canonical system name as
53 returned by config.guess, and used as the name for the AMD64 port
54 of GNU/Linux. The BSD's have renamed their ports to amd64; they
55 don't like to shout. For GDB we prefer the amd64_-prefix over the
56 x86_64_-prefix since it's so much easier to type. */
57
58 /* Register information. */
59
60 static const char *amd64_register_names[] =
61 {
62 "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp", "rsp",
63
64 /* %r8 is indeed register number 8. */
65 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
66 "rip", "eflags", "cs", "ss", "ds", "es", "fs", "gs",
67
68 /* %st0 is register number 24. */
69 "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7",
70 "fctrl", "fstat", "ftag", "fiseg", "fioff", "foseg", "fooff", "fop",
71
72 /* %xmm0 is register number 40. */
73 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
74 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
75 "mxcsr",
76 };
77
78 static const char *amd64_ymm_names[] =
79 {
80 "ymm0", "ymm1", "ymm2", "ymm3",
81 "ymm4", "ymm5", "ymm6", "ymm7",
82 "ymm8", "ymm9", "ymm10", "ymm11",
83 "ymm12", "ymm13", "ymm14", "ymm15"
84 };
85
86 static const char *amd64_ymm_avx512_names[] =
87 {
88 "ymm16", "ymm17", "ymm18", "ymm19",
89 "ymm20", "ymm21", "ymm22", "ymm23",
90 "ymm24", "ymm25", "ymm26", "ymm27",
91 "ymm28", "ymm29", "ymm30", "ymm31"
92 };
93
94 static const char *amd64_ymmh_names[] =
95 {
96 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
97 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
98 "ymm8h", "ymm9h", "ymm10h", "ymm11h",
99 "ymm12h", "ymm13h", "ymm14h", "ymm15h"
100 };
101
102 static const char *amd64_ymmh_avx512_names[] =
103 {
104 "ymm16h", "ymm17h", "ymm18h", "ymm19h",
105 "ymm20h", "ymm21h", "ymm22h", "ymm23h",
106 "ymm24h", "ymm25h", "ymm26h", "ymm27h",
107 "ymm28h", "ymm29h", "ymm30h", "ymm31h"
108 };
109
110 static const char *amd64_mpx_names[] =
111 {
112 "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus"
113 };
114
115 static const char *amd64_k_names[] =
116 {
117 "k0", "k1", "k2", "k3",
118 "k4", "k5", "k6", "k7"
119 };
120
121 static const char *amd64_zmmh_names[] =
122 {
123 "zmm0h", "zmm1h", "zmm2h", "zmm3h",
124 "zmm4h", "zmm5h", "zmm6h", "zmm7h",
125 "zmm8h", "zmm9h", "zmm10h", "zmm11h",
126 "zmm12h", "zmm13h", "zmm14h", "zmm15h",
127 "zmm16h", "zmm17h", "zmm18h", "zmm19h",
128 "zmm20h", "zmm21h", "zmm22h", "zmm23h",
129 "zmm24h", "zmm25h", "zmm26h", "zmm27h",
130 "zmm28h", "zmm29h", "zmm30h", "zmm31h"
131 };
132
133 static const char *amd64_zmm_names[] =
134 {
135 "zmm0", "zmm1", "zmm2", "zmm3",
136 "zmm4", "zmm5", "zmm6", "zmm7",
137 "zmm8", "zmm9", "zmm10", "zmm11",
138 "zmm12", "zmm13", "zmm14", "zmm15",
139 "zmm16", "zmm17", "zmm18", "zmm19",
140 "zmm20", "zmm21", "zmm22", "zmm23",
141 "zmm24", "zmm25", "zmm26", "zmm27",
142 "zmm28", "zmm29", "zmm30", "zmm31"
143 };
144
145 static const char *amd64_xmm_avx512_names[] = {
146 "xmm16", "xmm17", "xmm18", "xmm19",
147 "xmm20", "xmm21", "xmm22", "xmm23",
148 "xmm24", "xmm25", "xmm26", "xmm27",
149 "xmm28", "xmm29", "xmm30", "xmm31"
150 };
151
152 static const char *amd64_pkeys_names[] = {
153 "pkru"
154 };
155
156 /* DWARF Register Number Mapping as defined in the System V psABI,
157 section 3.6. */
158
159 static int amd64_dwarf_regmap[] =
160 {
161 /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */
162 AMD64_RAX_REGNUM, AMD64_RDX_REGNUM,
163 AMD64_RCX_REGNUM, AMD64_RBX_REGNUM,
164 AMD64_RSI_REGNUM, AMD64_RDI_REGNUM,
165
166 /* Frame Pointer Register RBP. */
167 AMD64_RBP_REGNUM,
168
169 /* Stack Pointer Register RSP. */
170 AMD64_RSP_REGNUM,
171
172 /* Extended Integer Registers 8 - 15. */
173 AMD64_R8_REGNUM, /* %r8 */
174 AMD64_R9_REGNUM, /* %r9 */
175 AMD64_R10_REGNUM, /* %r10 */
176 AMD64_R11_REGNUM, /* %r11 */
177 AMD64_R12_REGNUM, /* %r12 */
178 AMD64_R13_REGNUM, /* %r13 */
179 AMD64_R14_REGNUM, /* %r14 */
180 AMD64_R15_REGNUM, /* %r15 */
181
182 /* Return Address RA. Mapped to RIP. */
183 AMD64_RIP_REGNUM,
184
185 /* SSE Registers 0 - 7. */
186 AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM,
187 AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3,
188 AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5,
189 AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7,
190
191 /* Extended SSE Registers 8 - 15. */
192 AMD64_XMM0_REGNUM + 8, AMD64_XMM0_REGNUM + 9,
193 AMD64_XMM0_REGNUM + 10, AMD64_XMM0_REGNUM + 11,
194 AMD64_XMM0_REGNUM + 12, AMD64_XMM0_REGNUM + 13,
195 AMD64_XMM0_REGNUM + 14, AMD64_XMM0_REGNUM + 15,
196
197 /* Floating Point Registers 0-7. */
198 AMD64_ST0_REGNUM + 0, AMD64_ST0_REGNUM + 1,
199 AMD64_ST0_REGNUM + 2, AMD64_ST0_REGNUM + 3,
200 AMD64_ST0_REGNUM + 4, AMD64_ST0_REGNUM + 5,
201 AMD64_ST0_REGNUM + 6, AMD64_ST0_REGNUM + 7,
202
203 /* MMX Registers 0 - 7.
204 We have to handle those registers specifically, as their register
205 number within GDB depends on the target (or they may even not be
206 available at all). */
207 -1, -1, -1, -1, -1, -1, -1, -1,
208
209 /* Control and Status Flags Register. */
210 AMD64_EFLAGS_REGNUM,
211
212 /* Selector Registers. */
213 AMD64_ES_REGNUM,
214 AMD64_CS_REGNUM,
215 AMD64_SS_REGNUM,
216 AMD64_DS_REGNUM,
217 AMD64_FS_REGNUM,
218 AMD64_GS_REGNUM,
219 -1,
220 -1,
221
222 /* Segment Base Address Registers. */
223 -1,
224 -1,
225 -1,
226 -1,
227
228 /* Special Selector Registers. */
229 -1,
230 -1,
231
232 /* Floating Point Control Registers. */
233 AMD64_MXCSR_REGNUM,
234 AMD64_FCTRL_REGNUM,
235 AMD64_FSTAT_REGNUM
236 };
237
238 static const int amd64_dwarf_regmap_len =
239 (sizeof (amd64_dwarf_regmap) / sizeof (amd64_dwarf_regmap[0]));
240
241 /* Convert DWARF register number REG to the appropriate register
242 number used by GDB. */
243
244 static int
245 amd64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
246 {
247 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
248 int ymm0_regnum = tdep->ymm0_regnum;
249 int regnum = -1;
250
251 if (reg >= 0 && reg < amd64_dwarf_regmap_len)
252 regnum = amd64_dwarf_regmap[reg];
253
254 if (ymm0_regnum >= 0
255 && i386_xmm_regnum_p (gdbarch, regnum))
256 regnum += ymm0_regnum - I387_XMM0_REGNUM (tdep);
257
258 return regnum;
259 }
260
261 /* Map architectural register numbers to gdb register numbers. */
262
263 static const int amd64_arch_regmap[16] =
264 {
265 AMD64_RAX_REGNUM, /* %rax */
266 AMD64_RCX_REGNUM, /* %rcx */
267 AMD64_RDX_REGNUM, /* %rdx */
268 AMD64_RBX_REGNUM, /* %rbx */
269 AMD64_RSP_REGNUM, /* %rsp */
270 AMD64_RBP_REGNUM, /* %rbp */
271 AMD64_RSI_REGNUM, /* %rsi */
272 AMD64_RDI_REGNUM, /* %rdi */
273 AMD64_R8_REGNUM, /* %r8 */
274 AMD64_R9_REGNUM, /* %r9 */
275 AMD64_R10_REGNUM, /* %r10 */
276 AMD64_R11_REGNUM, /* %r11 */
277 AMD64_R12_REGNUM, /* %r12 */
278 AMD64_R13_REGNUM, /* %r13 */
279 AMD64_R14_REGNUM, /* %r14 */
280 AMD64_R15_REGNUM /* %r15 */
281 };
282
283 static const int amd64_arch_regmap_len =
284 (sizeof (amd64_arch_regmap) / sizeof (amd64_arch_regmap[0]));
285
286 /* Convert architectural register number REG to the appropriate register
287 number used by GDB. */
288
289 static int
290 amd64_arch_reg_to_regnum (int reg)
291 {
292 gdb_assert (reg >= 0 && reg < amd64_arch_regmap_len);
293
294 return amd64_arch_regmap[reg];
295 }
296
297 /* Register names for byte pseudo-registers. */
298
299 static const char *amd64_byte_names[] =
300 {
301 "al", "bl", "cl", "dl", "sil", "dil", "bpl", "spl",
302 "r8l", "r9l", "r10l", "r11l", "r12l", "r13l", "r14l", "r15l",
303 "ah", "bh", "ch", "dh"
304 };
305
306 /* Number of lower byte registers. */
307 #define AMD64_NUM_LOWER_BYTE_REGS 16
308
309 /* Register names for word pseudo-registers. */
310
311 static const char *amd64_word_names[] =
312 {
313 "ax", "bx", "cx", "dx", "si", "di", "bp", "",
314 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
315 };
316
317 /* Register names for dword pseudo-registers. */
318
319 static const char *amd64_dword_names[] =
320 {
321 "eax", "ebx", "ecx", "edx", "esi", "edi", "ebp", "esp",
322 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d",
323 "eip"
324 };
325
326 /* Return the name of register REGNUM. */
327
328 static const char *
329 amd64_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
330 {
331 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
332 if (i386_byte_regnum_p (gdbarch, regnum))
333 return amd64_byte_names[regnum - tdep->al_regnum];
334 else if (i386_zmm_regnum_p (gdbarch, regnum))
335 return amd64_zmm_names[regnum - tdep->zmm0_regnum];
336 else if (i386_ymm_regnum_p (gdbarch, regnum))
337 return amd64_ymm_names[regnum - tdep->ymm0_regnum];
338 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
339 return amd64_ymm_avx512_names[regnum - tdep->ymm16_regnum];
340 else if (i386_word_regnum_p (gdbarch, regnum))
341 return amd64_word_names[regnum - tdep->ax_regnum];
342 else if (i386_dword_regnum_p (gdbarch, regnum))
343 return amd64_dword_names[regnum - tdep->eax_regnum];
344 else
345 return i386_pseudo_register_name (gdbarch, regnum);
346 }
347
348 static struct value *
349 amd64_pseudo_register_read_value (struct gdbarch *gdbarch,
350 struct regcache *regcache,
351 int regnum)
352 {
353 gdb_byte *raw_buf = (gdb_byte *) alloca (register_size (gdbarch, regnum));
354 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
355 enum register_status status;
356 struct value *result_value;
357 gdb_byte *buf;
358
359 result_value = allocate_value (register_type (gdbarch, regnum));
360 VALUE_LVAL (result_value) = lval_register;
361 VALUE_REGNUM (result_value) = regnum;
362 buf = value_contents_raw (result_value);
363
364 if (i386_byte_regnum_p (gdbarch, regnum))
365 {
366 int gpnum = regnum - tdep->al_regnum;
367
368 /* Extract (always little endian). */
369 if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS)
370 {
371 /* Special handling for AH, BH, CH, DH. */
372 status = regcache_raw_read (regcache,
373 gpnum - AMD64_NUM_LOWER_BYTE_REGS,
374 raw_buf);
375 if (status == REG_VALID)
376 memcpy (buf, raw_buf + 1, 1);
377 else
378 mark_value_bytes_unavailable (result_value, 0,
379 TYPE_LENGTH (value_type (result_value)));
380 }
381 else
382 {
383 status = regcache_raw_read (regcache, gpnum, raw_buf);
384 if (status == REG_VALID)
385 memcpy (buf, raw_buf, 1);
386 else
387 mark_value_bytes_unavailable (result_value, 0,
388 TYPE_LENGTH (value_type (result_value)));
389 }
390 }
391 else if (i386_dword_regnum_p (gdbarch, regnum))
392 {
393 int gpnum = regnum - tdep->eax_regnum;
394 /* Extract (always little endian). */
395 status = regcache_raw_read (regcache, gpnum, raw_buf);
396 if (status == REG_VALID)
397 memcpy (buf, raw_buf, 4);
398 else
399 mark_value_bytes_unavailable (result_value, 0,
400 TYPE_LENGTH (value_type (result_value)));
401 }
402 else
403 i386_pseudo_register_read_into_value (gdbarch, regcache, regnum,
404 result_value);
405
406 return result_value;
407 }
408
409 static void
410 amd64_pseudo_register_write (struct gdbarch *gdbarch,
411 struct regcache *regcache,
412 int regnum, const gdb_byte *buf)
413 {
414 gdb_byte *raw_buf = (gdb_byte *) alloca (register_size (gdbarch, regnum));
415 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
416
417 if (i386_byte_regnum_p (gdbarch, regnum))
418 {
419 int gpnum = regnum - tdep->al_regnum;
420
421 if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS)
422 {
423 /* Read ... AH, BH, CH, DH. */
424 regcache_raw_read (regcache,
425 gpnum - AMD64_NUM_LOWER_BYTE_REGS, raw_buf);
426 /* ... Modify ... (always little endian). */
427 memcpy (raw_buf + 1, buf, 1);
428 /* ... Write. */
429 regcache_raw_write (regcache,
430 gpnum - AMD64_NUM_LOWER_BYTE_REGS, raw_buf);
431 }
432 else
433 {
434 /* Read ... */
435 regcache_raw_read (regcache, gpnum, raw_buf);
436 /* ... Modify ... (always little endian). */
437 memcpy (raw_buf, buf, 1);
438 /* ... Write. */
439 regcache_raw_write (regcache, gpnum, raw_buf);
440 }
441 }
442 else if (i386_dword_regnum_p (gdbarch, regnum))
443 {
444 int gpnum = regnum - tdep->eax_regnum;
445
446 /* Read ... */
447 regcache_raw_read (regcache, gpnum, raw_buf);
448 /* ... Modify ... (always little endian). */
449 memcpy (raw_buf, buf, 4);
450 /* ... Write. */
451 regcache_raw_write (regcache, gpnum, raw_buf);
452 }
453 else
454 i386_pseudo_register_write (gdbarch, regcache, regnum, buf);
455 }
456
457 /* Implement the 'ax_pseudo_register_collect' gdbarch method. */
458
459 static int
460 amd64_ax_pseudo_register_collect (struct gdbarch *gdbarch,
461 struct agent_expr *ax, int regnum)
462 {
463 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
464
465 if (i386_byte_regnum_p (gdbarch, regnum))
466 {
467 int gpnum = regnum - tdep->al_regnum;
468
469 if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS)
470 ax_reg_mask (ax, gpnum - AMD64_NUM_LOWER_BYTE_REGS);
471 else
472 ax_reg_mask (ax, gpnum);
473 return 0;
474 }
475 else if (i386_dword_regnum_p (gdbarch, regnum))
476 {
477 int gpnum = regnum - tdep->eax_regnum;
478
479 ax_reg_mask (ax, gpnum);
480 return 0;
481 }
482 else
483 return i386_ax_pseudo_register_collect (gdbarch, ax, regnum);
484 }
485
486
487
488 /* Register classes as defined in the psABI. */
489
490 enum amd64_reg_class
491 {
492 AMD64_INTEGER,
493 AMD64_SSE,
494 AMD64_SSEUP,
495 AMD64_X87,
496 AMD64_X87UP,
497 AMD64_COMPLEX_X87,
498 AMD64_NO_CLASS,
499 AMD64_MEMORY
500 };
501
502 /* Return the union class of CLASS1 and CLASS2. See the psABI for
503 details. */
504
505 static enum amd64_reg_class
506 amd64_merge_classes (enum amd64_reg_class class1, enum amd64_reg_class class2)
507 {
508 /* Rule (a): If both classes are equal, this is the resulting class. */
509 if (class1 == class2)
510 return class1;
511
512 /* Rule (b): If one of the classes is NO_CLASS, the resulting class
513 is the other class. */
514 if (class1 == AMD64_NO_CLASS)
515 return class2;
516 if (class2 == AMD64_NO_CLASS)
517 return class1;
518
519 /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */
520 if (class1 == AMD64_MEMORY || class2 == AMD64_MEMORY)
521 return AMD64_MEMORY;
522
523 /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */
524 if (class1 == AMD64_INTEGER || class2 == AMD64_INTEGER)
525 return AMD64_INTEGER;
526
527 /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class,
528 MEMORY is used as class. */
529 if (class1 == AMD64_X87 || class1 == AMD64_X87UP
530 || class1 == AMD64_COMPLEX_X87 || class2 == AMD64_X87
531 || class2 == AMD64_X87UP || class2 == AMD64_COMPLEX_X87)
532 return AMD64_MEMORY;
533
534 /* Rule (f): Otherwise class SSE is used. */
535 return AMD64_SSE;
536 }
537
538 static void amd64_classify (struct type *type, enum amd64_reg_class theclass[2]);
539
540 /* Return non-zero if TYPE is a non-POD structure or union type. */
541
542 static int
543 amd64_non_pod_p (struct type *type)
544 {
545 /* ??? A class with a base class certainly isn't POD, but does this
546 catch all non-POD structure types? */
547 if (TYPE_CODE (type) == TYPE_CODE_STRUCT && TYPE_N_BASECLASSES (type) > 0)
548 return 1;
549
550 return 0;
551 }
552
553 /* Classify TYPE according to the rules for aggregate (structures and
554 arrays) and union types, and store the result in CLASS. */
555
556 static void
557 amd64_classify_aggregate (struct type *type, enum amd64_reg_class theclass[2])
558 {
559 /* 1. If the size of an object is larger than two eightbytes, or in
560 C++, is a non-POD structure or union type, or contains
561 unaligned fields, it has class memory. */
562 if (TYPE_LENGTH (type) > 16 || amd64_non_pod_p (type))
563 {
564 theclass[0] = theclass[1] = AMD64_MEMORY;
565 return;
566 }
567
568 /* 2. Both eightbytes get initialized to class NO_CLASS. */
569 theclass[0] = theclass[1] = AMD64_NO_CLASS;
570
571 /* 3. Each field of an object is classified recursively so that
572 always two fields are considered. The resulting class is
573 calculated according to the classes of the fields in the
574 eightbyte: */
575
576 if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
577 {
578 struct type *subtype = check_typedef (TYPE_TARGET_TYPE (type));
579
580 /* All fields in an array have the same type. */
581 amd64_classify (subtype, theclass);
582 if (TYPE_LENGTH (type) > 8 && theclass[1] == AMD64_NO_CLASS)
583 theclass[1] = theclass[0];
584 }
585 else
586 {
587 int i;
588
589 /* Structure or union. */
590 gdb_assert (TYPE_CODE (type) == TYPE_CODE_STRUCT
591 || TYPE_CODE (type) == TYPE_CODE_UNION);
592
593 for (i = 0; i < TYPE_NFIELDS (type); i++)
594 {
595 struct type *subtype = check_typedef (TYPE_FIELD_TYPE (type, i));
596 int pos = TYPE_FIELD_BITPOS (type, i) / 64;
597 enum amd64_reg_class subclass[2];
598 int bitsize = TYPE_FIELD_BITSIZE (type, i);
599 int endpos;
600
601 if (bitsize == 0)
602 bitsize = TYPE_LENGTH (subtype) * 8;
603 endpos = (TYPE_FIELD_BITPOS (type, i) + bitsize - 1) / 64;
604
605 /* Ignore static fields. */
606 if (field_is_static (&TYPE_FIELD (type, i)))
607 continue;
608
609 gdb_assert (pos == 0 || pos == 1);
610
611 amd64_classify (subtype, subclass);
612 theclass[pos] = amd64_merge_classes (theclass[pos], subclass[0]);
613 if (bitsize <= 64 && pos == 0 && endpos == 1)
614 /* This is a bit of an odd case: We have a field that would
615 normally fit in one of the two eightbytes, except that
616 it is placed in a way that this field straddles them.
617 This has been seen with a structure containing an array.
618
619 The ABI is a bit unclear in this case, but we assume that
620 this field's class (stored in subclass[0]) must also be merged
621 into class[1]. In other words, our field has a piece stored
622 in the second eight-byte, and thus its class applies to
623 the second eight-byte as well.
624
625 In the case where the field length exceeds 8 bytes,
626 it should not be necessary to merge the field class
627 into class[1]. As LEN > 8, subclass[1] is necessarily
628 different from AMD64_NO_CLASS. If subclass[1] is equal
629 to subclass[0], then the normal class[1]/subclass[1]
630 merging will take care of everything. For subclass[1]
631 to be different from subclass[0], I can only see the case
632 where we have a SSE/SSEUP or X87/X87UP pair, which both
633 use up all 16 bytes of the aggregate, and are already
634 handled just fine (because each portion sits on its own
635 8-byte). */
636 theclass[1] = amd64_merge_classes (theclass[1], subclass[0]);
637 if (pos == 0)
638 theclass[1] = amd64_merge_classes (theclass[1], subclass[1]);
639 }
640 }
641
642 /* 4. Then a post merger cleanup is done: */
643
644 /* Rule (a): If one of the classes is MEMORY, the whole argument is
645 passed in memory. */
646 if (theclass[0] == AMD64_MEMORY || theclass[1] == AMD64_MEMORY)
647 theclass[0] = theclass[1] = AMD64_MEMORY;
648
649 /* Rule (b): If SSEUP is not preceded by SSE, it is converted to
650 SSE. */
651 if (theclass[0] == AMD64_SSEUP)
652 theclass[0] = AMD64_SSE;
653 if (theclass[1] == AMD64_SSEUP && theclass[0] != AMD64_SSE)
654 theclass[1] = AMD64_SSE;
655 }
656
657 /* Classify TYPE, and store the result in CLASS. */
658
659 static void
660 amd64_classify (struct type *type, enum amd64_reg_class theclass[2])
661 {
662 enum type_code code = TYPE_CODE (type);
663 int len = TYPE_LENGTH (type);
664
665 theclass[0] = theclass[1] = AMD64_NO_CLASS;
666
667 /* Arguments of types (signed and unsigned) _Bool, char, short, int,
668 long, long long, and pointers are in the INTEGER class. Similarly,
669 range types, used by languages such as Ada, are also in the INTEGER
670 class. */
671 if ((code == TYPE_CODE_INT || code == TYPE_CODE_ENUM
672 || code == TYPE_CODE_BOOL || code == TYPE_CODE_RANGE
673 || code == TYPE_CODE_CHAR
674 || code == TYPE_CODE_PTR || TYPE_IS_REFERENCE (type))
675 && (len == 1 || len == 2 || len == 4 || len == 8))
676 theclass[0] = AMD64_INTEGER;
677
678 /* Arguments of types float, double, _Decimal32, _Decimal64 and __m64
679 are in class SSE. */
680 else if ((code == TYPE_CODE_FLT || code == TYPE_CODE_DECFLOAT)
681 && (len == 4 || len == 8))
682 /* FIXME: __m64 . */
683 theclass[0] = AMD64_SSE;
684
685 /* Arguments of types __float128, _Decimal128 and __m128 are split into
686 two halves. The least significant ones belong to class SSE, the most
687 significant one to class SSEUP. */
688 else if (code == TYPE_CODE_DECFLOAT && len == 16)
689 /* FIXME: __float128, __m128. */
690 theclass[0] = AMD64_SSE, theclass[1] = AMD64_SSEUP;
691
692 /* The 64-bit mantissa of arguments of type long double belongs to
693 class X87, the 16-bit exponent plus 6 bytes of padding belongs to
694 class X87UP. */
695 else if (code == TYPE_CODE_FLT && len == 16)
696 /* Class X87 and X87UP. */
697 theclass[0] = AMD64_X87, theclass[1] = AMD64_X87UP;
698
699 /* Arguments of complex T where T is one of the types float or
700 double get treated as if they are implemented as:
701
702 struct complexT {
703 T real;
704 T imag;
705 };
706
707 */
708 else if (code == TYPE_CODE_COMPLEX && len == 8)
709 theclass[0] = AMD64_SSE;
710 else if (code == TYPE_CODE_COMPLEX && len == 16)
711 theclass[0] = theclass[1] = AMD64_SSE;
712
713 /* A variable of type complex long double is classified as type
714 COMPLEX_X87. */
715 else if (code == TYPE_CODE_COMPLEX && len == 32)
716 theclass[0] = AMD64_COMPLEX_X87;
717
718 /* Aggregates. */
719 else if (code == TYPE_CODE_ARRAY || code == TYPE_CODE_STRUCT
720 || code == TYPE_CODE_UNION)
721 amd64_classify_aggregate (type, theclass);
722 }
723
724 static enum return_value_convention
725 amd64_return_value (struct gdbarch *gdbarch, struct value *function,
726 struct type *type, struct regcache *regcache,
727 gdb_byte *readbuf, const gdb_byte *writebuf)
728 {
729 enum amd64_reg_class theclass[2];
730 int len = TYPE_LENGTH (type);
731 static int integer_regnum[] = { AMD64_RAX_REGNUM, AMD64_RDX_REGNUM };
732 static int sse_regnum[] = { AMD64_XMM0_REGNUM, AMD64_XMM1_REGNUM };
733 int integer_reg = 0;
734 int sse_reg = 0;
735 int i;
736
737 gdb_assert (!(readbuf && writebuf));
738
739 /* 1. Classify the return type with the classification algorithm. */
740 amd64_classify (type, theclass);
741
742 /* 2. If the type has class MEMORY, then the caller provides space
743 for the return value and passes the address of this storage in
744 %rdi as if it were the first argument to the function. In effect,
745 this address becomes a hidden first argument.
746
747 On return %rax will contain the address that has been passed in
748 by the caller in %rdi. */
749 if (theclass[0] == AMD64_MEMORY)
750 {
751 /* As indicated by the comment above, the ABI guarantees that we
752 can always find the return value just after the function has
753 returned. */
754
755 if (readbuf)
756 {
757 ULONGEST addr;
758
759 regcache_raw_read_unsigned (regcache, AMD64_RAX_REGNUM, &addr);
760 read_memory (addr, readbuf, TYPE_LENGTH (type));
761 }
762
763 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
764 }
765
766 /* 8. If the class is COMPLEX_X87, the real part of the value is
767 returned in %st0 and the imaginary part in %st1. */
768 if (theclass[0] == AMD64_COMPLEX_X87)
769 {
770 if (readbuf)
771 {
772 regcache_raw_read (regcache, AMD64_ST0_REGNUM, readbuf);
773 regcache_raw_read (regcache, AMD64_ST1_REGNUM, readbuf + 16);
774 }
775
776 if (writebuf)
777 {
778 i387_return_value (gdbarch, regcache);
779 regcache_raw_write (regcache, AMD64_ST0_REGNUM, writebuf);
780 regcache_raw_write (regcache, AMD64_ST1_REGNUM, writebuf + 16);
781
782 /* Fix up the tag word such that both %st(0) and %st(1) are
783 marked as valid. */
784 regcache_raw_write_unsigned (regcache, AMD64_FTAG_REGNUM, 0xfff);
785 }
786
787 return RETURN_VALUE_REGISTER_CONVENTION;
788 }
789
790 gdb_assert (theclass[1] != AMD64_MEMORY);
791 gdb_assert (len <= 16);
792
793 for (i = 0; len > 0; i++, len -= 8)
794 {
795 int regnum = -1;
796 int offset = 0;
797
798 switch (theclass[i])
799 {
800 case AMD64_INTEGER:
801 /* 3. If the class is INTEGER, the next available register
802 of the sequence %rax, %rdx is used. */
803 regnum = integer_regnum[integer_reg++];
804 break;
805
806 case AMD64_SSE:
807 /* 4. If the class is SSE, the next available SSE register
808 of the sequence %xmm0, %xmm1 is used. */
809 regnum = sse_regnum[sse_reg++];
810 break;
811
812 case AMD64_SSEUP:
813 /* 5. If the class is SSEUP, the eightbyte is passed in the
814 upper half of the last used SSE register. */
815 gdb_assert (sse_reg > 0);
816 regnum = sse_regnum[sse_reg - 1];
817 offset = 8;
818 break;
819
820 case AMD64_X87:
821 /* 6. If the class is X87, the value is returned on the X87
822 stack in %st0 as 80-bit x87 number. */
823 regnum = AMD64_ST0_REGNUM;
824 if (writebuf)
825 i387_return_value (gdbarch, regcache);
826 break;
827
828 case AMD64_X87UP:
829 /* 7. If the class is X87UP, the value is returned together
830 with the previous X87 value in %st0. */
831 gdb_assert (i > 0 && theclass[0] == AMD64_X87);
832 regnum = AMD64_ST0_REGNUM;
833 offset = 8;
834 len = 2;
835 break;
836
837 case AMD64_NO_CLASS:
838 continue;
839
840 default:
841 gdb_assert (!"Unexpected register class.");
842 }
843
844 gdb_assert (regnum != -1);
845
846 if (readbuf)
847 regcache_raw_read_part (regcache, regnum, offset, std::min (len, 8),
848 readbuf + i * 8);
849 if (writebuf)
850 regcache_raw_write_part (regcache, regnum, offset, std::min (len, 8),
851 writebuf + i * 8);
852 }
853
854 return RETURN_VALUE_REGISTER_CONVENTION;
855 }
856
857
858 static CORE_ADDR
859 amd64_push_arguments (struct regcache *regcache, int nargs,
860 struct value **args, CORE_ADDR sp, int struct_return)
861 {
862 static int integer_regnum[] =
863 {
864 AMD64_RDI_REGNUM, /* %rdi */
865 AMD64_RSI_REGNUM, /* %rsi */
866 AMD64_RDX_REGNUM, /* %rdx */
867 AMD64_RCX_REGNUM, /* %rcx */
868 AMD64_R8_REGNUM, /* %r8 */
869 AMD64_R9_REGNUM /* %r9 */
870 };
871 static int sse_regnum[] =
872 {
873 /* %xmm0 ... %xmm7 */
874 AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM,
875 AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3,
876 AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5,
877 AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7,
878 };
879 struct value **stack_args = XALLOCAVEC (struct value *, nargs);
880 int num_stack_args = 0;
881 int num_elements = 0;
882 int element = 0;
883 int integer_reg = 0;
884 int sse_reg = 0;
885 int i;
886
887 /* Reserve a register for the "hidden" argument. */
888 if (struct_return)
889 integer_reg++;
890
891 for (i = 0; i < nargs; i++)
892 {
893 struct type *type = value_type (args[i]);
894 int len = TYPE_LENGTH (type);
895 enum amd64_reg_class theclass[2];
896 int needed_integer_regs = 0;
897 int needed_sse_regs = 0;
898 int j;
899
900 /* Classify argument. */
901 amd64_classify (type, theclass);
902
903 /* Calculate the number of integer and SSE registers needed for
904 this argument. */
905 for (j = 0; j < 2; j++)
906 {
907 if (theclass[j] == AMD64_INTEGER)
908 needed_integer_regs++;
909 else if (theclass[j] == AMD64_SSE)
910 needed_sse_regs++;
911 }
912
913 /* Check whether enough registers are available, and if the
914 argument should be passed in registers at all. */
915 if (integer_reg + needed_integer_regs > ARRAY_SIZE (integer_regnum)
916 || sse_reg + needed_sse_regs > ARRAY_SIZE (sse_regnum)
917 || (needed_integer_regs == 0 && needed_sse_regs == 0))
918 {
919 /* The argument will be passed on the stack. */
920 num_elements += ((len + 7) / 8);
921 stack_args[num_stack_args++] = args[i];
922 }
923 else
924 {
925 /* The argument will be passed in registers. */
926 const gdb_byte *valbuf = value_contents (args[i]);
927 gdb_byte buf[8];
928
929 gdb_assert (len <= 16);
930
931 for (j = 0; len > 0; j++, len -= 8)
932 {
933 int regnum = -1;
934 int offset = 0;
935
936 switch (theclass[j])
937 {
938 case AMD64_INTEGER:
939 regnum = integer_regnum[integer_reg++];
940 break;
941
942 case AMD64_SSE:
943 regnum = sse_regnum[sse_reg++];
944 break;
945
946 case AMD64_SSEUP:
947 gdb_assert (sse_reg > 0);
948 regnum = sse_regnum[sse_reg - 1];
949 offset = 8;
950 break;
951
952 default:
953 gdb_assert (!"Unexpected register class.");
954 }
955
956 gdb_assert (regnum != -1);
957 memset (buf, 0, sizeof buf);
958 memcpy (buf, valbuf + j * 8, std::min (len, 8));
959 regcache_raw_write_part (regcache, regnum, offset, 8, buf);
960 }
961 }
962 }
963
964 /* Allocate space for the arguments on the stack. */
965 sp -= num_elements * 8;
966
967 /* The psABI says that "The end of the input argument area shall be
968 aligned on a 16 byte boundary." */
969 sp &= ~0xf;
970
971 /* Write out the arguments to the stack. */
972 for (i = 0; i < num_stack_args; i++)
973 {
974 struct type *type = value_type (stack_args[i]);
975 const gdb_byte *valbuf = value_contents (stack_args[i]);
976 int len = TYPE_LENGTH (type);
977
978 write_memory (sp + element * 8, valbuf, len);
979 element += ((len + 7) / 8);
980 }
981
982 /* The psABI says that "For calls that may call functions that use
983 varargs or stdargs (prototype-less calls or calls to functions
984 containing ellipsis (...) in the declaration) %al is used as
985 hidden argument to specify the number of SSE registers used. */
986 regcache_raw_write_unsigned (regcache, AMD64_RAX_REGNUM, sse_reg);
987 return sp;
988 }
989
990 static CORE_ADDR
991 amd64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
992 struct regcache *regcache, CORE_ADDR bp_addr,
993 int nargs, struct value **args, CORE_ADDR sp,
994 int struct_return, CORE_ADDR struct_addr)
995 {
996 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
997 gdb_byte buf[8];
998
999 /* BND registers can be in arbitrary values at the moment of the
1000 inferior call. This can cause boundary violations that are not
1001 due to a real bug or even desired by the user. The best to be done
1002 is set the BND registers to allow access to the whole memory, INIT
1003 state, before pushing the inferior call. */
1004 i387_reset_bnd_regs (gdbarch, regcache);
1005
1006 /* Pass arguments. */
1007 sp = amd64_push_arguments (regcache, nargs, args, sp, struct_return);
1008
1009 /* Pass "hidden" argument". */
1010 if (struct_return)
1011 {
1012 store_unsigned_integer (buf, 8, byte_order, struct_addr);
1013 regcache_cooked_write (regcache, AMD64_RDI_REGNUM, buf);
1014 }
1015
1016 /* Store return address. */
1017 sp -= 8;
1018 store_unsigned_integer (buf, 8, byte_order, bp_addr);
1019 write_memory (sp, buf, 8);
1020
1021 /* Finally, update the stack pointer... */
1022 store_unsigned_integer (buf, 8, byte_order, sp);
1023 regcache_cooked_write (regcache, AMD64_RSP_REGNUM, buf);
1024
1025 /* ...and fake a frame pointer. */
1026 regcache_cooked_write (regcache, AMD64_RBP_REGNUM, buf);
1027
1028 return sp + 16;
1029 }
1030
1031 /* Displaced instruction handling. */
1032
1033 /* A partially decoded instruction.
1034 This contains enough details for displaced stepping purposes. */
1035
1036 struct amd64_insn
1037 {
1038 /* The number of opcode bytes. */
1039 int opcode_len;
1040 /* The offset of the REX/VEX instruction encoding prefix or -1 if
1041 not present. */
1042 int enc_prefix_offset;
1043 /* The offset to the first opcode byte. */
1044 int opcode_offset;
1045 /* The offset to the modrm byte or -1 if not present. */
1046 int modrm_offset;
1047
1048 /* The raw instruction. */
1049 gdb_byte *raw_insn;
1050 };
1051
1052 struct amd64_displaced_step_closure : public displaced_step_closure
1053 {
1054 amd64_displaced_step_closure (int insn_buf_len)
1055 : insn_buf (insn_buf_len, 0)
1056 {}
1057
1058 /* For rip-relative insns, saved copy of the reg we use instead of %rip. */
1059 int tmp_used = 0;
1060 int tmp_regno;
1061 ULONGEST tmp_save;
1062
1063 /* Details of the instruction. */
1064 struct amd64_insn insn_details;
1065
1066 /* The possibly modified insn. */
1067 gdb::byte_vector insn_buf;
1068 };
1069
1070 /* WARNING: Keep onebyte_has_modrm, twobyte_has_modrm in sync with
1071 ../opcodes/i386-dis.c (until libopcodes exports them, or an alternative,
1072 at which point delete these in favor of libopcodes' versions). */
1073
1074 static const unsigned char onebyte_has_modrm[256] = {
1075 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1076 /* ------------------------------- */
1077 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
1078 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
1079 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
1080 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
1081 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
1082 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
1083 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
1084 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
1085 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
1086 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
1087 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
1088 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
1089 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
1090 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
1091 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
1092 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
1093 /* ------------------------------- */
1094 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1095 };
1096
1097 static const unsigned char twobyte_has_modrm[256] = {
1098 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1099 /* ------------------------------- */
1100 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
1101 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
1102 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
1103 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
1104 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
1105 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
1106 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
1107 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
1108 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1109 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
1110 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
1111 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
1112 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
1113 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
1114 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
1115 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
1116 /* ------------------------------- */
1117 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1118 };
1119
1120 static int amd64_syscall_p (const struct amd64_insn *insn, int *lengthp);
1121
1122 static int
1123 rex_prefix_p (gdb_byte pfx)
1124 {
1125 return REX_PREFIX_P (pfx);
1126 }
1127
1128 /* True if PFX is the start of the 2-byte VEX prefix. */
1129
1130 static bool
1131 vex2_prefix_p (gdb_byte pfx)
1132 {
1133 return pfx == 0xc5;
1134 }
1135
1136 /* True if PFX is the start of the 3-byte VEX prefix. */
1137
1138 static bool
1139 vex3_prefix_p (gdb_byte pfx)
1140 {
1141 return pfx == 0xc4;
1142 }
1143
1144 /* Skip the legacy instruction prefixes in INSN.
1145 We assume INSN is properly sentineled so we don't have to worry
1146 about falling off the end of the buffer. */
1147
1148 static gdb_byte *
1149 amd64_skip_prefixes (gdb_byte *insn)
1150 {
1151 while (1)
1152 {
1153 switch (*insn)
1154 {
1155 case DATA_PREFIX_OPCODE:
1156 case ADDR_PREFIX_OPCODE:
1157 case CS_PREFIX_OPCODE:
1158 case DS_PREFIX_OPCODE:
1159 case ES_PREFIX_OPCODE:
1160 case FS_PREFIX_OPCODE:
1161 case GS_PREFIX_OPCODE:
1162 case SS_PREFIX_OPCODE:
1163 case LOCK_PREFIX_OPCODE:
1164 case REPE_PREFIX_OPCODE:
1165 case REPNE_PREFIX_OPCODE:
1166 ++insn;
1167 continue;
1168 default:
1169 break;
1170 }
1171 break;
1172 }
1173
1174 return insn;
1175 }
1176
1177 /* Return an integer register (other than RSP) that is unused as an input
1178 operand in INSN.
1179 In order to not require adding a rex prefix if the insn doesn't already
1180 have one, the result is restricted to RAX ... RDI, sans RSP.
1181 The register numbering of the result follows architecture ordering,
1182 e.g. RDI = 7. */
1183
1184 static int
1185 amd64_get_unused_input_int_reg (const struct amd64_insn *details)
1186 {
1187 /* 1 bit for each reg */
1188 int used_regs_mask = 0;
1189
1190 /* There can be at most 3 int regs used as inputs in an insn, and we have
1191 7 to choose from (RAX ... RDI, sans RSP).
1192 This allows us to take a conservative approach and keep things simple.
1193 E.g. By avoiding RAX, we don't have to specifically watch for opcodes
1194 that implicitly specify RAX. */
1195
1196 /* Avoid RAX. */
1197 used_regs_mask |= 1 << EAX_REG_NUM;
1198 /* Similarily avoid RDX, implicit operand in divides. */
1199 used_regs_mask |= 1 << EDX_REG_NUM;
1200 /* Avoid RSP. */
1201 used_regs_mask |= 1 << ESP_REG_NUM;
1202
1203 /* If the opcode is one byte long and there's no ModRM byte,
1204 assume the opcode specifies a register. */
1205 if (details->opcode_len == 1 && details->modrm_offset == -1)
1206 used_regs_mask |= 1 << (details->raw_insn[details->opcode_offset] & 7);
1207
1208 /* Mark used regs in the modrm/sib bytes. */
1209 if (details->modrm_offset != -1)
1210 {
1211 int modrm = details->raw_insn[details->modrm_offset];
1212 int mod = MODRM_MOD_FIELD (modrm);
1213 int reg = MODRM_REG_FIELD (modrm);
1214 int rm = MODRM_RM_FIELD (modrm);
1215 int have_sib = mod != 3 && rm == 4;
1216
1217 /* Assume the reg field of the modrm byte specifies a register. */
1218 used_regs_mask |= 1 << reg;
1219
1220 if (have_sib)
1221 {
1222 int base = SIB_BASE_FIELD (details->raw_insn[details->modrm_offset + 1]);
1223 int idx = SIB_INDEX_FIELD (details->raw_insn[details->modrm_offset + 1]);
1224 used_regs_mask |= 1 << base;
1225 used_regs_mask |= 1 << idx;
1226 }
1227 else
1228 {
1229 used_regs_mask |= 1 << rm;
1230 }
1231 }
1232
1233 gdb_assert (used_regs_mask < 256);
1234 gdb_assert (used_regs_mask != 255);
1235
1236 /* Finally, find a free reg. */
1237 {
1238 int i;
1239
1240 for (i = 0; i < 8; ++i)
1241 {
1242 if (! (used_regs_mask & (1 << i)))
1243 return i;
1244 }
1245
1246 /* We shouldn't get here. */
1247 internal_error (__FILE__, __LINE__, _("unable to find free reg"));
1248 }
1249 }
1250
1251 /* Extract the details of INSN that we need. */
1252
1253 static void
1254 amd64_get_insn_details (gdb_byte *insn, struct amd64_insn *details)
1255 {
1256 gdb_byte *start = insn;
1257 int need_modrm;
1258
1259 details->raw_insn = insn;
1260
1261 details->opcode_len = -1;
1262 details->enc_prefix_offset = -1;
1263 details->opcode_offset = -1;
1264 details->modrm_offset = -1;
1265
1266 /* Skip legacy instruction prefixes. */
1267 insn = amd64_skip_prefixes (insn);
1268
1269 /* Skip REX/VEX instruction encoding prefixes. */
1270 if (rex_prefix_p (*insn))
1271 {
1272 details->enc_prefix_offset = insn - start;
1273 ++insn;
1274 }
1275 else if (vex2_prefix_p (*insn))
1276 {
1277 /* Don't record the offset in this case because this prefix has
1278 no REX.B equivalent. */
1279 insn += 2;
1280 }
1281 else if (vex3_prefix_p (*insn))
1282 {
1283 details->enc_prefix_offset = insn - start;
1284 insn += 3;
1285 }
1286
1287 details->opcode_offset = insn - start;
1288
1289 if (*insn == TWO_BYTE_OPCODE_ESCAPE)
1290 {
1291 /* Two or three-byte opcode. */
1292 ++insn;
1293 need_modrm = twobyte_has_modrm[*insn];
1294
1295 /* Check for three-byte opcode. */
1296 switch (*insn)
1297 {
1298 case 0x24:
1299 case 0x25:
1300 case 0x38:
1301 case 0x3a:
1302 case 0x7a:
1303 case 0x7b:
1304 ++insn;
1305 details->opcode_len = 3;
1306 break;
1307 default:
1308 details->opcode_len = 2;
1309 break;
1310 }
1311 }
1312 else
1313 {
1314 /* One-byte opcode. */
1315 need_modrm = onebyte_has_modrm[*insn];
1316 details->opcode_len = 1;
1317 }
1318
1319 if (need_modrm)
1320 {
1321 ++insn;
1322 details->modrm_offset = insn - start;
1323 }
1324 }
1325
1326 /* Update %rip-relative addressing in INSN.
1327
1328 %rip-relative addressing only uses a 32-bit displacement.
1329 32 bits is not enough to be guaranteed to cover the distance between where
1330 the real instruction is and where its copy is.
1331 Convert the insn to use base+disp addressing.
1332 We set base = pc + insn_length so we can leave disp unchanged. */
1333
1334 static void
1335 fixup_riprel (struct gdbarch *gdbarch, amd64_displaced_step_closure *dsc,
1336 CORE_ADDR from, CORE_ADDR to, struct regcache *regs)
1337 {
1338 const struct amd64_insn *insn_details = &dsc->insn_details;
1339 int modrm_offset = insn_details->modrm_offset;
1340 gdb_byte *insn = insn_details->raw_insn + modrm_offset;
1341 CORE_ADDR rip_base;
1342 int insn_length;
1343 int arch_tmp_regno, tmp_regno;
1344 ULONGEST orig_value;
1345
1346 /* %rip+disp32 addressing mode, displacement follows ModRM byte. */
1347 ++insn;
1348
1349 /* Compute the rip-relative address. */
1350 insn_length = gdb_buffered_insn_length (gdbarch, dsc->insn_buf.data (),
1351 dsc->insn_buf.size (), from);
1352 rip_base = from + insn_length;
1353
1354 /* We need a register to hold the address.
1355 Pick one not used in the insn.
1356 NOTE: arch_tmp_regno uses architecture ordering, e.g. RDI = 7. */
1357 arch_tmp_regno = amd64_get_unused_input_int_reg (insn_details);
1358 tmp_regno = amd64_arch_reg_to_regnum (arch_tmp_regno);
1359
1360 /* Position of the not-B bit in the 3-byte VEX prefix (in byte 1). */
1361 static constexpr gdb_byte VEX3_NOT_B = 0x20;
1362
1363 /* REX.B should be unset (VEX.!B set) as we were using rip-relative
1364 addressing, but ensure it's unset (set for VEX) anyway, tmp_regno
1365 is not r8-r15. */
1366 if (insn_details->enc_prefix_offset != -1)
1367 {
1368 gdb_byte *pfx = &dsc->insn_buf[insn_details->enc_prefix_offset];
1369 if (rex_prefix_p (pfx[0]))
1370 pfx[0] &= ~REX_B;
1371 else if (vex3_prefix_p (pfx[0]))
1372 pfx[1] |= VEX3_NOT_B;
1373 else
1374 gdb_assert_not_reached ("unhandled prefix");
1375 }
1376
1377 regcache_cooked_read_unsigned (regs, tmp_regno, &orig_value);
1378 dsc->tmp_regno = tmp_regno;
1379 dsc->tmp_save = orig_value;
1380 dsc->tmp_used = 1;
1381
1382 /* Convert the ModRM field to be base+disp. */
1383 dsc->insn_buf[modrm_offset] &= ~0xc7;
1384 dsc->insn_buf[modrm_offset] |= 0x80 + arch_tmp_regno;
1385
1386 regcache_cooked_write_unsigned (regs, tmp_regno, rip_base);
1387
1388 if (debug_displaced)
1389 fprintf_unfiltered (gdb_stdlog, "displaced: %%rip-relative addressing used.\n"
1390 "displaced: using temp reg %d, old value %s, new value %s\n",
1391 dsc->tmp_regno, paddress (gdbarch, dsc->tmp_save),
1392 paddress (gdbarch, rip_base));
1393 }
1394
1395 static void
1396 fixup_displaced_copy (struct gdbarch *gdbarch,
1397 amd64_displaced_step_closure *dsc,
1398 CORE_ADDR from, CORE_ADDR to, struct regcache *regs)
1399 {
1400 const struct amd64_insn *details = &dsc->insn_details;
1401
1402 if (details->modrm_offset != -1)
1403 {
1404 gdb_byte modrm = details->raw_insn[details->modrm_offset];
1405
1406 if ((modrm & 0xc7) == 0x05)
1407 {
1408 /* The insn uses rip-relative addressing.
1409 Deal with it. */
1410 fixup_riprel (gdbarch, dsc, from, to, regs);
1411 }
1412 }
1413 }
1414
1415 struct displaced_step_closure *
1416 amd64_displaced_step_copy_insn (struct gdbarch *gdbarch,
1417 CORE_ADDR from, CORE_ADDR to,
1418 struct regcache *regs)
1419 {
1420 int len = gdbarch_max_insn_length (gdbarch);
1421 /* Extra space for sentinels so fixup_{riprel,displaced_copy} don't have to
1422 continually watch for running off the end of the buffer. */
1423 int fixup_sentinel_space = len;
1424 amd64_displaced_step_closure *dsc
1425 = new amd64_displaced_step_closure (len + fixup_sentinel_space);
1426 gdb_byte *buf = &dsc->insn_buf[0];
1427 struct amd64_insn *details = &dsc->insn_details;
1428
1429 read_memory (from, buf, len);
1430
1431 /* Set up the sentinel space so we don't have to worry about running
1432 off the end of the buffer. An excessive number of leading prefixes
1433 could otherwise cause this. */
1434 memset (buf + len, 0, fixup_sentinel_space);
1435
1436 amd64_get_insn_details (buf, details);
1437
1438 /* GDB may get control back after the insn after the syscall.
1439 Presumably this is a kernel bug.
1440 If this is a syscall, make sure there's a nop afterwards. */
1441 {
1442 int syscall_length;
1443
1444 if (amd64_syscall_p (details, &syscall_length))
1445 buf[details->opcode_offset + syscall_length] = NOP_OPCODE;
1446 }
1447
1448 /* Modify the insn to cope with the address where it will be executed from.
1449 In particular, handle any rip-relative addressing. */
1450 fixup_displaced_copy (gdbarch, dsc, from, to, regs);
1451
1452 write_memory (to, buf, len);
1453
1454 if (debug_displaced)
1455 {
1456 fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ",
1457 paddress (gdbarch, from), paddress (gdbarch, to));
1458 displaced_step_dump_bytes (gdb_stdlog, buf, len);
1459 }
1460
1461 return dsc;
1462 }
1463
1464 static int
1465 amd64_absolute_jmp_p (const struct amd64_insn *details)
1466 {
1467 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1468
1469 if (insn[0] == 0xff)
1470 {
1471 /* jump near, absolute indirect (/4) */
1472 if ((insn[1] & 0x38) == 0x20)
1473 return 1;
1474
1475 /* jump far, absolute indirect (/5) */
1476 if ((insn[1] & 0x38) == 0x28)
1477 return 1;
1478 }
1479
1480 return 0;
1481 }
1482
1483 /* Return non-zero if the instruction DETAILS is a jump, zero otherwise. */
1484
1485 static int
1486 amd64_jmp_p (const struct amd64_insn *details)
1487 {
1488 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1489
1490 /* jump short, relative. */
1491 if (insn[0] == 0xeb)
1492 return 1;
1493
1494 /* jump near, relative. */
1495 if (insn[0] == 0xe9)
1496 return 1;
1497
1498 return amd64_absolute_jmp_p (details);
1499 }
1500
1501 static int
1502 amd64_absolute_call_p (const struct amd64_insn *details)
1503 {
1504 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1505
1506 if (insn[0] == 0xff)
1507 {
1508 /* Call near, absolute indirect (/2) */
1509 if ((insn[1] & 0x38) == 0x10)
1510 return 1;
1511
1512 /* Call far, absolute indirect (/3) */
1513 if ((insn[1] & 0x38) == 0x18)
1514 return 1;
1515 }
1516
1517 return 0;
1518 }
1519
1520 static int
1521 amd64_ret_p (const struct amd64_insn *details)
1522 {
1523 /* NOTE: gcc can emit "repz ; ret". */
1524 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1525
1526 switch (insn[0])
1527 {
1528 case 0xc2: /* ret near, pop N bytes */
1529 case 0xc3: /* ret near */
1530 case 0xca: /* ret far, pop N bytes */
1531 case 0xcb: /* ret far */
1532 case 0xcf: /* iret */
1533 return 1;
1534
1535 default:
1536 return 0;
1537 }
1538 }
1539
1540 static int
1541 amd64_call_p (const struct amd64_insn *details)
1542 {
1543 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1544
1545 if (amd64_absolute_call_p (details))
1546 return 1;
1547
1548 /* call near, relative */
1549 if (insn[0] == 0xe8)
1550 return 1;
1551
1552 return 0;
1553 }
1554
1555 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
1556 length in bytes. Otherwise, return zero. */
1557
1558 static int
1559 amd64_syscall_p (const struct amd64_insn *details, int *lengthp)
1560 {
1561 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1562
1563 if (insn[0] == 0x0f && insn[1] == 0x05)
1564 {
1565 *lengthp = 2;
1566 return 1;
1567 }
1568
1569 return 0;
1570 }
1571
1572 /* Classify the instruction at ADDR using PRED.
1573 Throw an error if the memory can't be read. */
1574
1575 static int
1576 amd64_classify_insn_at (struct gdbarch *gdbarch, CORE_ADDR addr,
1577 int (*pred) (const struct amd64_insn *))
1578 {
1579 struct amd64_insn details;
1580 gdb_byte *buf;
1581 int len, classification;
1582
1583 len = gdbarch_max_insn_length (gdbarch);
1584 buf = (gdb_byte *) alloca (len);
1585
1586 read_code (addr, buf, len);
1587 amd64_get_insn_details (buf, &details);
1588
1589 classification = pred (&details);
1590
1591 return classification;
1592 }
1593
1594 /* The gdbarch insn_is_call method. */
1595
1596 static int
1597 amd64_insn_is_call (struct gdbarch *gdbarch, CORE_ADDR addr)
1598 {
1599 return amd64_classify_insn_at (gdbarch, addr, amd64_call_p);
1600 }
1601
1602 /* The gdbarch insn_is_ret method. */
1603
1604 static int
1605 amd64_insn_is_ret (struct gdbarch *gdbarch, CORE_ADDR addr)
1606 {
1607 return amd64_classify_insn_at (gdbarch, addr, amd64_ret_p);
1608 }
1609
1610 /* The gdbarch insn_is_jump method. */
1611
1612 static int
1613 amd64_insn_is_jump (struct gdbarch *gdbarch, CORE_ADDR addr)
1614 {
1615 return amd64_classify_insn_at (gdbarch, addr, amd64_jmp_p);
1616 }
1617
1618 /* Fix up the state of registers and memory after having single-stepped
1619 a displaced instruction. */
1620
1621 void
1622 amd64_displaced_step_fixup (struct gdbarch *gdbarch,
1623 struct displaced_step_closure *dsc_,
1624 CORE_ADDR from, CORE_ADDR to,
1625 struct regcache *regs)
1626 {
1627 amd64_displaced_step_closure *dsc = (amd64_displaced_step_closure *) dsc_;
1628 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1629 /* The offset we applied to the instruction's address. */
1630 ULONGEST insn_offset = to - from;
1631 gdb_byte *insn = dsc->insn_buf.data ();
1632 const struct amd64_insn *insn_details = &dsc->insn_details;
1633
1634 if (debug_displaced)
1635 fprintf_unfiltered (gdb_stdlog,
1636 "displaced: fixup (%s, %s), "
1637 "insn = 0x%02x 0x%02x ...\n",
1638 paddress (gdbarch, from), paddress (gdbarch, to),
1639 insn[0], insn[1]);
1640
1641 /* If we used a tmp reg, restore it. */
1642
1643 if (dsc->tmp_used)
1644 {
1645 if (debug_displaced)
1646 fprintf_unfiltered (gdb_stdlog, "displaced: restoring reg %d to %s\n",
1647 dsc->tmp_regno, paddress (gdbarch, dsc->tmp_save));
1648 regcache_cooked_write_unsigned (regs, dsc->tmp_regno, dsc->tmp_save);
1649 }
1650
1651 /* The list of issues to contend with here is taken from
1652 resume_execution in arch/x86/kernel/kprobes.c, Linux 2.6.28.
1653 Yay for Free Software! */
1654
1655 /* Relocate the %rip back to the program's instruction stream,
1656 if necessary. */
1657
1658 /* Except in the case of absolute or indirect jump or call
1659 instructions, or a return instruction, the new rip is relative to
1660 the displaced instruction; make it relative to the original insn.
1661 Well, signal handler returns don't need relocation either, but we use the
1662 value of %rip to recognize those; see below. */
1663 if (! amd64_absolute_jmp_p (insn_details)
1664 && ! amd64_absolute_call_p (insn_details)
1665 && ! amd64_ret_p (insn_details))
1666 {
1667 ULONGEST orig_rip;
1668 int insn_len;
1669
1670 regcache_cooked_read_unsigned (regs, AMD64_RIP_REGNUM, &orig_rip);
1671
1672 /* A signal trampoline system call changes the %rip, resuming
1673 execution of the main program after the signal handler has
1674 returned. That makes them like 'return' instructions; we
1675 shouldn't relocate %rip.
1676
1677 But most system calls don't, and we do need to relocate %rip.
1678
1679 Our heuristic for distinguishing these cases: if stepping
1680 over the system call instruction left control directly after
1681 the instruction, the we relocate --- control almost certainly
1682 doesn't belong in the displaced copy. Otherwise, we assume
1683 the instruction has put control where it belongs, and leave
1684 it unrelocated. Goodness help us if there are PC-relative
1685 system calls. */
1686 if (amd64_syscall_p (insn_details, &insn_len)
1687 && orig_rip != to + insn_len
1688 /* GDB can get control back after the insn after the syscall.
1689 Presumably this is a kernel bug.
1690 Fixup ensures its a nop, we add one to the length for it. */
1691 && orig_rip != to + insn_len + 1)
1692 {
1693 if (debug_displaced)
1694 fprintf_unfiltered (gdb_stdlog,
1695 "displaced: syscall changed %%rip; "
1696 "not relocating\n");
1697 }
1698 else
1699 {
1700 ULONGEST rip = orig_rip - insn_offset;
1701
1702 /* If we just stepped over a breakpoint insn, we don't backup
1703 the pc on purpose; this is to match behaviour without
1704 stepping. */
1705
1706 regcache_cooked_write_unsigned (regs, AMD64_RIP_REGNUM, rip);
1707
1708 if (debug_displaced)
1709 fprintf_unfiltered (gdb_stdlog,
1710 "displaced: "
1711 "relocated %%rip from %s to %s\n",
1712 paddress (gdbarch, orig_rip),
1713 paddress (gdbarch, rip));
1714 }
1715 }
1716
1717 /* If the instruction was PUSHFL, then the TF bit will be set in the
1718 pushed value, and should be cleared. We'll leave this for later,
1719 since GDB already messes up the TF flag when stepping over a
1720 pushfl. */
1721
1722 /* If the instruction was a call, the return address now atop the
1723 stack is the address following the copied instruction. We need
1724 to make it the address following the original instruction. */
1725 if (amd64_call_p (insn_details))
1726 {
1727 ULONGEST rsp;
1728 ULONGEST retaddr;
1729 const ULONGEST retaddr_len = 8;
1730
1731 regcache_cooked_read_unsigned (regs, AMD64_RSP_REGNUM, &rsp);
1732 retaddr = read_memory_unsigned_integer (rsp, retaddr_len, byte_order);
1733 retaddr = (retaddr - insn_offset) & 0xffffffffffffffffULL;
1734 write_memory_unsigned_integer (rsp, retaddr_len, byte_order, retaddr);
1735
1736 if (debug_displaced)
1737 fprintf_unfiltered (gdb_stdlog,
1738 "displaced: relocated return addr at %s "
1739 "to %s\n",
1740 paddress (gdbarch, rsp),
1741 paddress (gdbarch, retaddr));
1742 }
1743 }
1744
1745 /* If the instruction INSN uses RIP-relative addressing, return the
1746 offset into the raw INSN where the displacement to be adjusted is
1747 found. Returns 0 if the instruction doesn't use RIP-relative
1748 addressing. */
1749
1750 static int
1751 rip_relative_offset (struct amd64_insn *insn)
1752 {
1753 if (insn->modrm_offset != -1)
1754 {
1755 gdb_byte modrm = insn->raw_insn[insn->modrm_offset];
1756
1757 if ((modrm & 0xc7) == 0x05)
1758 {
1759 /* The displacement is found right after the ModRM byte. */
1760 return insn->modrm_offset + 1;
1761 }
1762 }
1763
1764 return 0;
1765 }
1766
1767 static void
1768 append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf)
1769 {
1770 target_write_memory (*to, buf, len);
1771 *to += len;
1772 }
1773
1774 static void
1775 amd64_relocate_instruction (struct gdbarch *gdbarch,
1776 CORE_ADDR *to, CORE_ADDR oldloc)
1777 {
1778 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1779 int len = gdbarch_max_insn_length (gdbarch);
1780 /* Extra space for sentinels. */
1781 int fixup_sentinel_space = len;
1782 gdb_byte *buf = (gdb_byte *) xmalloc (len + fixup_sentinel_space);
1783 struct amd64_insn insn_details;
1784 int offset = 0;
1785 LONGEST rel32, newrel;
1786 gdb_byte *insn;
1787 int insn_length;
1788
1789 read_memory (oldloc, buf, len);
1790
1791 /* Set up the sentinel space so we don't have to worry about running
1792 off the end of the buffer. An excessive number of leading prefixes
1793 could otherwise cause this. */
1794 memset (buf + len, 0, fixup_sentinel_space);
1795
1796 insn = buf;
1797 amd64_get_insn_details (insn, &insn_details);
1798
1799 insn_length = gdb_buffered_insn_length (gdbarch, insn, len, oldloc);
1800
1801 /* Skip legacy instruction prefixes. */
1802 insn = amd64_skip_prefixes (insn);
1803
1804 /* Adjust calls with 32-bit relative addresses as push/jump, with
1805 the address pushed being the location where the original call in
1806 the user program would return to. */
1807 if (insn[0] == 0xe8)
1808 {
1809 gdb_byte push_buf[32];
1810 CORE_ADDR ret_addr;
1811 int i = 0;
1812
1813 /* Where "ret" in the original code will return to. */
1814 ret_addr = oldloc + insn_length;
1815
1816 /* If pushing an address higher than or equal to 0x80000000,
1817 avoid 'pushq', as that sign extends its 32-bit operand, which
1818 would be incorrect. */
1819 if (ret_addr <= 0x7fffffff)
1820 {
1821 push_buf[0] = 0x68; /* pushq $... */
1822 store_unsigned_integer (&push_buf[1], 4, byte_order, ret_addr);
1823 i = 5;
1824 }
1825 else
1826 {
1827 push_buf[i++] = 0x48; /* sub $0x8,%rsp */
1828 push_buf[i++] = 0x83;
1829 push_buf[i++] = 0xec;
1830 push_buf[i++] = 0x08;
1831
1832 push_buf[i++] = 0xc7; /* movl $imm,(%rsp) */
1833 push_buf[i++] = 0x04;
1834 push_buf[i++] = 0x24;
1835 store_unsigned_integer (&push_buf[i], 4, byte_order,
1836 ret_addr & 0xffffffff);
1837 i += 4;
1838
1839 push_buf[i++] = 0xc7; /* movl $imm,4(%rsp) */
1840 push_buf[i++] = 0x44;
1841 push_buf[i++] = 0x24;
1842 push_buf[i++] = 0x04;
1843 store_unsigned_integer (&push_buf[i], 4, byte_order,
1844 ret_addr >> 32);
1845 i += 4;
1846 }
1847 gdb_assert (i <= sizeof (push_buf));
1848 /* Push the push. */
1849 append_insns (to, i, push_buf);
1850
1851 /* Convert the relative call to a relative jump. */
1852 insn[0] = 0xe9;
1853
1854 /* Adjust the destination offset. */
1855 rel32 = extract_signed_integer (insn + 1, 4, byte_order);
1856 newrel = (oldloc - *to) + rel32;
1857 store_signed_integer (insn + 1, 4, byte_order, newrel);
1858
1859 if (debug_displaced)
1860 fprintf_unfiltered (gdb_stdlog,
1861 "Adjusted insn rel32=%s at %s to"
1862 " rel32=%s at %s\n",
1863 hex_string (rel32), paddress (gdbarch, oldloc),
1864 hex_string (newrel), paddress (gdbarch, *to));
1865
1866 /* Write the adjusted jump into its displaced location. */
1867 append_insns (to, 5, insn);
1868 return;
1869 }
1870
1871 offset = rip_relative_offset (&insn_details);
1872 if (!offset)
1873 {
1874 /* Adjust jumps with 32-bit relative addresses. Calls are
1875 already handled above. */
1876 if (insn[0] == 0xe9)
1877 offset = 1;
1878 /* Adjust conditional jumps. */
1879 else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80)
1880 offset = 2;
1881 }
1882
1883 if (offset)
1884 {
1885 rel32 = extract_signed_integer (insn + offset, 4, byte_order);
1886 newrel = (oldloc - *to) + rel32;
1887 store_signed_integer (insn + offset, 4, byte_order, newrel);
1888 if (debug_displaced)
1889 fprintf_unfiltered (gdb_stdlog,
1890 "Adjusted insn rel32=%s at %s to"
1891 " rel32=%s at %s\n",
1892 hex_string (rel32), paddress (gdbarch, oldloc),
1893 hex_string (newrel), paddress (gdbarch, *to));
1894 }
1895
1896 /* Write the adjusted instruction into its displaced location. */
1897 append_insns (to, insn_length, buf);
1898 }
1899
1900
1901 /* The maximum number of saved registers. This should include %rip. */
1902 #define AMD64_NUM_SAVED_REGS AMD64_NUM_GREGS
1903
1904 struct amd64_frame_cache
1905 {
1906 /* Base address. */
1907 CORE_ADDR base;
1908 int base_p;
1909 CORE_ADDR sp_offset;
1910 CORE_ADDR pc;
1911
1912 /* Saved registers. */
1913 CORE_ADDR saved_regs[AMD64_NUM_SAVED_REGS];
1914 CORE_ADDR saved_sp;
1915 int saved_sp_reg;
1916
1917 /* Do we have a frame? */
1918 int frameless_p;
1919 };
1920
1921 /* Initialize a frame cache. */
1922
1923 static void
1924 amd64_init_frame_cache (struct amd64_frame_cache *cache)
1925 {
1926 int i;
1927
1928 /* Base address. */
1929 cache->base = 0;
1930 cache->base_p = 0;
1931 cache->sp_offset = -8;
1932 cache->pc = 0;
1933
1934 /* Saved registers. We initialize these to -1 since zero is a valid
1935 offset (that's where %rbp is supposed to be stored).
1936 The values start out as being offsets, and are later converted to
1937 addresses (at which point -1 is interpreted as an address, still meaning
1938 "invalid"). */
1939 for (i = 0; i < AMD64_NUM_SAVED_REGS; i++)
1940 cache->saved_regs[i] = -1;
1941 cache->saved_sp = 0;
1942 cache->saved_sp_reg = -1;
1943
1944 /* Frameless until proven otherwise. */
1945 cache->frameless_p = 1;
1946 }
1947
1948 /* Allocate and initialize a frame cache. */
1949
1950 static struct amd64_frame_cache *
1951 amd64_alloc_frame_cache (void)
1952 {
1953 struct amd64_frame_cache *cache;
1954
1955 cache = FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache);
1956 amd64_init_frame_cache (cache);
1957 return cache;
1958 }
1959
1960 /* GCC 4.4 and later, can put code in the prologue to realign the
1961 stack pointer. Check whether PC points to such code, and update
1962 CACHE accordingly. Return the first instruction after the code
1963 sequence or CURRENT_PC, whichever is smaller. If we don't
1964 recognize the code, return PC. */
1965
1966 static CORE_ADDR
1967 amd64_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc,
1968 struct amd64_frame_cache *cache)
1969 {
1970 /* There are 2 code sequences to re-align stack before the frame
1971 gets set up:
1972
1973 1. Use a caller-saved saved register:
1974
1975 leaq 8(%rsp), %reg
1976 andq $-XXX, %rsp
1977 pushq -8(%reg)
1978
1979 2. Use a callee-saved saved register:
1980
1981 pushq %reg
1982 leaq 16(%rsp), %reg
1983 andq $-XXX, %rsp
1984 pushq -8(%reg)
1985
1986 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
1987
1988 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
1989 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
1990 */
1991
1992 gdb_byte buf[18];
1993 int reg, r;
1994 int offset, offset_and;
1995
1996 if (target_read_code (pc, buf, sizeof buf))
1997 return pc;
1998
1999 /* Check caller-saved saved register. The first instruction has
2000 to be "leaq 8(%rsp), %reg". */
2001 if ((buf[0] & 0xfb) == 0x48
2002 && buf[1] == 0x8d
2003 && buf[3] == 0x24
2004 && buf[4] == 0x8)
2005 {
2006 /* MOD must be binary 10 and R/M must be binary 100. */
2007 if ((buf[2] & 0xc7) != 0x44)
2008 return pc;
2009
2010 /* REG has register number. */
2011 reg = (buf[2] >> 3) & 7;
2012
2013 /* Check the REX.R bit. */
2014 if (buf[0] == 0x4c)
2015 reg += 8;
2016
2017 offset = 5;
2018 }
2019 else
2020 {
2021 /* Check callee-saved saved register. The first instruction
2022 has to be "pushq %reg". */
2023 reg = 0;
2024 if ((buf[0] & 0xf8) == 0x50)
2025 offset = 0;
2026 else if ((buf[0] & 0xf6) == 0x40
2027 && (buf[1] & 0xf8) == 0x50)
2028 {
2029 /* Check the REX.B bit. */
2030 if ((buf[0] & 1) != 0)
2031 reg = 8;
2032
2033 offset = 1;
2034 }
2035 else
2036 return pc;
2037
2038 /* Get register. */
2039 reg += buf[offset] & 0x7;
2040
2041 offset++;
2042
2043 /* The next instruction has to be "leaq 16(%rsp), %reg". */
2044 if ((buf[offset] & 0xfb) != 0x48
2045 || buf[offset + 1] != 0x8d
2046 || buf[offset + 3] != 0x24
2047 || buf[offset + 4] != 0x10)
2048 return pc;
2049
2050 /* MOD must be binary 10 and R/M must be binary 100. */
2051 if ((buf[offset + 2] & 0xc7) != 0x44)
2052 return pc;
2053
2054 /* REG has register number. */
2055 r = (buf[offset + 2] >> 3) & 7;
2056
2057 /* Check the REX.R bit. */
2058 if (buf[offset] == 0x4c)
2059 r += 8;
2060
2061 /* Registers in pushq and leaq have to be the same. */
2062 if (reg != r)
2063 return pc;
2064
2065 offset += 5;
2066 }
2067
2068 /* Rigister can't be %rsp nor %rbp. */
2069 if (reg == 4 || reg == 5)
2070 return pc;
2071
2072 /* The next instruction has to be "andq $-XXX, %rsp". */
2073 if (buf[offset] != 0x48
2074 || buf[offset + 2] != 0xe4
2075 || (buf[offset + 1] != 0x81 && buf[offset + 1] != 0x83))
2076 return pc;
2077
2078 offset_and = offset;
2079 offset += buf[offset + 1] == 0x81 ? 7 : 4;
2080
2081 /* The next instruction has to be "pushq -8(%reg)". */
2082 r = 0;
2083 if (buf[offset] == 0xff)
2084 offset++;
2085 else if ((buf[offset] & 0xf6) == 0x40
2086 && buf[offset + 1] == 0xff)
2087 {
2088 /* Check the REX.B bit. */
2089 if ((buf[offset] & 0x1) != 0)
2090 r = 8;
2091 offset += 2;
2092 }
2093 else
2094 return pc;
2095
2096 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
2097 01. */
2098 if (buf[offset + 1] != 0xf8
2099 || (buf[offset] & 0xf8) != 0x70)
2100 return pc;
2101
2102 /* R/M has register. */
2103 r += buf[offset] & 7;
2104
2105 /* Registers in leaq and pushq have to be the same. */
2106 if (reg != r)
2107 return pc;
2108
2109 if (current_pc > pc + offset_and)
2110 cache->saved_sp_reg = amd64_arch_reg_to_regnum (reg);
2111
2112 return std::min (pc + offset + 2, current_pc);
2113 }
2114
2115 /* Similar to amd64_analyze_stack_align for x32. */
2116
2117 static CORE_ADDR
2118 amd64_x32_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc,
2119 struct amd64_frame_cache *cache)
2120 {
2121 /* There are 2 code sequences to re-align stack before the frame
2122 gets set up:
2123
2124 1. Use a caller-saved saved register:
2125
2126 leaq 8(%rsp), %reg
2127 andq $-XXX, %rsp
2128 pushq -8(%reg)
2129
2130 or
2131
2132 [addr32] leal 8(%rsp), %reg
2133 andl $-XXX, %esp
2134 [addr32] pushq -8(%reg)
2135
2136 2. Use a callee-saved saved register:
2137
2138 pushq %reg
2139 leaq 16(%rsp), %reg
2140 andq $-XXX, %rsp
2141 pushq -8(%reg)
2142
2143 or
2144
2145 pushq %reg
2146 [addr32] leal 16(%rsp), %reg
2147 andl $-XXX, %esp
2148 [addr32] pushq -8(%reg)
2149
2150 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
2151
2152 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
2153 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
2154
2155 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
2156
2157 0x83 0xe4 0xf0 andl $-16, %esp
2158 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
2159 */
2160
2161 gdb_byte buf[19];
2162 int reg, r;
2163 int offset, offset_and;
2164
2165 if (target_read_memory (pc, buf, sizeof buf))
2166 return pc;
2167
2168 /* Skip optional addr32 prefix. */
2169 offset = buf[0] == 0x67 ? 1 : 0;
2170
2171 /* Check caller-saved saved register. The first instruction has
2172 to be "leaq 8(%rsp), %reg" or "leal 8(%rsp), %reg". */
2173 if (((buf[offset] & 0xfb) == 0x48 || (buf[offset] & 0xfb) == 0x40)
2174 && buf[offset + 1] == 0x8d
2175 && buf[offset + 3] == 0x24
2176 && buf[offset + 4] == 0x8)
2177 {
2178 /* MOD must be binary 10 and R/M must be binary 100. */
2179 if ((buf[offset + 2] & 0xc7) != 0x44)
2180 return pc;
2181
2182 /* REG has register number. */
2183 reg = (buf[offset + 2] >> 3) & 7;
2184
2185 /* Check the REX.R bit. */
2186 if ((buf[offset] & 0x4) != 0)
2187 reg += 8;
2188
2189 offset += 5;
2190 }
2191 else
2192 {
2193 /* Check callee-saved saved register. The first instruction
2194 has to be "pushq %reg". */
2195 reg = 0;
2196 if ((buf[offset] & 0xf6) == 0x40
2197 && (buf[offset + 1] & 0xf8) == 0x50)
2198 {
2199 /* Check the REX.B bit. */
2200 if ((buf[offset] & 1) != 0)
2201 reg = 8;
2202
2203 offset += 1;
2204 }
2205 else if ((buf[offset] & 0xf8) != 0x50)
2206 return pc;
2207
2208 /* Get register. */
2209 reg += buf[offset] & 0x7;
2210
2211 offset++;
2212
2213 /* Skip optional addr32 prefix. */
2214 if (buf[offset] == 0x67)
2215 offset++;
2216
2217 /* The next instruction has to be "leaq 16(%rsp), %reg" or
2218 "leal 16(%rsp), %reg". */
2219 if (((buf[offset] & 0xfb) != 0x48 && (buf[offset] & 0xfb) != 0x40)
2220 || buf[offset + 1] != 0x8d
2221 || buf[offset + 3] != 0x24
2222 || buf[offset + 4] != 0x10)
2223 return pc;
2224
2225 /* MOD must be binary 10 and R/M must be binary 100. */
2226 if ((buf[offset + 2] & 0xc7) != 0x44)
2227 return pc;
2228
2229 /* REG has register number. */
2230 r = (buf[offset + 2] >> 3) & 7;
2231
2232 /* Check the REX.R bit. */
2233 if ((buf[offset] & 0x4) != 0)
2234 r += 8;
2235
2236 /* Registers in pushq and leaq have to be the same. */
2237 if (reg != r)
2238 return pc;
2239
2240 offset += 5;
2241 }
2242
2243 /* Rigister can't be %rsp nor %rbp. */
2244 if (reg == 4 || reg == 5)
2245 return pc;
2246
2247 /* The next instruction may be "andq $-XXX, %rsp" or
2248 "andl $-XXX, %esp". */
2249 if (buf[offset] != 0x48)
2250 offset--;
2251
2252 if (buf[offset + 2] != 0xe4
2253 || (buf[offset + 1] != 0x81 && buf[offset + 1] != 0x83))
2254 return pc;
2255
2256 offset_and = offset;
2257 offset += buf[offset + 1] == 0x81 ? 7 : 4;
2258
2259 /* Skip optional addr32 prefix. */
2260 if (buf[offset] == 0x67)
2261 offset++;
2262
2263 /* The next instruction has to be "pushq -8(%reg)". */
2264 r = 0;
2265 if (buf[offset] == 0xff)
2266 offset++;
2267 else if ((buf[offset] & 0xf6) == 0x40
2268 && buf[offset + 1] == 0xff)
2269 {
2270 /* Check the REX.B bit. */
2271 if ((buf[offset] & 0x1) != 0)
2272 r = 8;
2273 offset += 2;
2274 }
2275 else
2276 return pc;
2277
2278 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
2279 01. */
2280 if (buf[offset + 1] != 0xf8
2281 || (buf[offset] & 0xf8) != 0x70)
2282 return pc;
2283
2284 /* R/M has register. */
2285 r += buf[offset] & 7;
2286
2287 /* Registers in leaq and pushq have to be the same. */
2288 if (reg != r)
2289 return pc;
2290
2291 if (current_pc > pc + offset_and)
2292 cache->saved_sp_reg = amd64_arch_reg_to_regnum (reg);
2293
2294 return std::min (pc + offset + 2, current_pc);
2295 }
2296
2297 /* Do a limited analysis of the prologue at PC and update CACHE
2298 accordingly. Bail out early if CURRENT_PC is reached. Return the
2299 address where the analysis stopped.
2300
2301 We will handle only functions beginning with:
2302
2303 pushq %rbp 0x55
2304 movq %rsp, %rbp 0x48 0x89 0xe5 (or 0x48 0x8b 0xec)
2305
2306 or (for the X32 ABI):
2307
2308 pushq %rbp 0x55
2309 movl %esp, %ebp 0x89 0xe5 (or 0x8b 0xec)
2310
2311 Any function that doesn't start with one of these sequences will be
2312 assumed to have no prologue and thus no valid frame pointer in
2313 %rbp. */
2314
2315 static CORE_ADDR
2316 amd64_analyze_prologue (struct gdbarch *gdbarch,
2317 CORE_ADDR pc, CORE_ADDR current_pc,
2318 struct amd64_frame_cache *cache)
2319 {
2320 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2321 /* There are two variations of movq %rsp, %rbp. */
2322 static const gdb_byte mov_rsp_rbp_1[3] = { 0x48, 0x89, 0xe5 };
2323 static const gdb_byte mov_rsp_rbp_2[3] = { 0x48, 0x8b, 0xec };
2324 /* Ditto for movl %esp, %ebp. */
2325 static const gdb_byte mov_esp_ebp_1[2] = { 0x89, 0xe5 };
2326 static const gdb_byte mov_esp_ebp_2[2] = { 0x8b, 0xec };
2327
2328 gdb_byte buf[3];
2329 gdb_byte op;
2330
2331 if (current_pc <= pc)
2332 return current_pc;
2333
2334 if (gdbarch_ptr_bit (gdbarch) == 32)
2335 pc = amd64_x32_analyze_stack_align (pc, current_pc, cache);
2336 else
2337 pc = amd64_analyze_stack_align (pc, current_pc, cache);
2338
2339 op = read_code_unsigned_integer (pc, 1, byte_order);
2340
2341 if (op == 0x55) /* pushq %rbp */
2342 {
2343 /* Take into account that we've executed the `pushq %rbp' that
2344 starts this instruction sequence. */
2345 cache->saved_regs[AMD64_RBP_REGNUM] = 0;
2346 cache->sp_offset += 8;
2347
2348 /* If that's all, return now. */
2349 if (current_pc <= pc + 1)
2350 return current_pc;
2351
2352 read_code (pc + 1, buf, 3);
2353
2354 /* Check for `movq %rsp, %rbp'. */
2355 if (memcmp (buf, mov_rsp_rbp_1, 3) == 0
2356 || memcmp (buf, mov_rsp_rbp_2, 3) == 0)
2357 {
2358 /* OK, we actually have a frame. */
2359 cache->frameless_p = 0;
2360 return pc + 4;
2361 }
2362
2363 /* For X32, also check for `movq %esp, %ebp'. */
2364 if (gdbarch_ptr_bit (gdbarch) == 32)
2365 {
2366 if (memcmp (buf, mov_esp_ebp_1, 2) == 0
2367 || memcmp (buf, mov_esp_ebp_2, 2) == 0)
2368 {
2369 /* OK, we actually have a frame. */
2370 cache->frameless_p = 0;
2371 return pc + 3;
2372 }
2373 }
2374
2375 return pc + 1;
2376 }
2377
2378 return pc;
2379 }
2380
2381 /* Work around false termination of prologue - GCC PR debug/48827.
2382
2383 START_PC is the first instruction of a function, PC is its minimal already
2384 determined advanced address. Function returns PC if it has nothing to do.
2385
2386 84 c0 test %al,%al
2387 74 23 je after
2388 <-- here is 0 lines advance - the false prologue end marker.
2389 0f 29 85 70 ff ff ff movaps %xmm0,-0x90(%rbp)
2390 0f 29 4d 80 movaps %xmm1,-0x80(%rbp)
2391 0f 29 55 90 movaps %xmm2,-0x70(%rbp)
2392 0f 29 5d a0 movaps %xmm3,-0x60(%rbp)
2393 0f 29 65 b0 movaps %xmm4,-0x50(%rbp)
2394 0f 29 6d c0 movaps %xmm5,-0x40(%rbp)
2395 0f 29 75 d0 movaps %xmm6,-0x30(%rbp)
2396 0f 29 7d e0 movaps %xmm7,-0x20(%rbp)
2397 after: */
2398
2399 static CORE_ADDR
2400 amd64_skip_xmm_prologue (CORE_ADDR pc, CORE_ADDR start_pc)
2401 {
2402 struct symtab_and_line start_pc_sal, next_sal;
2403 gdb_byte buf[4 + 8 * 7];
2404 int offset, xmmreg;
2405
2406 if (pc == start_pc)
2407 return pc;
2408
2409 start_pc_sal = find_pc_sect_line (start_pc, NULL, 0);
2410 if (start_pc_sal.symtab == NULL
2411 || producer_is_gcc_ge_4 (COMPUNIT_PRODUCER
2412 (SYMTAB_COMPUNIT (start_pc_sal.symtab))) < 6
2413 || start_pc_sal.pc != start_pc || pc >= start_pc_sal.end)
2414 return pc;
2415
2416 next_sal = find_pc_sect_line (start_pc_sal.end, NULL, 0);
2417 if (next_sal.line != start_pc_sal.line)
2418 return pc;
2419
2420 /* START_PC can be from overlayed memory, ignored here. */
2421 if (target_read_code (next_sal.pc - 4, buf, sizeof (buf)) != 0)
2422 return pc;
2423
2424 /* test %al,%al */
2425 if (buf[0] != 0x84 || buf[1] != 0xc0)
2426 return pc;
2427 /* je AFTER */
2428 if (buf[2] != 0x74)
2429 return pc;
2430
2431 offset = 4;
2432 for (xmmreg = 0; xmmreg < 8; xmmreg++)
2433 {
2434 /* 0x0f 0x29 0b??000101 movaps %xmmreg?,-0x??(%rbp) */
2435 if (buf[offset] != 0x0f || buf[offset + 1] != 0x29
2436 || (buf[offset + 2] & 0x3f) != (xmmreg << 3 | 0x5))
2437 return pc;
2438
2439 /* 0b01?????? */
2440 if ((buf[offset + 2] & 0xc0) == 0x40)
2441 {
2442 /* 8-bit displacement. */
2443 offset += 4;
2444 }
2445 /* 0b10?????? */
2446 else if ((buf[offset + 2] & 0xc0) == 0x80)
2447 {
2448 /* 32-bit displacement. */
2449 offset += 7;
2450 }
2451 else
2452 return pc;
2453 }
2454
2455 /* je AFTER */
2456 if (offset - 4 != buf[3])
2457 return pc;
2458
2459 return next_sal.end;
2460 }
2461
2462 /* Return PC of first real instruction. */
2463
2464 static CORE_ADDR
2465 amd64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
2466 {
2467 struct amd64_frame_cache cache;
2468 CORE_ADDR pc;
2469 CORE_ADDR func_addr;
2470
2471 if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL))
2472 {
2473 CORE_ADDR post_prologue_pc
2474 = skip_prologue_using_sal (gdbarch, func_addr);
2475 struct compunit_symtab *cust = find_pc_compunit_symtab (func_addr);
2476
2477 /* Clang always emits a line note before the prologue and another
2478 one after. We trust clang to emit usable line notes. */
2479 if (post_prologue_pc
2480 && (cust != NULL
2481 && COMPUNIT_PRODUCER (cust) != NULL
2482 && startswith (COMPUNIT_PRODUCER (cust), "clang ")))
2483 return std::max (start_pc, post_prologue_pc);
2484 }
2485
2486 amd64_init_frame_cache (&cache);
2487 pc = amd64_analyze_prologue (gdbarch, start_pc, 0xffffffffffffffffLL,
2488 &cache);
2489 if (cache.frameless_p)
2490 return start_pc;
2491
2492 return amd64_skip_xmm_prologue (pc, start_pc);
2493 }
2494
2495
2496 /* Normal frames. */
2497
2498 static void
2499 amd64_frame_cache_1 (struct frame_info *this_frame,
2500 struct amd64_frame_cache *cache)
2501 {
2502 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2503 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2504 gdb_byte buf[8];
2505 int i;
2506
2507 cache->pc = get_frame_func (this_frame);
2508 if (cache->pc != 0)
2509 amd64_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame),
2510 cache);
2511
2512 if (cache->frameless_p)
2513 {
2514 /* We didn't find a valid frame. If we're at the start of a
2515 function, or somewhere half-way its prologue, the function's
2516 frame probably hasn't been fully setup yet. Try to
2517 reconstruct the base address for the stack frame by looking
2518 at the stack pointer. For truly "frameless" functions this
2519 might work too. */
2520
2521 if (cache->saved_sp_reg != -1)
2522 {
2523 /* Stack pointer has been saved. */
2524 get_frame_register (this_frame, cache->saved_sp_reg, buf);
2525 cache->saved_sp = extract_unsigned_integer (buf, 8, byte_order);
2526
2527 /* We're halfway aligning the stack. */
2528 cache->base = ((cache->saved_sp - 8) & 0xfffffffffffffff0LL) - 8;
2529 cache->saved_regs[AMD64_RIP_REGNUM] = cache->saved_sp - 8;
2530
2531 /* This will be added back below. */
2532 cache->saved_regs[AMD64_RIP_REGNUM] -= cache->base;
2533 }
2534 else
2535 {
2536 get_frame_register (this_frame, AMD64_RSP_REGNUM, buf);
2537 cache->base = extract_unsigned_integer (buf, 8, byte_order)
2538 + cache->sp_offset;
2539 }
2540 }
2541 else
2542 {
2543 get_frame_register (this_frame, AMD64_RBP_REGNUM, buf);
2544 cache->base = extract_unsigned_integer (buf, 8, byte_order);
2545 }
2546
2547 /* Now that we have the base address for the stack frame we can
2548 calculate the value of %rsp in the calling frame. */
2549 cache->saved_sp = cache->base + 16;
2550
2551 /* For normal frames, %rip is stored at 8(%rbp). If we don't have a
2552 frame we find it at the same offset from the reconstructed base
2553 address. If we're halfway aligning the stack, %rip is handled
2554 differently (see above). */
2555 if (!cache->frameless_p || cache->saved_sp_reg == -1)
2556 cache->saved_regs[AMD64_RIP_REGNUM] = 8;
2557
2558 /* Adjust all the saved registers such that they contain addresses
2559 instead of offsets. */
2560 for (i = 0; i < AMD64_NUM_SAVED_REGS; i++)
2561 if (cache->saved_regs[i] != -1)
2562 cache->saved_regs[i] += cache->base;
2563
2564 cache->base_p = 1;
2565 }
2566
2567 static struct amd64_frame_cache *
2568 amd64_frame_cache (struct frame_info *this_frame, void **this_cache)
2569 {
2570 struct amd64_frame_cache *cache;
2571
2572 if (*this_cache)
2573 return (struct amd64_frame_cache *) *this_cache;
2574
2575 cache = amd64_alloc_frame_cache ();
2576 *this_cache = cache;
2577
2578 TRY
2579 {
2580 amd64_frame_cache_1 (this_frame, cache);
2581 }
2582 CATCH (ex, RETURN_MASK_ERROR)
2583 {
2584 if (ex.error != NOT_AVAILABLE_ERROR)
2585 throw_exception (ex);
2586 }
2587 END_CATCH
2588
2589 return cache;
2590 }
2591
2592 static enum unwind_stop_reason
2593 amd64_frame_unwind_stop_reason (struct frame_info *this_frame,
2594 void **this_cache)
2595 {
2596 struct amd64_frame_cache *cache =
2597 amd64_frame_cache (this_frame, this_cache);
2598
2599 if (!cache->base_p)
2600 return UNWIND_UNAVAILABLE;
2601
2602 /* This marks the outermost frame. */
2603 if (cache->base == 0)
2604 return UNWIND_OUTERMOST;
2605
2606 return UNWIND_NO_REASON;
2607 }
2608
2609 static void
2610 amd64_frame_this_id (struct frame_info *this_frame, void **this_cache,
2611 struct frame_id *this_id)
2612 {
2613 struct amd64_frame_cache *cache =
2614 amd64_frame_cache (this_frame, this_cache);
2615
2616 if (!cache->base_p)
2617 (*this_id) = frame_id_build_unavailable_stack (cache->pc);
2618 else if (cache->base == 0)
2619 {
2620 /* This marks the outermost frame. */
2621 return;
2622 }
2623 else
2624 (*this_id) = frame_id_build (cache->base + 16, cache->pc);
2625 }
2626
2627 static struct value *
2628 amd64_frame_prev_register (struct frame_info *this_frame, void **this_cache,
2629 int regnum)
2630 {
2631 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2632 struct amd64_frame_cache *cache =
2633 amd64_frame_cache (this_frame, this_cache);
2634
2635 gdb_assert (regnum >= 0);
2636
2637 if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp)
2638 return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp);
2639
2640 if (regnum < AMD64_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
2641 return frame_unwind_got_memory (this_frame, regnum,
2642 cache->saved_regs[regnum]);
2643
2644 return frame_unwind_got_register (this_frame, regnum, regnum);
2645 }
2646
2647 static const struct frame_unwind amd64_frame_unwind =
2648 {
2649 NORMAL_FRAME,
2650 amd64_frame_unwind_stop_reason,
2651 amd64_frame_this_id,
2652 amd64_frame_prev_register,
2653 NULL,
2654 default_frame_sniffer
2655 };
2656
2657 /* Generate a bytecode expression to get the value of the saved PC. */
2658
2659 static void
2660 amd64_gen_return_address (struct gdbarch *gdbarch,
2661 struct agent_expr *ax, struct axs_value *value,
2662 CORE_ADDR scope)
2663 {
2664 /* The following sequence assumes the traditional use of the base
2665 register. */
2666 ax_reg (ax, AMD64_RBP_REGNUM);
2667 ax_const_l (ax, 8);
2668 ax_simple (ax, aop_add);
2669 value->type = register_type (gdbarch, AMD64_RIP_REGNUM);
2670 value->kind = axs_lvalue_memory;
2671 }
2672
2673
2674 /* Signal trampolines. */
2675
2676 /* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and
2677 64-bit variants. This would require using identical frame caches
2678 on both platforms. */
2679
2680 static struct amd64_frame_cache *
2681 amd64_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache)
2682 {
2683 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2684 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2685 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2686 struct amd64_frame_cache *cache;
2687 CORE_ADDR addr;
2688 gdb_byte buf[8];
2689 int i;
2690
2691 if (*this_cache)
2692 return (struct amd64_frame_cache *) *this_cache;
2693
2694 cache = amd64_alloc_frame_cache ();
2695
2696 TRY
2697 {
2698 get_frame_register (this_frame, AMD64_RSP_REGNUM, buf);
2699 cache->base = extract_unsigned_integer (buf, 8, byte_order) - 8;
2700
2701 addr = tdep->sigcontext_addr (this_frame);
2702 gdb_assert (tdep->sc_reg_offset);
2703 gdb_assert (tdep->sc_num_regs <= AMD64_NUM_SAVED_REGS);
2704 for (i = 0; i < tdep->sc_num_regs; i++)
2705 if (tdep->sc_reg_offset[i] != -1)
2706 cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];
2707
2708 cache->base_p = 1;
2709 }
2710 CATCH (ex, RETURN_MASK_ERROR)
2711 {
2712 if (ex.error != NOT_AVAILABLE_ERROR)
2713 throw_exception (ex);
2714 }
2715 END_CATCH
2716
2717 *this_cache = cache;
2718 return cache;
2719 }
2720
2721 static enum unwind_stop_reason
2722 amd64_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame,
2723 void **this_cache)
2724 {
2725 struct amd64_frame_cache *cache =
2726 amd64_sigtramp_frame_cache (this_frame, this_cache);
2727
2728 if (!cache->base_p)
2729 return UNWIND_UNAVAILABLE;
2730
2731 return UNWIND_NO_REASON;
2732 }
2733
2734 static void
2735 amd64_sigtramp_frame_this_id (struct frame_info *this_frame,
2736 void **this_cache, struct frame_id *this_id)
2737 {
2738 struct amd64_frame_cache *cache =
2739 amd64_sigtramp_frame_cache (this_frame, this_cache);
2740
2741 if (!cache->base_p)
2742 (*this_id) = frame_id_build_unavailable_stack (get_frame_pc (this_frame));
2743 else if (cache->base == 0)
2744 {
2745 /* This marks the outermost frame. */
2746 return;
2747 }
2748 else
2749 (*this_id) = frame_id_build (cache->base + 16, get_frame_pc (this_frame));
2750 }
2751
2752 static struct value *
2753 amd64_sigtramp_frame_prev_register (struct frame_info *this_frame,
2754 void **this_cache, int regnum)
2755 {
2756 /* Make sure we've initialized the cache. */
2757 amd64_sigtramp_frame_cache (this_frame, this_cache);
2758
2759 return amd64_frame_prev_register (this_frame, this_cache, regnum);
2760 }
2761
2762 static int
2763 amd64_sigtramp_frame_sniffer (const struct frame_unwind *self,
2764 struct frame_info *this_frame,
2765 void **this_cache)
2766 {
2767 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
2768
2769 /* We shouldn't even bother if we don't have a sigcontext_addr
2770 handler. */
2771 if (tdep->sigcontext_addr == NULL)
2772 return 0;
2773
2774 if (tdep->sigtramp_p != NULL)
2775 {
2776 if (tdep->sigtramp_p (this_frame))
2777 return 1;
2778 }
2779
2780 if (tdep->sigtramp_start != 0)
2781 {
2782 CORE_ADDR pc = get_frame_pc (this_frame);
2783
2784 gdb_assert (tdep->sigtramp_end != 0);
2785 if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end)
2786 return 1;
2787 }
2788
2789 return 0;
2790 }
2791
2792 static const struct frame_unwind amd64_sigtramp_frame_unwind =
2793 {
2794 SIGTRAMP_FRAME,
2795 amd64_sigtramp_frame_unwind_stop_reason,
2796 amd64_sigtramp_frame_this_id,
2797 amd64_sigtramp_frame_prev_register,
2798 NULL,
2799 amd64_sigtramp_frame_sniffer
2800 };
2801
2802
2803 static CORE_ADDR
2804 amd64_frame_base_address (struct frame_info *this_frame, void **this_cache)
2805 {
2806 struct amd64_frame_cache *cache =
2807 amd64_frame_cache (this_frame, this_cache);
2808
2809 return cache->base;
2810 }
2811
2812 static const struct frame_base amd64_frame_base =
2813 {
2814 &amd64_frame_unwind,
2815 amd64_frame_base_address,
2816 amd64_frame_base_address,
2817 amd64_frame_base_address
2818 };
2819
2820 /* Normal frames, but in a function epilogue. */
2821
2822 /* Implement the stack_frame_destroyed_p gdbarch method.
2823
2824 The epilogue is defined here as the 'ret' instruction, which will
2825 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2826 the function's stack frame. */
2827
2828 static int
2829 amd64_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
2830 {
2831 gdb_byte insn;
2832 struct compunit_symtab *cust;
2833
2834 cust = find_pc_compunit_symtab (pc);
2835 if (cust != NULL && COMPUNIT_EPILOGUE_UNWIND_VALID (cust))
2836 return 0;
2837
2838 if (target_read_memory (pc, &insn, 1))
2839 return 0; /* Can't read memory at pc. */
2840
2841 if (insn != 0xc3) /* 'ret' instruction. */
2842 return 0;
2843
2844 return 1;
2845 }
2846
2847 static int
2848 amd64_epilogue_frame_sniffer (const struct frame_unwind *self,
2849 struct frame_info *this_frame,
2850 void **this_prologue_cache)
2851 {
2852 if (frame_relative_level (this_frame) == 0)
2853 return amd64_stack_frame_destroyed_p (get_frame_arch (this_frame),
2854 get_frame_pc (this_frame));
2855 else
2856 return 0;
2857 }
2858
2859 static struct amd64_frame_cache *
2860 amd64_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache)
2861 {
2862 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2863 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2864 struct amd64_frame_cache *cache;
2865 gdb_byte buf[8];
2866
2867 if (*this_cache)
2868 return (struct amd64_frame_cache *) *this_cache;
2869
2870 cache = amd64_alloc_frame_cache ();
2871 *this_cache = cache;
2872
2873 TRY
2874 {
2875 /* Cache base will be %esp plus cache->sp_offset (-8). */
2876 get_frame_register (this_frame, AMD64_RSP_REGNUM, buf);
2877 cache->base = extract_unsigned_integer (buf, 8,
2878 byte_order) + cache->sp_offset;
2879
2880 /* Cache pc will be the frame func. */
2881 cache->pc = get_frame_pc (this_frame);
2882
2883 /* The saved %esp will be at cache->base plus 16. */
2884 cache->saved_sp = cache->base + 16;
2885
2886 /* The saved %eip will be at cache->base plus 8. */
2887 cache->saved_regs[AMD64_RIP_REGNUM] = cache->base + 8;
2888
2889 cache->base_p = 1;
2890 }
2891 CATCH (ex, RETURN_MASK_ERROR)
2892 {
2893 if (ex.error != NOT_AVAILABLE_ERROR)
2894 throw_exception (ex);
2895 }
2896 END_CATCH
2897
2898 return cache;
2899 }
2900
2901 static enum unwind_stop_reason
2902 amd64_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame,
2903 void **this_cache)
2904 {
2905 struct amd64_frame_cache *cache
2906 = amd64_epilogue_frame_cache (this_frame, this_cache);
2907
2908 if (!cache->base_p)
2909 return UNWIND_UNAVAILABLE;
2910
2911 return UNWIND_NO_REASON;
2912 }
2913
2914 static void
2915 amd64_epilogue_frame_this_id (struct frame_info *this_frame,
2916 void **this_cache,
2917 struct frame_id *this_id)
2918 {
2919 struct amd64_frame_cache *cache = amd64_epilogue_frame_cache (this_frame,
2920 this_cache);
2921
2922 if (!cache->base_p)
2923 (*this_id) = frame_id_build_unavailable_stack (cache->pc);
2924 else
2925 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
2926 }
2927
2928 static const struct frame_unwind amd64_epilogue_frame_unwind =
2929 {
2930 NORMAL_FRAME,
2931 amd64_epilogue_frame_unwind_stop_reason,
2932 amd64_epilogue_frame_this_id,
2933 amd64_frame_prev_register,
2934 NULL,
2935 amd64_epilogue_frame_sniffer
2936 };
2937
2938 static struct frame_id
2939 amd64_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2940 {
2941 CORE_ADDR fp;
2942
2943 fp = get_frame_register_unsigned (this_frame, AMD64_RBP_REGNUM);
2944
2945 return frame_id_build (fp + 16, get_frame_pc (this_frame));
2946 }
2947
2948 /* 16 byte align the SP per frame requirements. */
2949
2950 static CORE_ADDR
2951 amd64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
2952 {
2953 return sp & -(CORE_ADDR)16;
2954 }
2955
2956
2957 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
2958 in the floating-point register set REGSET to register cache
2959 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2960
2961 static void
2962 amd64_supply_fpregset (const struct regset *regset, struct regcache *regcache,
2963 int regnum, const void *fpregs, size_t len)
2964 {
2965 struct gdbarch *gdbarch = regcache->arch ();
2966 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2967
2968 gdb_assert (len >= tdep->sizeof_fpregset);
2969 amd64_supply_fxsave (regcache, regnum, fpregs);
2970 }
2971
2972 /* Collect register REGNUM from the register cache REGCACHE and store
2973 it in the buffer specified by FPREGS and LEN as described by the
2974 floating-point register set REGSET. If REGNUM is -1, do this for
2975 all registers in REGSET. */
2976
2977 static void
2978 amd64_collect_fpregset (const struct regset *regset,
2979 const struct regcache *regcache,
2980 int regnum, void *fpregs, size_t len)
2981 {
2982 struct gdbarch *gdbarch = regcache->arch ();
2983 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2984
2985 gdb_assert (len >= tdep->sizeof_fpregset);
2986 amd64_collect_fxsave (regcache, regnum, fpregs);
2987 }
2988
2989 const struct regset amd64_fpregset =
2990 {
2991 NULL, amd64_supply_fpregset, amd64_collect_fpregset
2992 };
2993
2994
2995 /* Figure out where the longjmp will land. Slurp the jmp_buf out of
2996 %rdi. We expect its value to be a pointer to the jmp_buf structure
2997 from which we extract the address that we will land at. This
2998 address is copied into PC. This routine returns non-zero on
2999 success. */
3000
3001 static int
3002 amd64_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
3003 {
3004 gdb_byte buf[8];
3005 CORE_ADDR jb_addr;
3006 struct gdbarch *gdbarch = get_frame_arch (frame);
3007 int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset;
3008 int len = TYPE_LENGTH (builtin_type (gdbarch)->builtin_func_ptr);
3009
3010 /* If JB_PC_OFFSET is -1, we have no way to find out where the
3011 longjmp will land. */
3012 if (jb_pc_offset == -1)
3013 return 0;
3014
3015 get_frame_register (frame, AMD64_RDI_REGNUM, buf);
3016 jb_addr= extract_typed_address
3017 (buf, builtin_type (gdbarch)->builtin_data_ptr);
3018 if (target_read_memory (jb_addr + jb_pc_offset, buf, len))
3019 return 0;
3020
3021 *pc = extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
3022
3023 return 1;
3024 }
3025
3026 static const int amd64_record_regmap[] =
3027 {
3028 AMD64_RAX_REGNUM, AMD64_RCX_REGNUM, AMD64_RDX_REGNUM, AMD64_RBX_REGNUM,
3029 AMD64_RSP_REGNUM, AMD64_RBP_REGNUM, AMD64_RSI_REGNUM, AMD64_RDI_REGNUM,
3030 AMD64_R8_REGNUM, AMD64_R9_REGNUM, AMD64_R10_REGNUM, AMD64_R11_REGNUM,
3031 AMD64_R12_REGNUM, AMD64_R13_REGNUM, AMD64_R14_REGNUM, AMD64_R15_REGNUM,
3032 AMD64_RIP_REGNUM, AMD64_EFLAGS_REGNUM, AMD64_CS_REGNUM, AMD64_SS_REGNUM,
3033 AMD64_DS_REGNUM, AMD64_ES_REGNUM, AMD64_FS_REGNUM, AMD64_GS_REGNUM
3034 };
3035
3036 void
3037 amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch,
3038 const target_desc *default_tdesc)
3039 {
3040 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3041 const struct target_desc *tdesc = info.target_desc;
3042 static const char *const stap_integer_prefixes[] = { "$", NULL };
3043 static const char *const stap_register_prefixes[] = { "%", NULL };
3044 static const char *const stap_register_indirection_prefixes[] = { "(",
3045 NULL };
3046 static const char *const stap_register_indirection_suffixes[] = { ")",
3047 NULL };
3048
3049 /* AMD64 generally uses `fxsave' instead of `fsave' for saving its
3050 floating-point registers. */
3051 tdep->sizeof_fpregset = I387_SIZEOF_FXSAVE;
3052 tdep->fpregset = &amd64_fpregset;
3053
3054 if (! tdesc_has_registers (tdesc))
3055 tdesc = default_tdesc;
3056 tdep->tdesc = tdesc;
3057
3058 tdep->num_core_regs = AMD64_NUM_GREGS + I387_NUM_REGS;
3059 tdep->register_names = amd64_register_names;
3060
3061 if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx512") != NULL)
3062 {
3063 tdep->zmmh_register_names = amd64_zmmh_names;
3064 tdep->k_register_names = amd64_k_names;
3065 tdep->xmm_avx512_register_names = amd64_xmm_avx512_names;
3066 tdep->ymm16h_register_names = amd64_ymmh_avx512_names;
3067
3068 tdep->num_zmm_regs = 32;
3069 tdep->num_xmm_avx512_regs = 16;
3070 tdep->num_ymm_avx512_regs = 16;
3071
3072 tdep->zmm0h_regnum = AMD64_ZMM0H_REGNUM;
3073 tdep->k0_regnum = AMD64_K0_REGNUM;
3074 tdep->xmm16_regnum = AMD64_XMM16_REGNUM;
3075 tdep->ymm16h_regnum = AMD64_YMM16H_REGNUM;
3076 }
3077
3078 if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx") != NULL)
3079 {
3080 tdep->ymmh_register_names = amd64_ymmh_names;
3081 tdep->num_ymm_regs = 16;
3082 tdep->ymm0h_regnum = AMD64_YMM0H_REGNUM;
3083 }
3084
3085 if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx") != NULL)
3086 {
3087 tdep->mpx_register_names = amd64_mpx_names;
3088 tdep->bndcfgu_regnum = AMD64_BNDCFGU_REGNUM;
3089 tdep->bnd0r_regnum = AMD64_BND0R_REGNUM;
3090 }
3091
3092 if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.segments") != NULL)
3093 {
3094 const struct tdesc_feature *feature =
3095 tdesc_find_feature (tdesc, "org.gnu.gdb.i386.segments");
3096 struct tdesc_arch_data *tdesc_data_segments =
3097 (struct tdesc_arch_data *) info.tdep_info;
3098
3099 tdesc_numbered_register (feature, tdesc_data_segments,
3100 AMD64_FSBASE_REGNUM, "fs_base");
3101 tdesc_numbered_register (feature, tdesc_data_segments,
3102 AMD64_GSBASE_REGNUM, "gs_base");
3103 }
3104
3105 if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.pkeys") != NULL)
3106 {
3107 tdep->pkeys_register_names = amd64_pkeys_names;
3108 tdep->pkru_regnum = AMD64_PKRU_REGNUM;
3109 tdep->num_pkeys_regs = 1;
3110 }
3111
3112 tdep->num_byte_regs = 20;
3113 tdep->num_word_regs = 16;
3114 tdep->num_dword_regs = 16;
3115 /* Avoid wiring in the MMX registers for now. */
3116 tdep->num_mmx_regs = 0;
3117
3118 set_gdbarch_pseudo_register_read_value (gdbarch,
3119 amd64_pseudo_register_read_value);
3120 set_gdbarch_pseudo_register_write (gdbarch,
3121 amd64_pseudo_register_write);
3122 set_gdbarch_ax_pseudo_register_collect (gdbarch,
3123 amd64_ax_pseudo_register_collect);
3124
3125 set_tdesc_pseudo_register_name (gdbarch, amd64_pseudo_register_name);
3126
3127 /* AMD64 has an FPU and 16 SSE registers. */
3128 tdep->st0_regnum = AMD64_ST0_REGNUM;
3129 tdep->num_xmm_regs = 16;
3130
3131 /* This is what all the fuss is about. */
3132 set_gdbarch_long_bit (gdbarch, 64);
3133 set_gdbarch_long_long_bit (gdbarch, 64);
3134 set_gdbarch_ptr_bit (gdbarch, 64);
3135
3136 /* In contrast to the i386, on AMD64 a `long double' actually takes
3137 up 128 bits, even though it's still based on the i387 extended
3138 floating-point format which has only 80 significant bits. */
3139 set_gdbarch_long_double_bit (gdbarch, 128);
3140
3141 set_gdbarch_num_regs (gdbarch, AMD64_NUM_REGS);
3142
3143 /* Register numbers of various important registers. */
3144 set_gdbarch_sp_regnum (gdbarch, AMD64_RSP_REGNUM); /* %rsp */
3145 set_gdbarch_pc_regnum (gdbarch, AMD64_RIP_REGNUM); /* %rip */
3146 set_gdbarch_ps_regnum (gdbarch, AMD64_EFLAGS_REGNUM); /* %eflags */
3147 set_gdbarch_fp0_regnum (gdbarch, AMD64_ST0_REGNUM); /* %st(0) */
3148
3149 /* The "default" register numbering scheme for AMD64 is referred to
3150 as the "DWARF Register Number Mapping" in the System V psABI.
3151 The preferred debugging format for all known AMD64 targets is
3152 actually DWARF2, and GCC doesn't seem to support DWARF (that is
3153 DWARF-1), but we provide the same mapping just in case. This
3154 mapping is also used for stabs, which GCC does support. */
3155 set_gdbarch_stab_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
3156 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
3157
3158 /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to
3159 be in use on any of the supported AMD64 targets. */
3160
3161 /* Call dummy code. */
3162 set_gdbarch_push_dummy_call (gdbarch, amd64_push_dummy_call);
3163 set_gdbarch_frame_align (gdbarch, amd64_frame_align);
3164 set_gdbarch_frame_red_zone_size (gdbarch, 128);
3165
3166 set_gdbarch_convert_register_p (gdbarch, i387_convert_register_p);
3167 set_gdbarch_register_to_value (gdbarch, i387_register_to_value);
3168 set_gdbarch_value_to_register (gdbarch, i387_value_to_register);
3169
3170 set_gdbarch_return_value (gdbarch, amd64_return_value);
3171
3172 set_gdbarch_skip_prologue (gdbarch, amd64_skip_prologue);
3173
3174 tdep->record_regmap = amd64_record_regmap;
3175
3176 set_gdbarch_dummy_id (gdbarch, amd64_dummy_id);
3177
3178 /* Hook the function epilogue frame unwinder. This unwinder is
3179 appended to the list first, so that it supercedes the other
3180 unwinders in function epilogues. */
3181 frame_unwind_prepend_unwinder (gdbarch, &amd64_epilogue_frame_unwind);
3182
3183 /* Hook the prologue-based frame unwinders. */
3184 frame_unwind_append_unwinder (gdbarch, &amd64_sigtramp_frame_unwind);
3185 frame_unwind_append_unwinder (gdbarch, &amd64_frame_unwind);
3186 frame_base_set_default (gdbarch, &amd64_frame_base);
3187
3188 set_gdbarch_get_longjmp_target (gdbarch, amd64_get_longjmp_target);
3189
3190 set_gdbarch_relocate_instruction (gdbarch, amd64_relocate_instruction);
3191
3192 set_gdbarch_gen_return_address (gdbarch, amd64_gen_return_address);
3193
3194 /* SystemTap variables and functions. */
3195 set_gdbarch_stap_integer_prefixes (gdbarch, stap_integer_prefixes);
3196 set_gdbarch_stap_register_prefixes (gdbarch, stap_register_prefixes);
3197 set_gdbarch_stap_register_indirection_prefixes (gdbarch,
3198 stap_register_indirection_prefixes);
3199 set_gdbarch_stap_register_indirection_suffixes (gdbarch,
3200 stap_register_indirection_suffixes);
3201 set_gdbarch_stap_is_single_operand (gdbarch,
3202 i386_stap_is_single_operand);
3203 set_gdbarch_stap_parse_special_token (gdbarch,
3204 i386_stap_parse_special_token);
3205 set_gdbarch_insn_is_call (gdbarch, amd64_insn_is_call);
3206 set_gdbarch_insn_is_ret (gdbarch, amd64_insn_is_ret);
3207 set_gdbarch_insn_is_jump (gdbarch, amd64_insn_is_jump);
3208 }
3209
3210
3211 static struct type *
3212 amd64_x32_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
3213 {
3214 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3215
3216 switch (regnum - tdep->eax_regnum)
3217 {
3218 case AMD64_RBP_REGNUM: /* %ebp */
3219 case AMD64_RSP_REGNUM: /* %esp */
3220 return builtin_type (gdbarch)->builtin_data_ptr;
3221 case AMD64_RIP_REGNUM: /* %eip */
3222 return builtin_type (gdbarch)->builtin_func_ptr;
3223 }
3224
3225 return i386_pseudo_register_type (gdbarch, regnum);
3226 }
3227
3228 void
3229 amd64_x32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch,
3230 const target_desc *default_tdesc)
3231 {
3232 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3233
3234 amd64_init_abi (info, gdbarch, default_tdesc);
3235
3236 tdep->num_dword_regs = 17;
3237 set_tdesc_pseudo_register_type (gdbarch, amd64_x32_pseudo_register_type);
3238
3239 set_gdbarch_long_bit (gdbarch, 32);
3240 set_gdbarch_ptr_bit (gdbarch, 32);
3241 }
3242
3243 /* Return the target description for a specified XSAVE feature mask. */
3244
3245 const struct target_desc *
3246 amd64_target_description (uint64_t xcr0)
3247 {
3248 static target_desc *amd64_tdescs \
3249 [2/*AVX*/][2/*MPX*/][2/*AVX512*/][2/*PKRU*/] = {};
3250 target_desc **tdesc;
3251
3252 tdesc = &amd64_tdescs[(xcr0 & X86_XSTATE_AVX) ? 1 : 0]
3253 [(xcr0 & X86_XSTATE_MPX) ? 1 : 0]
3254 [(xcr0 & X86_XSTATE_AVX512) ? 1 : 0]
3255 [(xcr0 & X86_XSTATE_PKRU) ? 1 : 0];
3256
3257 if (*tdesc == NULL)
3258 *tdesc = amd64_create_target_description (xcr0, false, false);
3259
3260 return *tdesc;
3261 }
3262
3263 void
3264 _initialize_amd64_tdep (void)
3265 {
3266 #if GDB_SELF_TEST
3267 struct
3268 {
3269 const char *xml;
3270 uint64_t mask;
3271 } xml_masks[] = {
3272 { "i386/amd64.xml", X86_XSTATE_SSE_MASK },
3273 { "i386/amd64-avx.xml", X86_XSTATE_AVX_MASK },
3274 { "i386/amd64-mpx.xml", X86_XSTATE_MPX_MASK },
3275 { "i386/amd64-avx-mpx.xml", X86_XSTATE_AVX_MPX_MASK },
3276 { "i386/amd64-avx-avx512.xml", X86_XSTATE_AVX_AVX512_MASK },
3277 { "i386/amd64-avx-mpx-avx512-pku.xml",
3278 X86_XSTATE_AVX_MPX_AVX512_PKU_MASK },
3279 };
3280
3281 for (auto &a : xml_masks)
3282 {
3283 auto tdesc = amd64_target_description (a.mask);
3284
3285 selftests::record_xml_tdesc (a.xml, tdesc);
3286 }
3287 #endif /* GDB_SELF_TEST */
3288 }
3289
3290
3291 /* The 64-bit FXSAVE format differs from the 32-bit format in the
3292 sense that the instruction pointer and data pointer are simply
3293 64-bit offsets into the code segment and the data segment instead
3294 of a selector offset pair. The functions below store the upper 32
3295 bits of these pointers (instead of just the 16-bits of the segment
3296 selector). */
3297
3298 /* Fill register REGNUM in REGCACHE with the appropriate
3299 floating-point or SSE register value from *FXSAVE. If REGNUM is
3300 -1, do this for all registers. This function masks off any of the
3301 reserved bits in *FXSAVE. */
3302
3303 void
3304 amd64_supply_fxsave (struct regcache *regcache, int regnum,
3305 const void *fxsave)
3306 {
3307 struct gdbarch *gdbarch = regcache->arch ();
3308 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3309
3310 i387_supply_fxsave (regcache, regnum, fxsave);
3311
3312 if (fxsave
3313 && gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64)
3314 {
3315 const gdb_byte *regs = (const gdb_byte *) fxsave;
3316
3317 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
3318 regcache_raw_supply (regcache, I387_FISEG_REGNUM (tdep), regs + 12);
3319 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
3320 regcache_raw_supply (regcache, I387_FOSEG_REGNUM (tdep), regs + 20);
3321 }
3322 }
3323
3324 /* Similar to amd64_supply_fxsave, but use XSAVE extended state. */
3325
3326 void
3327 amd64_supply_xsave (struct regcache *regcache, int regnum,
3328 const void *xsave)
3329 {
3330 struct gdbarch *gdbarch = regcache->arch ();
3331 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3332
3333 i387_supply_xsave (regcache, regnum, xsave);
3334
3335 if (xsave
3336 && gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64)
3337 {
3338 const gdb_byte *regs = (const gdb_byte *) xsave;
3339
3340 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
3341 regcache_raw_supply (regcache, I387_FISEG_REGNUM (tdep),
3342 regs + 12);
3343 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
3344 regcache_raw_supply (regcache, I387_FOSEG_REGNUM (tdep),
3345 regs + 20);
3346 }
3347 }
3348
3349 /* Fill register REGNUM (if it is a floating-point or SSE register) in
3350 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for
3351 all registers. This function doesn't touch any of the reserved
3352 bits in *FXSAVE. */
3353
3354 void
3355 amd64_collect_fxsave (const struct regcache *regcache, int regnum,
3356 void *fxsave)
3357 {
3358 struct gdbarch *gdbarch = regcache->arch ();
3359 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3360 gdb_byte *regs = (gdb_byte *) fxsave;
3361
3362 i387_collect_fxsave (regcache, regnum, fxsave);
3363
3364 if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64)
3365 {
3366 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
3367 regcache_raw_collect (regcache, I387_FISEG_REGNUM (tdep), regs + 12);
3368 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
3369 regcache_raw_collect (regcache, I387_FOSEG_REGNUM (tdep), regs + 20);
3370 }
3371 }
3372
3373 /* Similar to amd64_collect_fxsave, but use XSAVE extended state. */
3374
3375 void
3376 amd64_collect_xsave (const struct regcache *regcache, int regnum,
3377 void *xsave, int gcore)
3378 {
3379 struct gdbarch *gdbarch = regcache->arch ();
3380 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3381 gdb_byte *regs = (gdb_byte *) xsave;
3382
3383 i387_collect_xsave (regcache, regnum, xsave, gcore);
3384
3385 if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64)
3386 {
3387 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
3388 regcache_raw_collect (regcache, I387_FISEG_REGNUM (tdep),
3389 regs + 12);
3390 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
3391 regcache_raw_collect (regcache, I387_FOSEG_REGNUM (tdep),
3392 regs + 20);
3393 }
3394 }
i386_zmm_regnum_p
int i386_zmm_regnum_p(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:229
set_gdbarch_num_regs
void set_gdbarch_num_regs(struct gdbarch *gdbarch, int num_regs)
Definition: gdbarch.c:2050
gdbarch
Definition: gdbarch.c:127
set_gdbarch_frame_align
void set_gdbarch_frame_align(struct gdbarch *gdbarch, gdbarch_frame_align_ftype frame_align)
Definition: gdbarch.c:3151
X86_XSTATE_AVX_MASK
#define X86_XSTATE_AVX_MASK
Definition: x86-xstate.h:43
set_gdbarch_value_to_register
void set_gdbarch_value_to_register(struct gdbarch *gdbarch, gdbarch_value_to_register_ftype value_to_register)
Definition: gdbarch.c:2639
TYPE_CODE_BOOL
Definition: gdbtypes.h:164
hex_string
char * hex_string(LONGEST num)
Definition: print-utils.c:220
axs_value
Definition: ax-gdb.h:77
amd64_sigtramp_frame_unwind_stop_reason
static enum unwind_stop_reason amd64_sigtramp_frame_unwind_stop_reason(struct frame_info *this_frame, void **this_cache)
Definition: amd64-tdep.c:2722
amd64_x32_init_abi
void amd64_x32_init_abi(struct gdbarch_info info, struct gdbarch *gdbarch, const target_desc *default_tdesc)
Definition: amd64-tdep.c:3229
AMD64_SSEUP
Definition: amd64-tdep.c:494
type_code
type_code
Definition: gdbtypes.h:80
SYMTAB_COMPUNIT
#define SYMTAB_COMPUNIT(symtab)
Definition: symtab.h:1331
TYPE_CODE_ARRAY
Definition: gdbtypes.h:104
amd64_skip_prologue
static CORE_ADDR amd64_skip_prologue(struct gdbarch *gdbarch, CORE_ADDR start_pc)
Definition: amd64-tdep.c:2465
gdbarch_tdep::jb_pc_offset
int jb_pc_offset
Definition: i386-tdep.h:210
AMD64_R8_REGNUM
Definition: amd64-tdep.h:42
set_gdbarch_ps_regnum
void set_gdbarch_ps_regnum(struct gdbarch *gdbarch, int ps_regnum)
Definition: gdbarch.c:2190
AMD64_YMM16H_REGNUM
Definition: amd64-tdep.h:74
frame_id_build
struct frame_id frame_id_build(CORE_ADDR stack_addr, CORE_ADDR code_addr)
Definition: frame.c:624
extract_typed_address
CORE_ADDR extract_typed_address(const gdb_byte *buf, struct type *type)
Definition: findvar.c:154
set_gdbarch_get_longjmp_target
void set_gdbarch_get_longjmp_target(struct gdbarch *gdbarch, gdbarch_get_longjmp_target_ftype get_longjmp_target)
Definition: gdbarch.c:2572
AMD64_EFLAGS_REGNUM
Definition: amd64-tdep.h:51
gdbarch_tdep::zmm0_regnum
int zmm0_regnum
Definition: i386-tdep.h:99
amd64_syscall_p
static int amd64_syscall_p(const struct amd64_insn *insn, int *lengthp)
Definition: amd64-tdep.c:1559
REG_VALID
Definition: common-regcache.h:32
AMD64_ST1_REGNUM
Definition: amd64-tdep.h:59
amd64_reg_class
amd64_reg_class
Definition: amd64-tdep.c:490
TYPE_CODE_ENUM
Definition: gdbtypes.h:108
gdbarch_tdep::xmm16_regnum
int xmm16_regnum
Definition: i386-tdep.h:130
builtin_type::builtin_func_ptr
struct type * builtin_func_ptr
Definition: gdbtypes.h:1565
set_tdesc_pseudo_register_name
void set_tdesc_pseudo_register_name(struct gdbarch *gdbarch, gdbarch_register_name_ftype *pseudo_name)
Definition: target-descriptions.c:1341
producer.h
gdbarch_tdep::num_core_regs
int num_core_regs
Definition: i386-tdep.h:121
get_frame_pc
CORE_ADDR get_frame_pc(struct frame_info *frame)
Definition: frame.c:2376
set_gdbarch_fp0_regnum
void set_gdbarch_fp0_regnum(struct gdbarch *gdbarch, int fp0_regnum)
Definition: gdbarch.c:2207
amd64_arch_reg_to_regnum
static int amd64_arch_reg_to_regnum(int reg)
Definition: amd64-tdep.c:290
X86_XSTATE_SSE_MASK
#define X86_XSTATE_SSE_MASK
Definition: x86-xstate.h:42
amd64_push_arguments
static CORE_ADDR amd64_push_arguments(struct regcache *regcache, int nargs, struct value **args, CORE_ADDR sp, int struct_return)
Definition: amd64-tdep.c:859
append_insns
static void append_insns(CORE_ADDR *to, ULONGEST len, const gdb_byte *buf)
Definition: amd64-tdep.c:1768
amd64_skip_xmm_prologue
static CORE_ADDR amd64_skip_xmm_prologue(CORE_ADDR pc, CORE_ADDR start_pc)
Definition: amd64-tdep.c:2400
CORE_ADDR
bfd_vma CORE_ADDR
Definition: common-types.h:41
value::type
struct type * type
Definition: value.c:266
gdbarch_tdep::mpx_register_names
const char ** mpx_register_names
Definition: i386-tdep.h:176
vex2_prefix_p
static bool vex2_prefix_p(gdb_byte pfx)
Definition: amd64-tdep.c:1131
displaced_step_dump_bytes
void displaced_step_dump_bytes(struct ui_file *file, const gdb_byte *buf, size_t len)
Definition: infrun.c:1721
target_write_memory
int target_write_memory(CORE_ADDR memaddr, const gdb_byte *myaddr, ssize_t len)
Definition: target.c:1451
TYPE_N_BASECLASSES
#define TYPE_N_BASECLASSES(thistype)
Definition: gdbtypes.h:1331
i386_pseudo_register_type
struct type * i386_pseudo_register_type(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:3219
amd64_return_value
static enum return_value_convention amd64_return_value(struct gdbarch *gdbarch, struct value *function, struct type *type, struct regcache *regcache, gdb_byte *readbuf, const gdb_byte *writebuf)
Definition: amd64-tdep.c:725
AMD64_RBX_REGNUM
Definition: amd64-tdep.h:35
gdbarch_tdep::sc_num_regs
int sc_num_regs
Definition: i386-tdep.h:227
ax_reg_mask
void ax_reg_mask(struct agent_expr *ax, int reg)
Definition: ax-general.c:425
amd64_call_p
static int amd64_call_p(const struct amd64_insn *details)
Definition: amd64-tdep.c:1541
set_gdbarch_stap_parse_special_token
void set_gdbarch_stap_parse_special_token(struct gdbarch *gdbarch, gdbarch_stap_parse_special_token_ftype stap_parse_special_token)
Definition: gdbarch.c:4499
i386_dword_regnum_p
int i386_dword_regnum_p(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:201
AMD64_INTEGER
Definition: amd64-tdep.c:492
gdbarch_tdep::ymm16h_register_names
const char ** ymm16h_register_names
Definition: i386-tdep.h:161
amd64_displaced_step_copy_insn
struct displaced_step_closure * amd64_displaced_step_copy_insn(struct gdbarch *gdbarch, CORE_ADDR from, CORE_ADDR to, struct regcache *regs)
Definition: amd64-tdep.c:1416
amd64_insn_is_ret
static int amd64_insn_is_ret(struct gdbarch *gdbarch, CORE_ADDR addr)
Definition: amd64-tdep.c:1605
amd64_init_abi
void amd64_init_abi(struct gdbarch_info info, struct gdbarch *gdbarch, const target_desc *default_tdesc)
Definition: amd64-tdep.c:3037
AMD64_ST0_REGNUM
Definition: amd64-tdep.h:58
AMD64_RIP_REGNUM
Definition: amd64-tdep.h:50
X86_XSTATE_MPX_MASK
#define X86_XSTATE_MPX_MASK
Definition: x86-xstate.h:44
frame_unwind_got_memory
struct value * frame_unwind_got_memory(struct frame_info *frame, int regnum, CORE_ADDR addr)
Definition: frame-unwind.c:233
write_memory_unsigned_integer
void write_memory_unsigned_integer(CORE_ADDR addr, int len, enum bfd_endian byte_order, ULONGEST value)
Definition: corefile.c:417
amd64_register_names
static const char * amd64_register_names[]
Definition: amd64-tdep.c:60
set_tdesc_pseudo_register_type
void set_tdesc_pseudo_register_type(struct gdbarch *gdbarch, gdbarch_register_type_ftype *pseudo_type)
Definition: target-descriptions.c:1351
gdbarch_tdep::sigtramp_start
CORE_ADDR sigtramp_start
Definition: i386-tdep.h:216
gdbarch_tdep::ymm16_regnum
int ymm16_regnum
Definition: i386-tdep.h:136
_initialize_amd64_tdep
void _initialize_amd64_tdep(void)
Definition: amd64-tdep.c:3264
set_gdbarch_relocate_instruction
void set_gdbarch_relocate_instruction(struct gdbarch *gdbarch, gdbarch_relocate_instruction_ftype relocate_instruction)
Definition: gdbarch.c:4024
symtab_and_line::end
CORE_ADDR end
Definition: symtab.h:1760
amd64_frame_cache::saved_sp_reg
int saved_sp_reg
Definition: amd64-tdep.c:1915
set_gdbarch_gen_return_address
void set_gdbarch_gen_return_address(struct gdbarch *gdbarch, gdbarch_gen_return_address_ftype gen_return_address)
Definition: gdbarch.c:4764
i387_supply_fxsave
void i387_supply_fxsave(struct regcache *regcache, int regnum, const void *fxsave)
Definition: i387-tdep.c:586
set_gdbarch_stab_reg_to_regnum
void set_gdbarch_stab_reg_to_regnum(struct gdbarch *gdbarch, gdbarch_stab_reg_to_regnum_ftype stab_reg_to_regnum)
Definition: gdbarch.c:2224
amd64_get_insn_details
static void amd64_get_insn_details(gdb_byte *insn, struct amd64_insn *details)
Definition: amd64-tdep.c:1254
AMD64_FS_REGNUM
Definition: amd64-tdep.h:56
gdbarch_tdep::num_mmx_regs
int num_mmx_regs
Definition: i386-tdep.h:74
gdbarch_ptr_bit
int gdbarch_ptr_bit(struct gdbarch *gdbarch)
Definition: gdbarch.c:1831
amd64_insn_is_jump
static int amd64_insn_is_jump(struct gdbarch *gdbarch, CORE_ADDR addr)
Definition: amd64-tdep.c:1613
AMD64_K0_REGNUM
Definition: amd64-tdep.h:76
set_gdbarch_stap_register_prefixes
void set_gdbarch_stap_register_prefixes(struct gdbarch *gdbarch, const char *const *stap_register_prefixes)
Definition: gdbarch.c:4366
lval_register
Definition: defs.h:385
amd64_frame_unwind_stop_reason
static enum unwind_stop_reason amd64_frame_unwind_stop_reason(struct frame_info *this_frame, void **this_cache)
Definition: amd64-tdep.c:2593
TYPE_CODE_RANGE
Definition: gdbtypes.h:127
amd64_sigtramp_frame_cache
static struct amd64_frame_cache * amd64_sigtramp_frame_cache(struct frame_info *this_frame, void **this_cache)
Definition: amd64-tdep.c:2681
builtin_type
const struct builtin_type * builtin_type(struct gdbarch *gdbarch)
Definition: gdbtypes.c:5217
mark_value_bytes_unavailable
void mark_value_bytes_unavailable(struct value *value, LONGEST offset, LONGEST length)
Definition: value.c:601
RETURN_MASK_ERROR
Definition: common-exceptions.h:43
frame_id_build_unavailable_stack
struct frame_id frame_id_build_unavailable_stack(CORE_ADDR code_addr)
Definition: frame.c:597
TYPE_CODE_INT
Definition: gdbtypes.h:111
AMD64_SS_REGNUM
Definition: amd64-tdep.h:53
AMD64_XMM1_REGNUM
Definition: amd64-tdep.h:64
set_gdbarch_frame_red_zone_size
void set_gdbarch_frame_red_zone_size(struct gdbarch *gdbarch, int frame_red_zone_size)
Definition: gdbarch.c:3184
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Definition: amd64-tdep.h:36
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struct gdbarch_tdep_info * tdep_info
Definition: gdbarch.h:1644
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TYPE_FIELD
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Definition: gdbtypes.h:1370
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static void amd64_supply_fpregset(const struct regset *regset, struct regcache *regcache, int regnum, const void *fpregs, size_t len)
Definition: amd64-tdep.c:2962
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Definition: gdbtypes.h:1495
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struct gdbarch_tdep * gdbarch_tdep(struct gdbarch *gdbarch)
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Definition: amd64-tdep.c:1904
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static struct value * amd64_sigtramp_frame_prev_register(struct frame_info *this_frame, void **this_cache, int regnum)
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Definition: common-exceptions.h:259
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static const char * amd64_ymm_avx512_names[]
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int ymm0_regnum
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int num_xmm_avx512_regs
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Definition: frame.h:678
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const char * paddress(struct gdbarch *gdbarch, CORE_ADDR addr)
Definition: utils.c:2745
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Definition: infrun.h:249
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void set_gdbarch_stap_register_indirection_suffixes(struct gdbarch *gdbarch, const char *const *stap_register_indirection_suffixes)
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Definition: frame-unwind.c:246
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int i386_xmm_regnum_p(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:326
TYPE_IS_REFERENCE
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Definition: gdbtypes.h:332
i387_value_to_register
void i387_value_to_register(struct frame_info *frame, int regnum, struct type *type, const gdb_byte *from)
Definition: i387-tdep.c:381
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ULONGEST read_code_unsigned_integer(CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
Definition: corefile.c:346
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static enum amd64_reg_class amd64_merge_classes(enum amd64_reg_class class1, enum amd64_reg_class class2)
Definition: amd64-tdep.c:506
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struct compunit_symtab * find_pc_compunit_symtab(CORE_ADDR pc)
Definition: symtab.c:2988
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int target_read_code(CORE_ADDR memaddr, gdb_byte *myaddr, ssize_t len)
Definition: target.c:1433
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Definition: regset.h:34
i386_byte_regnum_p
int i386_byte_regnum_p(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:179
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static struct amd64_frame_cache * amd64_alloc_frame_cache(void)
Definition: amd64-tdep.c:1951
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int i386_ymm_regnum_p(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:270
NOT_AVAILABLE_ERROR
Definition: common-exceptions.h:82
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static CORE_ADDR amd64_analyze_prologue(struct gdbarch *gdbarch, CORE_ADDR pc, CORE_ADDR current_pc, struct amd64_frame_cache *cache)
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void amd64_collect_fxsave(const struct regcache *regcache, int regnum, void *fxsave)
Definition: amd64-tdep.c:3355
AMD64_ES_REGNUM
Definition: amd64-tdep.h:55
TRY
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Definition: common-exceptions.h:246
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void set_gdbarch_stap_integer_prefixes(struct gdbarch *gdbarch, const char *const *stap_integer_prefixes)
Definition: gdbarch.c:4332
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Definition: amd64-tdep.c:1052
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static const int amd64_dwarf_regmap_len
Definition: amd64-tdep.c:238
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Definition: i387-tdep.c:1835
AMD64_YMM0H_REGNUM
Definition: amd64-tdep.h:66
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static struct frame_id amd64_dummy_id(struct gdbarch *gdbarch, struct frame_info *this_frame)
Definition: amd64-tdep.c:2939
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int tdesc_numbered_register(const struct tdesc_feature *feature, struct tdesc_arch_data *data, int regno, const char *name)
Definition: target-descriptions.c:1084
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void frame_base_set_default(struct gdbarch *gdbarch, const struct frame_base *default_base)
Definition: frame-base.c:95
X86_XSTATE_PKRU
#define X86_XSTATE_PKRU
Definition: x86-xstate.h:38
amd64_dwarf_regmap
static int amd64_dwarf_regmap[]
Definition: amd64-tdep.c:159
amd64_create_target_description
target_desc * amd64_create_target_description(uint64_t xcr0, bool is_x32, bool is_linux)
Definition: amd64.c:38
amd64_mpx_names
static const char * amd64_mpx_names[]
Definition: amd64-tdep.c:110
set_gdbarch_pseudo_register_write
void set_gdbarch_pseudo_register_write(struct gdbarch *gdbarch, gdbarch_pseudo_register_write_ftype pseudo_register_write)
Definition: gdbarch.c:2032
amd64_xmm_avx512_names
static const char * amd64_xmm_avx512_names[]
Definition: amd64-tdep.c:145
amd64_ymmh_names
static const char * amd64_ymmh_names[]
Definition: amd64-tdep.c:94
set_gdbarch_pseudo_register_read_value
void set_gdbarch_pseudo_register_read_value(struct gdbarch *gdbarch, gdbarch_pseudo_register_read_value_ftype pseudo_register_read_value)
Definition: gdbarch.c:2008
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struct type * check_typedef(struct type *type)
Definition: gdbtypes.c:2421
NORMAL_FRAME
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AMD64_FTAG_REGNUM
Definition: amd64-tdep.h:62
gdbarch_max_insn_length
ULONGEST gdbarch_max_insn_length(struct gdbarch *gdbarch)
Definition: gdbarch.c:3905
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const gdb_byte * value_contents(struct value *value)
Definition: value.c:1407
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Definition: common-exceptions.h:254
regcache_raw_read_part
enum register_status regcache_raw_read_part(struct regcache *regcache, int regnum, int offset, int len, gdb_byte *buf)
Definition: regcache.c:943
i387_collect_fxsave
void i387_collect_fxsave(const struct regcache *regcache, int regnum, void *fxsave)
Definition: i387-tdep.c:669
X86_XSTATE_AVX_AVX512_MASK
#define X86_XSTATE_AVX_AVX512_MASK
Definition: x86-xstate.h:46
TYPE_CODE_CHAR
Definition: gdbtypes.h:160
amd64_supply_fxsave
void amd64_supply_fxsave(struct regcache *regcache, int regnum, const void *fxsave)
Definition: amd64-tdep.c:3304
AMD64_R12_REGNUM
Definition: amd64-tdep.h:46
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static int amd64_non_pod_p(struct type *type)
Definition: amd64-tdep.c:543
amd64_ymm_names
static const char * amd64_ymm_names[]
Definition: amd64-tdep.c:78
field_is_static
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int gdbarch_sp_regnum(struct gdbarch *gdbarch)
Definition: gdbarch.c:2146
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set_gdbarch_insn_is_ret
void set_gdbarch_insn_is_ret(struct gdbarch *gdbarch, gdbarch_insn_is_ret_ftype insn_is_ret)
Definition: gdbarch.c:4880
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static void amd64_collect_fpregset(const struct regset *regset, const struct regcache *regcache, int regnum, void *fpregs, size_t len)
Definition: amd64-tdep.c:2978
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static ULONGEST extract_unsigned_integer(const gdb_byte *addr, int len, enum bfd_endian byte_order)
Definition: defs.h:577
regcache_cooked_read_unsigned
enum register_status regcache_cooked_read_unsigned(struct regcache *regcache, int regnum, ULONGEST *val)
Definition: regcache.c:777
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const char ** ymmh_register_names
Definition: i386-tdep.h:154
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set_gdbarch_sp_regnum
void set_gdbarch_sp_regnum(struct gdbarch *gdbarch, int sp_regnum)
Definition: gdbarch.c:2156
debug_displaced
int debug_displaced
Definition: infrun.c:156
AMD64_DS_REGNUM
Definition: amd64-tdep.h:54
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struct type * register_type(struct gdbarch *gdbarch, int regnum)
Definition: regcache.c:152
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void set_gdbarch_dummy_id(struct gdbarch *gdbarch, gdbarch_dummy_id_ftype dummy_id)
Definition: gdbarch.c:2340
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static int amd64_jmp_p(const struct amd64_insn *details)
Definition: amd64-tdep.c:1486
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Definition: utils.c:2018
I387_XMM0_REGNUM
#define I387_XMM0_REGNUM(tdep)
Definition: i387-tdep.h:64
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struct_return
Definition: arm-tdep.h:88
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int frameless_p
Definition: amd64-tdep.c:1918
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TYPE_CODE_FLT
Definition: gdbtypes.h:116
AMD64_ZMM0H_REGNUM
Definition: amd64-tdep.h:78
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static void amd64_classify(struct type *type, enum amd64_reg_class theclass[2])
Definition: amd64-tdep.c:660
gdb_assert_not_reached
#define gdb_assert_not_reached(message)
Definition: gdb_assert.h:55
AMD64_R10_REGNUM
Definition: amd64-tdep.h:44
amd64_supply_xsave
void amd64_supply_xsave(struct regcache *regcache, int regnum, const void *xsave)
Definition: amd64-tdep.c:3327
gdbarch_tdep::ax_regnum
int ax_regnum
Definition: i386-tdep.h:111
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static const int amd64_arch_regmap_len
Definition: amd64-tdep.c:283
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static int rex_prefix_p(gdb_byte pfx)
Definition: amd64-tdep.c:1123
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enum bfd_endian gdbarch_byte_order(struct gdbarch *gdbarch)
Definition: gdbarch.c:1509
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#define AMD64_NUM_GREGS
Definition: amd64-tdep.h:86
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#define I387_FISEG_REGNUM(tdep)
Definition: i387-tdep.h:59
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AMD64_X87
Definition: amd64-tdep.c:495
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int num_ymm_avx512_regs
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Definition: amd64-tdep.h:41
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static void amd64_frame_this_id(struct frame_info *this_frame, void **this_cache, struct frame_id *this_id)
Definition: amd64-tdep.c:2610
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const char ** pkeys_register_names
Definition: i386-tdep.h:201
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static const struct frame_base amd64_frame_base
Definition: amd64-tdep.c:2812
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void set_gdbarch_stap_register_indirection_prefixes(struct gdbarch *gdbarch, const char *const *stap_register_indirection_prefixes)
Definition: gdbarch.c:4400
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type
Definition: gdbtypes.h:749
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int find_pc_partial_function(CORE_ADDR pc, const char **name, CORE_ADDR *address, CORE_ADDR *endaddr)
Definition: blockframe.c:320
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#define VALUE_REGNUM(val)
Definition: value.h:451
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set_gdbarch_register_to_value
void set_gdbarch_register_to_value(struct gdbarch *gdbarch, gdbarch_register_to_value_ftype register_to_value)
Definition: gdbarch.c:2622
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Definition: corefile.c:274
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Definition: amd64-tdep.h:57
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Definition: frame-unwind.c:174
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Definition: symtab.h:1463
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static bool vex3_prefix_p(gdb_byte pfx)
Definition: amd64-tdep.c:1139
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#define AMD64_NUM_LOWER_BYTE_REGS
Definition: amd64-tdep.c:307
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mach_port_t mach_port_t name mach_port_t mach_port_t name kern_return_t int status
Definition: gnu-nat.c:1822
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Definition: ax-general.c:125
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Definition: common-utils.h:107
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amd64_displaced_step_closure(int insn_buf_len)
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static struct value * amd64_frame_prev_register(struct frame_info *this_frame, void **this_cache, int regnum)
Definition: amd64-tdep.c:2628
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int producer_is_gcc_ge_4(const char *producer)
Definition: producer.c:27
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const char ** zmmh_register_names
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static CORE_ADDR amd64_push_dummy_call(struct gdbarch *gdbarch, struct value *function, struct regcache *regcache, CORE_ADDR bp_addr, int nargs, struct value **args, CORE_ADDR sp, int struct_return, CORE_ADDR struct_addr)
Definition: amd64-tdep.c:991
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int opcode_len
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AMD64_RSI_REGNUM
Definition: amd64-tdep.h:38
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static void amd64_gen_return_address(struct gdbarch *gdbarch, struct agent_expr *ax, struct axs_value *value, CORE_ADDR scope)
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int num_byte_regs
Definition: i386-tdep.h:102
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static void amd64_init_frame_cache(struct amd64_frame_cache *cache)
Definition: amd64-tdep.c:1924
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static const char * amd64_byte_names[]
Definition: amd64-tdep.c:299
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static int amd64_absolute_jmp_p(const struct amd64_insn *details)
Definition: amd64-tdep.c:1465
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static const char * amd64_dword_names[]
Definition: amd64-tdep.c:319
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void read_memory(CORE_ADDR memaddr, gdb_byte *myaddr, ssize_t len)
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Definition: gdbarch.c:4897
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int i386_word_regnum_p(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:190
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int pkru_regnum
Definition: i386-tdep.h:198
I387_FOSEG_REGNUM
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Definition: i387-tdep.h:61
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static CORE_ADDR amd64_frame_align(struct gdbarch *gdbarch, CORE_ADDR sp)
Definition: amd64-tdep.c:2951
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ULONGEST get_frame_register_unsigned(struct frame_info *frame, int regnum)
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struct symtab * symtab
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int i387_convert_register_p(struct gdbarch *gdbarch, int regnum, struct type *type)
Definition: i387-tdep.c:327
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Definition: gdbtypes.h:106
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Definition: gdbtypes.h:1380
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static int amd64_sigtramp_frame_sniffer(const struct frame_unwind *self, struct frame_info *this_frame, void **this_cache)
Definition: amd64-tdep.c:2763
frame-base.h
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static CORE_ADDR amd64_x32_analyze_stack_align(CORE_ADDR pc, CORE_ADDR current_pc, struct amd64_frame_cache *cache)
Definition: amd64-tdep.c:2118
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const char ** xmm_avx512_register_names
Definition: i386-tdep.h:189
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Definition: gdbarch.c:1623
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int i386_ax_pseudo_register_collect(struct gdbarch *gdbarch, struct agent_expr *ax, int regnum)
Definition: i386-tdep.c:3625
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Definition: amd64-tdep.h:39
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struct amd64_insn insn_details
Definition: amd64-tdep.c:1064
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Definition: gdbtypes.h:1374
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Definition: regdef.h:22
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Definition: gdb_assert.h:32
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const struct target_desc * target_desc
Definition: gdbarch.h:1660
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Definition: i387-tdep.c:1306
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Definition: value.c:169
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const char ** register_names
Definition: frv-tdep.c:88
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const struct regset amd64_fpregset
Definition: amd64-tdep.c:2989
AMD64_R13_REGNUM
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static const struct frame_unwind amd64_epilogue_frame_unwind
Definition: amd64-tdep.c:2928
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Definition: i387-tdep.h:117
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CORE_ADDR saved_regs[AMD64_NUM_SAVED_REGS]
Definition: amd64-tdep.c:1913
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Definition: symtab.h:1746
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Definition: regcache.c:957
TYPE_CODE_PTR
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AMD64_MXCSR_REGNUM
Definition: amd64-tdep.h:65
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const char * i386_pseudo_register_name(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:457
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gdb_byte * raw_insn
Definition: amd64-tdep.c:1049
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static int amd64_dwarf_reg_to_regnum(struct gdbarch *gdbarch, int reg)
Definition: amd64-tdep.c:245
AMD64_RBP_REGNUM
Definition: amd64-tdep.h:40
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Definition: common-exceptions.c:312
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Definition: i386-tdep.h:71
AMD64_PKRU_REGNUM
Definition: amd64-tdep.h:80
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static int amd64_get_unused_input_int_reg(const struct amd64_insn *details)
Definition: amd64-tdep.c:1185
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Definition: common-types.h:38
AMD64_RDX_REGNUM
Definition: amd64-tdep.h:37
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static int amd64_epilogue_frame_sniffer(const struct frame_unwind *self, struct frame_info *this_frame, void **this_prologue_cache)
Definition: amd64-tdep.c:2848
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static const char * amd64_pseudo_register_name(struct gdbarch *gdbarch, int regnum)
Definition: amd64-tdep.c:329
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Definition: i386-tdep.h:158
AMD64_FCTRL_REGNUM
Definition: amd64-tdep.h:60
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Definition: defs.h:264
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Definition: amd64-tdep.c:2499
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static const char * amd64_pkeys_names[]
Definition: amd64-tdep.c:152
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Definition: gdbtypes.h:1226
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Definition: gdbarch.c:2605
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Definition: amd64-tdep.c:1335
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Definition: gdbtypes.h:1238
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enum register_status regcache_raw_read(struct regcache *regcache, int regnum, gdb_byte *buf)
Definition: regcache.c:565
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const int * record_regmap
Definition: i386-tdep.h:244
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Definition: frame-unwind.c:223
regcache_cooked_write_unsigned
void regcache_cooked_write_unsigned(struct regcache *regcache, int regnum, ULONGEST val)
Definition: regcache.c:806
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#define X86_XSTATE_AVX512
Definition: x86-xstate.h:35
gdbarch_tdep::num_pkeys_regs
int num_pkeys_regs
Definition: i386-tdep.h:195
target_read_memory
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Definition: target.c:1370
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int num_xmm_regs
Definition: i386-tdep.h:124
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Definition: target-descriptions.c:591
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struct type * builtin_data_ptr
Definition: gdbtypes.h:1554
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int i386_stap_is_single_operand(struct gdbarch *gdbarch, const char *s)
Definition: i386-tdep.c:4058
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void set_gdbarch_stap_is_single_operand(struct gdbarch *gdbarch, gdbarch_stap_is_single_operand_ftype stap_is_single_operand)
Definition: gdbarch.c:4475
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static const char * amd64_k_names[]
Definition: amd64-tdep.c:115
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Definition: amd64-tdep.c:1910
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Definition: amd64-tdep.c:1060
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static void amd64_sigtramp_frame_this_id(struct frame_info *this_frame, void **this_cache, struct frame_id *this_id)
Definition: amd64-tdep.c:2735
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Definition: agent.c:65
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void regcache_raw_write_unsigned(struct regcache *regcache, int regnum, ULONGEST val)
Definition: regcache.c:640
code
int code
Definition: ser-unix.c:239
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void get_frame_register(struct frame_info *frame, int regnum, gdb_byte *buf)
Definition: frame.c:1165
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#define TYPE_NFIELDS(thistype)
Definition: gdbtypes.h:1239
target-descriptions.h
fixup_displaced_copy
static void fixup_displaced_copy(struct gdbarch *gdbarch, amd64_displaced_step_closure *dsc, CORE_ADDR from, CORE_ADDR to, struct regcache *regs)
Definition: amd64-tdep.c:1396
regcache::arch
gdbarch * arch() const
Definition: regcache.c:221
amd64_frame_cache
static struct amd64_frame_cache * amd64_frame_cache(struct frame_info *this_frame, void **this_cache)
Definition: amd64-tdep.c:2568
AMD64_R14_REGNUM
Definition: amd64-tdep.h:48
amd64_sigtramp_frame_unwind
static const struct frame_unwind amd64_sigtramp_frame_unwind
Definition: amd64-tdep.c:2792
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int eax_regnum
Definition: i386-tdep.h:118
amd64_record_regmap
static const int amd64_record_regmap[]
Definition: amd64-tdep.c:3026
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CORE_ADDR pc
Definition: symtab.h:1759
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static LONGEST extract_signed_integer(const gdb_byte *addr, int len, enum bfd_endian byte_order)
Definition: defs.h:570
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struct m32c_reg regs[M32C_MAX_NUM_REGS]
Definition: m32c-tdep.c:110
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Definition: frame-unwind.h:144
AMD64_XMM0_REGNUM
Definition: amd64-tdep.h:63
gdbarch_tdep::tdesc
const struct target_desc * tdesc
Definition: i386-tdep.h:204
i386_ymm_avx512_regnum_p
int i386_ymm_avx512_regnum_p(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:296
ax_const_l
void ax_const_l(struct agent_expr *x, LONGEST l)
Definition: ax-general.c:229
gdbarch_tdep::fpregset
const struct regset * fpregset
Definition: i386-tdep.h:253
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gdb::def_vector< gdb_byte > byte_vector
Definition: byte-vector.h:58
X86_XSTATE_MPX
#define X86_XSTATE_MPX
Definition: x86-xstate.h:29
amd64_insn
Definition: amd64-tdep.c:1036
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void regcache_raw_supply(struct regcache *regcache, int regnum, const void *buf)
Definition: regcache.c:1004
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int * sc_reg_offset
Definition: i386-tdep.h:226
ULONGEST
unsigned long long ULONGEST
Definition: common-types.h:53
amd64_insn_is_call
static int amd64_insn_is_call(struct gdbarch *gdbarch, CORE_ADDR addr)
Definition: amd64-tdep.c:1597
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int i387_register_to_value(struct frame_info *frame, int regnum, struct type *type, gdb_byte *to, int *optimizedp, int *unavailablep)
Definition: i387-tdep.c:348
AMD64_NO_CLASS
Definition: amd64-tdep.c:498
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struct symtab_and_line find_pc_sect_line(CORE_ADDR pc, struct obj_section *section, int notcurrent)
Definition: symtab.c:3051
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const struct tdesc_feature * tdesc_find_feature(const struct target_desc *target_desc, const char *name)
Definition: target-descriptions.c:942
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Definition: target-descriptions.c:670
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int register_size(struct gdbarch *gdbarch, int regnum)
Definition: regcache.c:164
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Definition: regcache.h:232
amd64_insn::modrm_offset
int modrm_offset
Definition: amd64-tdep.c:1046
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static void amd64_relocate_instruction(struct gdbarch *gdbarch, CORE_ADDR *to, CORE_ADDR oldloc)
Definition: amd64-tdep.c:1775
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Definition: gdbarch.h:1626
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void set_gdbarch_long_double_bit(struct gdbarch *gdbarch, int long_double_bit)
Definition: gdbarch.c:1756
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#define gdb_stdlog
Definition: utils.h:349
value_type
struct type * value_type(const struct value *value)
Definition: value.c:1095
set_gdbarch_long_bit
void set_gdbarch_long_bit(struct gdbarch *gdbarch, int long_bit)
Definition: gdbarch.c:1606
set_gdbarch_return_value
void set_gdbarch_return_value(struct gdbarch *gdbarch, gdbarch_return_value_ftype return_value)
Definition: gdbarch.c:2738
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const struct bfd_arch_info * gdbarch_bfd_arch_info(struct gdbarch *gdbarch)
Definition: gdbarch.c:1500
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void regcache_raw_collect(const struct regcache *regcache, int regnum, void *buf)
Definition: regcache.c:1085
AMD64_NUM_REGS
#define AMD64_NUM_REGS
Definition: amd64-tdep.h:88
amd64_displaced_step_fixup
void amd64_displaced_step_fixup(struct gdbarch *gdbarch, struct displaced_step_closure *dsc_, CORE_ADDR from, CORE_ADDR to, struct regcache *regs)
Definition: amd64-tdep.c:1622
X86_XSTATE_AVX_MPX_MASK
#define X86_XSTATE_AVX_MPX_MASK
Definition: x86-xstate.h:45
amd64_collect_xsave
void amd64_collect_xsave(const struct regcache *regcache, int regnum, void *xsave, int gcore)
Definition: amd64-tdep.c:3376
amd64_pseudo_register_write
static void amd64_pseudo_register_write(struct gdbarch *gdbarch, struct regcache *regcache, int regnum, const gdb_byte *buf)
Definition: amd64-tdep.c:410
regset.h
amd64_displaced_step_closure::insn_buf
gdb::byte_vector insn_buf
Definition: amd64-tdep.c:1067
AMD64_FSBASE_REGNUM
Definition: amd64-tdep.h:81
amd64_frame_cache::saved_sp
CORE_ADDR saved_sp
Definition: amd64-tdep.c:1914
amd64_absolute_call_p
static int amd64_absolute_call_p(const struct amd64_insn *details)
Definition: amd64-tdep.c:1502
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gdb_byte * value_contents_raw(struct value *value)
Definition: value.c:1158
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int line
Definition: symtab.h:1757
AMD64_XMM16_REGNUM
Definition: amd64-tdep.h:72
amd64_ax_pseudo_register_collect
static int amd64_ax_pseudo_register_collect(struct gdbarch *gdbarch, struct agent_expr *ax, int regnum)
Definition: amd64-tdep.c:460
TYPE_LENGTH
#define TYPE_LENGTH(thistype)
Definition: gdbtypes.h:1235
set_gdbarch_ptr_bit
void set_gdbarch_ptr_bit(struct gdbarch *gdbarch, int ptr_bit)
Definition: gdbarch.c:1841
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enum register_status regcache_raw_read_unsigned(struct regcache *regcache, int regnum, ULONGEST *val)
Definition: regcache.c:612
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void set_gdbarch_push_dummy_call(struct gdbarch *gdbarch, gdbarch_push_dummy_call_ftype push_dummy_call)
Definition: gdbarch.c:2381
COMPUNIT_EPILOGUE_UNWIND_VALID
#define COMPUNIT_EPILOGUE_UNWIND_VALID(cust)
Definition: symtab.h:1468
AMD64_BND0R_REGNUM
Definition: amd64-tdep.h:68
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static const int amd64_arch_regmap[16]
Definition: amd64-tdep.c:263
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ULONGEST read_memory_unsigned_integer(CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
Definition: corefile.c:326
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static CORE_ADDR amd64_frame_base_address(struct frame_info *this_frame, void **this_cache)
Definition: amd64-tdep.c:2804
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void set_gdbarch_insn_is_call(struct gdbarch *gdbarch, gdbarch_insn_is_call_ftype insn_is_call)
Definition: gdbarch.c:4863
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void write_memory(CORE_ADDR memaddr, const bfd_byte *myaddr, ssize_t len)
Definition: corefile.c:394
set_gdbarch_skip_prologue
void set_gdbarch_skip_prologue(struct gdbarch *gdbarch, gdbarch_skip_prologue_ftype skip_prologue)
Definition: gdbarch.c:2772
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const char ** k_register_names
Definition: i386-tdep.h:183
gdbarch_tdep::k0_regnum
int k0_regnum
Definition: i386-tdep.h:92
i387-tdep.h
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void i386_pseudo_register_read_into_value(struct gdbarch *gdbarch, struct regcache *regcache, int regnum, struct value *result_value)
Definition: i386-tdep.c:3271
amd64_stack_frame_destroyed_p
static int amd64_stack_frame_destroyed_p(struct gdbarch *gdbarch, CORE_ADDR pc)
Definition: amd64-tdep.c:2829
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void i387_supply_xsave(struct regcache *regcache, int regnum, const void *xsave)
Definition: i387-tdep.c:898
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int enc_prefix_offset
Definition: amd64-tdep.c:1042
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Definition: defs.h:251
AMD64_BNDCFGU_REGNUM
Definition: amd64-tdep.h:70
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#define I387_NUM_REGS
Definition: i387-tdep.h:30
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const struct target_desc * amd64_target_description(uint64_t xcr0)
Definition: amd64-tdep.c:3246
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enum bfd_endian byte_order
Definition: gdbarch.c:137
X86_XSTATE_AVX
#define X86_XSTATE_AVX
Definition: x86-xstate.h:26
set_gdbarch_pc_regnum
void set_gdbarch_pc_regnum(struct gdbarch *gdbarch, int pc_regnum)
Definition: gdbarch.c:2173
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static int amd64_classify_insn_at(struct gdbarch *gdbarch, CORE_ADDR addr, int(*pred)(const struct amd64_insn *))
Definition: amd64-tdep.c:1576
gdbcmd.h
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static const char * amd64_word_names[]
Definition: amd64-tdep.c:311
amd64_pseudo_register_read_value
static struct value * amd64_pseudo_register_read_value(struct gdbarch *gdbarch, struct regcache *regcache, int regnum)
Definition: amd64-tdep.c:349
tdesc_has_registers
int tdesc_has_registers(const struct target_desc *target_desc)
Definition: target-descriptions.c:926
get_frame_func
CORE_ADDR get_frame_func(struct frame_info *this_frame)
Definition: frame.c:1001
gdbarch_tdep::bnd0r_regnum
int bnd0r_regnum
Definition: i386-tdep.h:165
store_signed_integer
static void store_signed_integer(gdb_byte *addr, int len, enum bfd_endian byte_order, LONGEST val)
Definition: defs.h:597
gdbarch_tdep::al_regnum
int al_regnum
Definition: i386-tdep.h:105
amd64_frame_cache::sp_offset
CORE_ADDR sp_offset
Definition: amd64-tdep.c:1909
amd64_skip_prefixes
static gdb_byte * amd64_skip_prefixes(gdb_byte *insn)
Definition: amd64-tdep.c:1149
AMD64_GSBASE_REGNUM
Definition: amd64-tdep.h:82
frame_id
Definition: frame.h:111
get_frame_arch
struct gdbarch * get_frame_arch(struct frame_info *this_frame)
Definition: frame.c:2691
X86_XSTATE_AVX_MPX_AVX512_PKU_MASK
#define X86_XSTATE_AVX_MPX_AVX512_PKU_MASK
Definition: x86-xstate.h:47
block.h
LONGEST
long long LONGEST
Definition: common-types.h:52
gdb_buffered_insn_length
int gdb_buffered_insn_length(struct gdbarch *gdbarch, const gdb_byte *insn, int max_len, CORE_ADDR addr)
Definition: disasm.c:871
AMD64_R15_REGNUM
Definition: amd64-tdep.h:49
i386_pseudo_register_write
void i386_pseudo_register_write(struct gdbarch *gdbarch, struct regcache *regcache, int regnum, const gdb_byte *buf)
Definition: i386-tdep.c:3478
AMD64_CS_REGNUM
Definition: amd64-tdep.h:52
regcache_cooked_write
void regcache_cooked_write(struct regcache *regcache, int regnum, const gdb_byte *buf)
Definition: regcache.c:873
gdbarch_tdep::zmm0h_regnum
int zmm0h_regnum
Definition: i386-tdep.h:180
gdbarch_tdep::num_dword_regs
int num_dword_regs
Definition: i386-tdep.h:114
symfile.h
TYPE_CODE_COMPLEX
Definition: gdbtypes.h:167
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static void store_unsigned_integer(gdb_byte *addr, int len, enum bfd_endian byte_order, ULONGEST val)
Definition: defs.h:604
AMD64_COMPLEX_X87
Definition: amd64-tdep.c:497
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static struct amd64_frame_cache * amd64_epilogue_frame_cache(struct frame_info *this_frame, void **this_cache)
Definition: amd64-tdep.c:2860
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void regcache_raw_write(struct regcache *regcache, int regnum, const gdb_byte *buf)
Definition: regcache.c:831
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static const char * amd64_zmmh_names[]
Definition: amd64-tdep.c:121
amd64_epilogue_frame_this_id
static void amd64_epilogue_frame_this_id(struct frame_info *this_frame, void **this_cache, struct frame_id *this_id)
Definition: amd64-tdep.c:2915
amd64_frame_unwind
static const struct frame_unwind amd64_frame_unwind
Definition: amd64-tdep.c:2647
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int bndcfgu_regnum
Definition: i386-tdep.h:173