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x86-dregs.c
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1 /* Debug register code for x86 (i386 and x86-64).
2
3 Copyright (C) 2001-2018 Free Software Foundation, Inc.
4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19
20 #include "common-defs.h"
21 #include "x86-dregs.h"
22 #include "break-common.h"
23
24 /* Support for hardware watchpoints and breakpoints using the x86
25 debug registers.
26
27 This provides several functions for inserting and removing
28 hardware-assisted breakpoints and watchpoints, testing if one or
29 more of the watchpoints triggered and at what address, checking
30 whether a given region can be watched, etc.
31
32 The functions below implement debug registers sharing by reference
33 counts, and allow to watch regions up to 16 bytes long. */
34
35 /* Accessor macros for low-level function vector. */
36
37 /* Can we update the inferior's debug registers? */
38 #define x86_dr_low_can_set_addr() (x86_dr_low.set_addr != NULL)
39
40 /* Update the inferior's debug register REGNUM from STATE. */
41 #define x86_dr_low_set_addr(new_state, i) \
42 (x86_dr_low.set_addr ((i), (new_state)->dr_mirror[(i)]))
43
44 /* Return the inferior's debug register REGNUM. */
45 #define x86_dr_low_get_addr(i) (x86_dr_low.get_addr ((i)))
46
47 /* Can we update the inferior's DR7 control register? */
48 #define x86_dr_low_can_set_control() (x86_dr_low.set_control != NULL)
49
50 /* Update the inferior's DR7 debug control register from STATE. */
51 #define x86_dr_low_set_control(new_state) \
52 (x86_dr_low.set_control ((new_state)->dr_control_mirror))
53
54 /* Return the value of the inferior's DR7 debug control register. */
55 #define x86_dr_low_get_control() (x86_dr_low.get_control ())
56
57 /* Return the value of the inferior's DR6 debug status register. */
58 #define x86_dr_low_get_status() (x86_dr_low.get_status ())
59
60 /* Return the debug register size, in bytes. */
61 #define x86_get_debug_register_length() \
62 (x86_dr_low.debug_register_length)
63
64 /* Support for 8-byte wide hw watchpoints. */
65 #define TARGET_HAS_DR_LEN_8 (x86_get_debug_register_length () == 8)
66
67 /* DR7 Debug Control register fields. */
68
69 /* How many bits to skip in DR7 to get to R/W and LEN fields. */
70 #define DR_CONTROL_SHIFT 16
71 /* How many bits in DR7 per R/W and LEN field for each watchpoint. */
72 #define DR_CONTROL_SIZE 4
73
74 /* Watchpoint/breakpoint read/write fields in DR7. */
75 #define DR_RW_EXECUTE (0x0) /* Break on instruction execution. */
76 #define DR_RW_WRITE (0x1) /* Break on data writes. */
77 #define DR_RW_READ (0x3) /* Break on data reads or writes. */
78
79 /* This is here for completeness. No platform supports this
80 functionality yet (as of March 2001). Note that the DE flag in the
81 CR4 register needs to be set to support this. */
82 #ifndef DR_RW_IORW
83 #define DR_RW_IORW (0x2) /* Break on I/O reads or writes. */
84 #endif
85
86 /* Watchpoint/breakpoint length fields in DR7. The 2-bit left shift
87 is so we could OR this with the read/write field defined above. */
88 #define DR_LEN_1 (0x0 << 2) /* 1-byte region watch or breakpoint. */
89 #define DR_LEN_2 (0x1 << 2) /* 2-byte region watch. */
90 #define DR_LEN_4 (0x3 << 2) /* 4-byte region watch. */
91 #define DR_LEN_8 (0x2 << 2) /* 8-byte region watch (AMD64). */
92
93 /* Local and Global Enable flags in DR7.
94
95 When the Local Enable flag is set, the breakpoint/watchpoint is
96 enabled only for the current task; the processor automatically
97 clears this flag on every task switch. When the Global Enable flag
98 is set, the breakpoint/watchpoint is enabled for all tasks; the
99 processor never clears this flag.
100
101 Currently, all watchpoint are locally enabled. If you need to
102 enable them globally, read the comment which pertains to this in
103 x86_insert_aligned_watchpoint below. */
104 #define DR_LOCAL_ENABLE_SHIFT 0 /* Extra shift to the local enable bit. */
105 #define DR_GLOBAL_ENABLE_SHIFT 1 /* Extra shift to the global enable bit. */
106 #define DR_ENABLE_SIZE 2 /* Two enable bits per debug register. */
107
108 /* Local and global exact breakpoint enable flags (a.k.a. slowdown
109 flags). These are only required on i386, to allow detection of the
110 exact instruction which caused a watchpoint to break; i486 and
111 later processors do that automatically. We set these flags for
112 backwards compatibility. */
113 #define DR_LOCAL_SLOWDOWN (0x100)
114 #define DR_GLOBAL_SLOWDOWN (0x200)
115
116 /* Fields reserved by Intel. This includes the GD (General Detect
117 Enable) flag, which causes a debug exception to be generated when a
118 MOV instruction accesses one of the debug registers.
119
120 FIXME: My Intel manual says we should use 0xF800, not 0xFC00. */
121 #define DR_CONTROL_RESERVED (0xFC00)
122
123 /* Auxiliary helper macros. */
124
125 /* A value that masks all fields in DR7 that are reserved by Intel. */
126 #define X86_DR_CONTROL_MASK (~DR_CONTROL_RESERVED)
127
128 /* The I'th debug register is vacant if its Local and Global Enable
129 bits are reset in the Debug Control register. */
130 #define X86_DR_VACANT(state, i) \
131 (((state)->dr_control_mirror & (3 << (DR_ENABLE_SIZE * (i)))) == 0)
132
133 /* Locally enable the break/watchpoint in the I'th debug register. */
134 #define X86_DR_LOCAL_ENABLE(state, i) \
135 do { \
136 (state)->dr_control_mirror |= \
137 (1 << (DR_LOCAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \
138 } while (0)
139
140 /* Globally enable the break/watchpoint in the I'th debug register. */
141 #define X86_DR_GLOBAL_ENABLE(state, i) \
142 do { \
143 (state)->dr_control_mirror |= \
144 (1 << (DR_GLOBAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \
145 } while (0)
146
147 /* Disable the break/watchpoint in the I'th debug register. */
148 #define X86_DR_DISABLE(state, i) \
149 do { \
150 (state)->dr_control_mirror &= \
151 ~(3 << (DR_ENABLE_SIZE * (i))); \
152 } while (0)
153
154 /* Set in DR7 the RW and LEN fields for the I'th debug register. */
155 #define X86_DR_SET_RW_LEN(state, i, rwlen) \
156 do { \
157 (state)->dr_control_mirror &= \
158 ~(0x0f << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \
159 (state)->dr_control_mirror |= \
160 ((rwlen) << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \
161 } while (0)
162
163 /* Get from DR7 the RW and LEN fields for the I'th debug register. */
164 #define X86_DR_GET_RW_LEN(dr7, i) \
165 (((dr7) \
166 >> (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))) & 0x0f)
167
168 /* Did the watchpoint whose address is in the I'th register break? */
169 #define X86_DR_WATCH_HIT(dr6, i) ((dr6) & (1 << (i)))
170
171 /* Types of operations supported by x86_handle_nonaligned_watchpoint. */
172 typedef enum { WP_INSERT, WP_REMOVE, WP_COUNT } x86_wp_op_t;
173
174 /* Print the values of the mirrored debug registers. */
175
176 static void
177 x86_show_dr (struct x86_debug_reg_state *state,
178 const char *func, CORE_ADDR addr,
179 int len, enum target_hw_bp_type type)
180 {
181 int i;
182
183 debug_printf ("%s", func);
184 if (addr || len)
185 debug_printf (" (addr=%s, len=%d, type=%s)",
186 phex (addr, 8), len,
187 type == hw_write ? "data-write"
188 : (type == hw_read ? "data-read"
189 : (type == hw_access ? "data-read/write"
190 : (type == hw_execute ? "instruction-execute"
191 /* FIXME: if/when I/O read/write
192 watchpoints are supported, add them
193 here. */
194 : "??unknown??"))));
195 debug_printf (":\n");
196
197 debug_printf ("\tCONTROL (DR7): 0x%s\n", phex (state->dr_control_mirror, 8));
198 debug_printf ("\tSTATUS (DR6): 0x%s\n", phex (state->dr_status_mirror, 8));
199
200 ALL_DEBUG_ADDRESS_REGISTERS (i)
201 {
202 debug_printf ("\tDR%d: addr=0x%s, ref.count=%d\n",
203 i, phex (state->dr_mirror[i],
204 x86_get_debug_register_length ()),
205 state->dr_ref_count[i]);
206 }
207 }
208
209 /* Return the value of a 4-bit field for DR7 suitable for watching a
210 region of LEN bytes for accesses of type TYPE. LEN is assumed to
211 have the value of 1, 2, or 4. */
212
213 static unsigned
214 x86_length_and_rw_bits (int len, enum target_hw_bp_type type)
215 {
216 unsigned rw;
217
218 switch (type)
219 {
220 case hw_execute:
221 rw = DR_RW_EXECUTE;
222 break;
223 case hw_write:
224 rw = DR_RW_WRITE;
225 break;
226 case hw_read:
227 internal_error (__FILE__, __LINE__,
228 _("The i386 doesn't support "
229 "data-read watchpoints.\n"));
230 case hw_access:
231 rw = DR_RW_READ;
232 break;
233 #if 0
234 /* Not yet supported. */
235 case hw_io_access:
236 rw = DR_RW_IORW;
237 break;
238 #endif
239 default:
240 internal_error (__FILE__, __LINE__, _("\
241 Invalid hardware breakpoint type %d in x86_length_and_rw_bits.\n"),
242 (int) type);
243 }
244
245 switch (len)
246 {
247 case 1:
248 return (DR_LEN_1 | rw);
249 case 2:
250 return (DR_LEN_2 | rw);
251 case 4:
252 return (DR_LEN_4 | rw);
253 case 8:
254 if (TARGET_HAS_DR_LEN_8)
255 return (DR_LEN_8 | rw);
256 /* ELSE FALL THROUGH */
257 default:
258 internal_error (__FILE__, __LINE__, _("\
259 Invalid hardware breakpoint length %d in x86_length_and_rw_bits.\n"), len);
260 }
261 }
262
263 /* Insert a watchpoint at address ADDR, which is assumed to be aligned
264 according to the length of the region to watch. LEN_RW_BITS is the
265 value of the bits from DR7 which describes the length and access
266 type of the region to be watched by this watchpoint. Return 0 on
267 success, -1 on failure. */
268
269 static int
270 x86_insert_aligned_watchpoint (struct x86_debug_reg_state *state,
271 CORE_ADDR addr, unsigned len_rw_bits)
272 {
273 int i;
274
275 if (!x86_dr_low_can_set_addr () || !x86_dr_low_can_set_control ())
276 return -1;
277
278 /* First, look for an occupied debug register with the same address
279 and the same RW and LEN definitions. If we find one, we can
280 reuse it for this watchpoint as well (and save a register). */
281 ALL_DEBUG_ADDRESS_REGISTERS (i)
282 {
283 if (!X86_DR_VACANT (state, i)
284 && state->dr_mirror[i] == addr
285 && X86_DR_GET_RW_LEN (state->dr_control_mirror, i) == len_rw_bits)
286 {
287 state->dr_ref_count[i]++;
288 return 0;
289 }
290 }
291
292 /* Next, look for a vacant debug register. */
293 ALL_DEBUG_ADDRESS_REGISTERS (i)
294 {
295 if (X86_DR_VACANT (state, i))
296 break;
297 }
298
299 /* No more debug registers! */
300 if (i >= DR_NADDR)
301 return -1;
302
303 /* Now set up the register I to watch our region. */
304
305 /* Record the info in our local mirrored array. */
306 state->dr_mirror[i] = addr;
307 state->dr_ref_count[i] = 1;
308 X86_DR_SET_RW_LEN (state, i, len_rw_bits);
309 /* Note: we only enable the watchpoint locally, i.e. in the current
310 task. Currently, no x86 target allows or supports global
311 watchpoints; however, if any target would want that in the
312 future, GDB should probably provide a command to control whether
313 to enable watchpoints globally or locally, and the code below
314 should use global or local enable and slow-down flags as
315 appropriate. */
316 X86_DR_LOCAL_ENABLE (state, i);
317 state->dr_control_mirror |= DR_LOCAL_SLOWDOWN;
318 state->dr_control_mirror &= X86_DR_CONTROL_MASK;
319
320 return 0;
321 }
322
323 /* Remove a watchpoint at address ADDR, which is assumed to be aligned
324 according to the length of the region to watch. LEN_RW_BITS is the
325 value of the bits from DR7 which describes the length and access
326 type of the region watched by this watchpoint. Return 0 on
327 success, -1 on failure. */
328
329 static int
330 x86_remove_aligned_watchpoint (struct x86_debug_reg_state *state,
331 CORE_ADDR addr, unsigned len_rw_bits)
332 {
333 int i, retval = -1;
334 int all_vacant = 1;
335
336 ALL_DEBUG_ADDRESS_REGISTERS (i)
337 {
338 if (!X86_DR_VACANT (state, i)
339 && state->dr_mirror[i] == addr
340 && X86_DR_GET_RW_LEN (state->dr_control_mirror, i) == len_rw_bits)
341 {
342 if (--state->dr_ref_count[i] == 0) /* No longer in use? */
343 {
344 /* Reset our mirror. */
345 state->dr_mirror[i] = 0;
346 X86_DR_DISABLE (state, i);
347 /* Even though not strictly necessary, clear out all
348 bits in DR_CONTROL related to this debug register.
349 Debug output is clearer when we don't have stale bits
350 in place. This also allows the assertion below. */
351 X86_DR_SET_RW_LEN (state, i, 0);
352 }
353 retval = 0;
354 }
355
356 if (!X86_DR_VACANT (state, i))
357 all_vacant = 0;
358 }
359
360 if (all_vacant)
361 {
362 /* Even though not strictly necessary, clear out all of
363 DR_CONTROL, so that when we have no debug registers in use,
364 we end up with DR_CONTROL == 0. The Linux support relies on
365 this for an optimization. Plus, it makes for clearer debug
366 output. */
367 state->dr_control_mirror &= ~DR_LOCAL_SLOWDOWN;
368
369 gdb_assert (state->dr_control_mirror == 0);
370 }
371 return retval;
372 }
373
374 /* Insert or remove a (possibly non-aligned) watchpoint, or count the
375 number of debug registers required to watch a region at address
376 ADDR whose length is LEN for accesses of type TYPE. Return 0 on
377 successful insertion or removal, a positive number when queried
378 about the number of registers, or -1 on failure. If WHAT is not a
379 valid value, bombs through internal_error. */
380
381 static int
382 x86_handle_nonaligned_watchpoint (struct x86_debug_reg_state *state,
383 x86_wp_op_t what, CORE_ADDR addr, int len,
384 enum target_hw_bp_type type)
385 {
386 int retval = 0;
387 int max_wp_len = TARGET_HAS_DR_LEN_8 ? 8 : 4;
388
389 static const int size_try_array[8][8] =
390 {
391 {1, 1, 1, 1, 1, 1, 1, 1}, /* Trying size one. */
392 {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size two. */
393 {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size three. */
394 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size four. */
395 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size five. */
396 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size six. */
397 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size seven. */
398 {8, 1, 2, 1, 4, 1, 2, 1}, /* Trying size eight. */
399 };
400
401 while (len > 0)
402 {
403 int align = addr % max_wp_len;
404 /* Four (eight on AMD64) is the maximum length a debug register
405 can watch. */
406 int attempt = (len > max_wp_len ? (max_wp_len - 1) : len - 1);
407 int size = size_try_array[attempt][align];
408
409 if (what == WP_COUNT)
410 {
411 /* size_try_array[] is defined such that each iteration
412 through the loop is guaranteed to produce an address and a
413 size that can be watched with a single debug register.
414 Thus, for counting the registers required to watch a
415 region, we simply need to increment the count on each
416 iteration. */
417 retval++;
418 }
419 else
420 {
421 unsigned len_rw = x86_length_and_rw_bits (size, type);
422
423 if (what == WP_INSERT)
424 retval = x86_insert_aligned_watchpoint (state, addr, len_rw);
425 else if (what == WP_REMOVE)
426 retval = x86_remove_aligned_watchpoint (state, addr, len_rw);
427 else
428 internal_error (__FILE__, __LINE__, _("\
429 Invalid value %d of operation in x86_handle_nonaligned_watchpoint.\n"),
430 (int) what);
431 if (retval)
432 break;
433 }
434
435 addr += size;
436 len -= size;
437 }
438
439 return retval;
440 }
441
442 /* Update the inferior debug registers state, in STATE, with the
443 new debug registers state, in NEW_STATE. */
444
445 static void
446 x86_update_inferior_debug_regs (struct x86_debug_reg_state *state,
447 struct x86_debug_reg_state *new_state)
448 {
449 int i;
450
451 ALL_DEBUG_ADDRESS_REGISTERS (i)
452 {
453 if (X86_DR_VACANT (new_state, i) != X86_DR_VACANT (state, i))
454 x86_dr_low_set_addr (new_state, i);
455 else
456 gdb_assert (new_state->dr_mirror[i] == state->dr_mirror[i]);
457 }
458
459 if (new_state->dr_control_mirror != state->dr_control_mirror)
460 x86_dr_low_set_control (new_state);
461
462 *state = *new_state;
463 }
464
465 /* Insert a watchpoint to watch a memory region which starts at
466 address ADDR and whose length is LEN bytes. Watch memory accesses
467 of the type TYPE. Return 0 on success, -1 on failure. */
468
469 int
470 x86_dr_insert_watchpoint (struct x86_debug_reg_state *state,
471 enum target_hw_bp_type type,
472 CORE_ADDR addr, int len)
473 {
474 int retval;
475 /* Work on a local copy of the debug registers, and on success,
476 commit the change back to the inferior. */
477 struct x86_debug_reg_state local_state = *state;
478
479 if (type == hw_read)
480 return 1; /* unsupported */
481
482 if (((len != 1 && len != 2 && len != 4)
483 && !(TARGET_HAS_DR_LEN_8 && len == 8))
484 || addr % len != 0)
485 {
486 retval = x86_handle_nonaligned_watchpoint (&local_state,
487 WP_INSERT,
488 addr, len, type);
489 }
490 else
491 {
492 unsigned len_rw = x86_length_and_rw_bits (len, type);
493
494 retval = x86_insert_aligned_watchpoint (&local_state,
495 addr, len_rw);
496 }
497
498 if (retval == 0)
499 x86_update_inferior_debug_regs (state, &local_state);
500
501 if (show_debug_regs)
502 x86_show_dr (state, "insert_watchpoint", addr, len, type);
503
504 return retval;
505 }
506
507 /* Remove a watchpoint that watched the memory region which starts at
508 address ADDR, whose length is LEN bytes, and for accesses of the
509 type TYPE. Return 0 on success, -1 on failure. */
510
511 int
512 x86_dr_remove_watchpoint (struct x86_debug_reg_state *state,
513 enum target_hw_bp_type type,
514 CORE_ADDR addr, int len)
515 {
516 int retval;
517 /* Work on a local copy of the debug registers, and on success,
518 commit the change back to the inferior. */
519 struct x86_debug_reg_state local_state = *state;
520
521 if (((len != 1 && len != 2 && len != 4)
522 && !(TARGET_HAS_DR_LEN_8 && len == 8))
523 || addr % len != 0)
524 {
525 retval = x86_handle_nonaligned_watchpoint (&local_state,
526 WP_REMOVE,
527 addr, len, type);
528 }
529 else
530 {
531 unsigned len_rw = x86_length_and_rw_bits (len, type);
532
533 retval = x86_remove_aligned_watchpoint (&local_state,
534 addr, len_rw);
535 }
536
537 if (retval == 0)
538 x86_update_inferior_debug_regs (state, &local_state);
539
540 if (show_debug_regs)
541 x86_show_dr (state, "remove_watchpoint", addr, len, type);
542
543 return retval;
544 }
545
546 /* Return non-zero if we can watch a memory region that starts at
547 address ADDR and whose length is LEN bytes. */
548
549 int
550 x86_dr_region_ok_for_watchpoint (struct x86_debug_reg_state *state,
551 CORE_ADDR addr, int len)
552 {
553 int nregs;
554
555 /* Compute how many aligned watchpoints we would need to cover this
556 region. */
557 nregs = x86_handle_nonaligned_watchpoint (state, WP_COUNT,
558 addr, len, hw_write);
559 return nregs <= DR_NADDR ? 1 : 0;
560 }
561
562 /* If the inferior has some break/watchpoint that triggered, set the
563 address associated with that break/watchpoint and return non-zero.
564 Otherwise, return zero. */
565
566 int
567 x86_dr_stopped_data_address (struct x86_debug_reg_state *state,
568 CORE_ADDR *addr_p)
569 {
570 CORE_ADDR addr = 0;
571 int i;
572 int rc = 0;
573 /* The current thread's DR_STATUS. We always need to read this to
574 check whether some watchpoint caused the trap. */
575 unsigned status;
576 /* We need DR_CONTROL as well, but only iff DR_STATUS indicates a
577 data breakpoint trap. Only fetch it when necessary, to avoid an
578 unnecessary extra syscall when no watchpoint triggered. */
579 int control_p = 0;
580 unsigned control = 0;
581
582 /* In non-stop/async, threads can be running while we change the
583 global dr_mirror (and friends). Say, we set a watchpoint, and
584 let threads resume. Now, say you delete the watchpoint, or
585 add/remove watchpoints such that dr_mirror changes while threads
586 are running. On targets that support non-stop,
587 inserting/deleting watchpoints updates the global dr_mirror only.
588 It does not update the real thread's debug registers; that's only
589 done prior to resume. Instead, if threads are running when the
590 mirror changes, a temporary and transparent stop on all threads
591 is forced so they can get their copy of the debug registers
592 updated on re-resume. Now, say, a thread hit a watchpoint before
593 having been updated with the new dr_mirror contents, and we
594 haven't yet handled the corresponding SIGTRAP. If we trusted
595 dr_mirror below, we'd mistake the real trapped address (from the
596 last time we had updated debug registers in the thread) with
597 whatever was currently in dr_mirror. So to fix this, dr_mirror
598 always represents intention, what we _want_ threads to have in
599 debug registers. To get at the address and cause of the trap, we
600 need to read the state the thread still has in its debug
601 registers.
602
603 In sum, always get the current debug register values the current
604 thread has, instead of trusting the global mirror. If the thread
605 was running when we last changed watchpoints, the mirror no
606 longer represents what was set in this thread's debug
607 registers. */
608 status = x86_dr_low_get_status ();
609
610 ALL_DEBUG_ADDRESS_REGISTERS (i)
611 {
612 if (!X86_DR_WATCH_HIT (status, i))
613 continue;
614
615 if (!control_p)
616 {
617 control = x86_dr_low_get_control ();
618 control_p = 1;
619 }
620
621 /* This second condition makes sure DRi is set up for a data
622 watchpoint, not a hardware breakpoint. The reason is that
623 GDB doesn't call the target_stopped_data_address method
624 except for data watchpoints. In other words, I'm being
625 paranoiac. */
626 if (X86_DR_GET_RW_LEN (control, i) != 0)
627 {
628 addr = x86_dr_low_get_addr (i);
629 rc = 1;
630 if (show_debug_regs)
631 x86_show_dr (state, "watchpoint_hit", addr, -1, hw_write);
632 }
633 }
634
635 if (show_debug_regs && addr == 0)
636 x86_show_dr (state, "stopped_data_addr", 0, 0, hw_write);
637
638 if (rc)
639 *addr_p = addr;
640 return rc;
641 }
642
643 /* Return non-zero if the inferior has some watchpoint that triggered.
644 Otherwise return zero. */
645
646 int
647 x86_dr_stopped_by_watchpoint (struct x86_debug_reg_state *state)
648 {
649 CORE_ADDR addr = 0;
650 return x86_dr_stopped_data_address (state, &addr);
651 }
x86_update_inferior_debug_regs
static void x86_update_inferior_debug_regs(struct x86_debug_reg_state *state, struct x86_debug_reg_state *new_state)
Definition: x86-dregs.c:446
X86_DR_WATCH_HIT
#define X86_DR_WATCH_HIT(dr6, i)
Definition: x86-dregs.c:169
x86_dr_low_get_status
#define x86_dr_low_get_status()
Definition: x86-dregs.c:58
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#define x86_dr_low_set_control(new_state)
Definition: x86-dregs.c:51
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#define DR_RW_EXECUTE
Definition: x86-dregs.c:75
DR_RW_WRITE
#define DR_RW_WRITE
Definition: x86-dregs.c:76
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#define DR_RW_READ
Definition: x86-dregs.c:77
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bfd_vma CORE_ADDR
Definition: common-types.h:41
DR_LEN_8
#define DR_LEN_8
Definition: x86-dregs.c:91
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unsigned dr_control_mirror
Definition: x86-dregs.h:85
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#define DR_LOCAL_SLOWDOWN
Definition: x86-dregs.c:113
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Definition: print-utils.c:151
TARGET_HAS_DR_LEN_8
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Definition: x86-dregs.c:65
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Definition: errors.c:50
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#define x86_dr_low_get_control()
Definition: x86-dregs.c:55
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#define X86_DR_DISABLE(state, i)
Definition: x86-dregs.c:148
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static void x86_show_dr(struct x86_debug_reg_state *state, const char *func, CORE_ADDR addr, int len, enum target_hw_bp_type type)
Definition: x86-dregs.c:177
hw_execute
Definition: break-common.h:27
x86_dr_remove_watchpoint
int x86_dr_remove_watchpoint(struct x86_debug_reg_state *state, enum target_hw_bp_type type, CORE_ADDR addr, int len)
Definition: x86-dregs.c:512
_
#define _(String)
Definition: gdb_locale.h:35
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int x86_dr_stopped_data_address(struct x86_debug_reg_state *state, CORE_ADDR *addr_p)
Definition: x86-dregs.c:567
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#define x86_dr_low_can_set_addr()
Definition: x86-dregs.c:38
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static int x86_handle_nonaligned_watchpoint(struct x86_debug_reg_state *state, x86_wp_op_t what, CORE_ADDR addr, int len, enum target_hw_bp_type type)
Definition: x86-dregs.c:382
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#define X86_DR_CONTROL_MASK
Definition: x86-dregs.c:126
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Definition: x86-dregs.c:172
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Definition: break-common.h:24
DR_LEN_4
#define DR_LEN_4
Definition: x86-dregs.c:90
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int x86_dr_insert_watchpoint(struct x86_debug_reg_state *state, enum target_hw_bp_type type, CORE_ADDR addr, int len)
Definition: x86-dregs.c:470
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int x86_dr_region_ok_for_watchpoint(struct x86_debug_reg_state *state, CORE_ADDR addr, int len)
Definition: x86-dregs.c:550
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#define DR_LEN_2
Definition: x86-dregs.c:89
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Definition: x86-dregs.h:84
WP_REMOVE
Definition: x86-dregs.c:172
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int show_debug_regs
Definition: common-debug.c:25
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#define x86_dr_low_get_addr(i)
Definition: x86-dregs.c:45
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Definition: break-common.h:25
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#define x86_dr_low_can_set_control()
Definition: x86-dregs.c:48
break-common.h
common-defs.h
x86_dr_stopped_by_watchpoint
int x86_dr_stopped_by_watchpoint(struct x86_debug_reg_state *state)
Definition: x86-dregs.c:647
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Definition: x86-dregs.c:172
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#define gdb_assert(expr)
Definition: gdb_assert.h:32
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#define x86_dr_low_set_addr(new_state, i)
Definition: x86-dregs.c:41
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#define DR_LEN_1
Definition: x86-dregs.c:88
X86_DR_SET_RW_LEN
#define X86_DR_SET_RW_LEN(state, i, rwlen)
Definition: x86-dregs.c:155
WP_INSERT
Definition: x86-dregs.c:172
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int dr_ref_count[DR_NADDR]
Definition: x86-dregs.h:88
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#define DR_NADDR
Definition: x86-dregs.h:71
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#define ALL_DEBUG_ADDRESS_REGISTERS(i)
Definition: x86-dregs.h:92
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static int x86_remove_aligned_watchpoint(struct x86_debug_reg_state *state, CORE_ADDR addr, unsigned len_rw_bits)
Definition: x86-dregs.c:330
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static unsigned x86_length_and_rw_bits(int len, enum target_hw_bp_type type)
Definition: x86-dregs.c:214
target_hw_bp_type
target_hw_bp_type
Definition: break-common.h:22
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#define X86_DR_GET_RW_LEN(dr7, i)
Definition: x86-dregs.c:164
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Definition: x86-dregs.h:77
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unsigned dr_status_mirror
Definition: x86-dregs.h:85
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#define DR_RW_IORW
Definition: x86-dregs.c:83
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Definition: break-common.h:26
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void debug_printf(const char *fmt,...)
Definition: common-debug.c:30
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#define x86_get_debug_register_length()
Definition: x86-dregs.c:61
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static int x86_insert_aligned_watchpoint(struct x86_debug_reg_state *state, CORE_ADDR addr, unsigned len_rw_bits)
Definition: x86-dregs.c:270
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#define X86_DR_LOCAL_ENABLE(state, i)
Definition: x86-dregs.c:134
X86_DR_VACANT
#define X86_DR_VACANT(state, i)
Definition: x86-dregs.c:130