#ifndef _ARM2X86_SHIFT_H_
#define _ARM2X86_SHIFT_H_

extern op_table_t	op_shift_T1_im[4];	//only shift
extern op_table_t	op_shift_T1_im_sc[4];	//only set CFlag
extern op_table_t	op_shift_T1_T0[4];	//only shift
extern op_table_t	op_shift_T1_T0_sc[4];	//shift & set CFlag
extern op_table_t	op_shift_T2_im[4];	//only shift

extern int		arm2x86_shift_init();

static __inline__ void
gen_op_shift_T1_im(ARMul_State *state, uint8_t **tbpp, int *plen, ARMword op, uint8_t im)
{
	if (im == 0)
		return;
	GEN_OP(*tbpp, *plen, op_shift_T1_im[op]);
	if (*tbpp) {
		memcpy(*tbpp, &im, sizeof(im));
		*tbpp += sizeof(im);
	}
	*plen += sizeof(im);
}

static __inline__ void
gen_op_shift_T1_im_sc(ARMul_State *state, uint8_t **tbpp, int *plen, ARMword op, uint8_t im)
{
	if (im == 0)
		return;
	if (*tbpp) {
		memcpy(*tbpp, op_shift_T1_im_sc[op].op, op_shift_T1_im_sc[op].len);
		if (!op) {
			(*tbpp)[4] = 32 - im;
		}
		else {
			(*tbpp)[4] = im - 1;
		}
		*tbpp += op_shift_T1_im_sc[op].len;
	}
	*plen += op_shift_T1_im_sc[op].len;

	//set cpsr cf
	GEN_OP(*tbpp, *plen, op_set_cf);
}

static __inline__ void
gen_op_shift_T1_T0(ARMul_State *state, uint8_t **tbpp, int *plen, ARMword op)
{
	GEN_OP(*tbpp, *plen, op_shift_T1_T0[op]);
}

static __inline__ void
gen_op_shift_T1_T0_sc(ARMul_State *state, uint8_t **tbpp, int *plen, ARMword op)
{
	GEN_OP(*tbpp, *plen, op_shift_T1_T0_sc[op]);

	//set cpsr cf
	GEN_OP(*tbpp, *plen, op_set_cf);
}

static __inline__ void
gen_op_shift_T2_im(ARMul_State *state, uint8_t **tbpp, int *plen, ARMword op, uint8_t im)
{
	if (im == 0)
		return;
	GEN_OP(*tbpp, *plen, op_shift_T2_im[op]);
	if (*tbpp) {
		memcpy(*tbpp, &im, sizeof(im));
		*tbpp += sizeof(im);
	}
	*plen += sizeof(im);
}
#endif	//_ARM2X86_SHIFT_H_
