/*
 *	DEC registers and such stuff
 *	Copyright (C) 1995 Michael Poole
 *
 *	This program is free software; you can redistribute it and/or modify
 *	it under the terms of the GNU General Public License as published by
 *	the Free Software Foundation; either version 2 of the License, or
 *	(at your option) any later version.
 *
 *	This program is distributed in the hope that it will be useful,
 *	but WITHOUT ANY WARRANTY; without even the implied warranty of
 *	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *	GNU General Public License for more details.
 *
 *	You should have received a copy of the GNU General Public License
 *	along with this program; if not, write to the Free Software
 *	Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

/* Register numbering is somewhat complicated as there are naming conventions
   introduced by assembler, C compiler, transputer code, etc, etc that
   need to be reflected to produce code that is both optimal and readable */

/* first we name the DEC alpha integer registers as DEC do for their
   assembler */

#define v0       0
#define t0       1
#define t1       2
#define t2       3
#define t3       4
#define t4       5
#define t5       6
#define t6       7
#define t7       8
#define s0        9
#define s1       10
#define s2       11
#define s3       12
#define s4       13
#define s5       14
#define s6       15
#define fp       15
#define a0       16
#define a1       17
#define a2       18
#define a3       19
#define a4       20
#define a5       21
#define t8       22
#define t9       23
#define t10      24
#define t11      25
#define ra       26
#define t12      27
#define at       28
#define gp       29
#define sp       30
#define zero     31
/* these are some of the conventions which appear to be obeyed:
(e.g in code compiled from C)
v0      is used for function results
a0..a5  are used for function arguments
t8..t11 are used for temporaries in in-line division and such like
gp      is ???
sp      is ???
fp      is ???
*/

#define REG_0    t0
#define REG_1    t1
#define REG_2    t2
#define REGW     s4
#define REGZERO  zero
#define MIN      s0
#define REGKLINK    s5
#define REGRETURN   ra
#define REGSCRATCH  at
#define REGKBASE    fp
#define REG_UNDEF (-1)

#define FREGSCRATCH 30
#define FREGZERO 31
#define FREG_UNDEF (-1)
#define FREG_0     0
#define FREG_1     1
#define FREG_2     2
#define FREG_two     5
#define FREG_half    4
#define FREG_two32   6
#define FREG_twom32  7
#define FREG_twom23  8
#define FREG_two52   9

#define WSH      2 /* shift to make byte address from wspace unit size */

/* In code compiled from occam these further conventions apply:
The transputer integer stack RegA,RegB,RegC is emulated by REG_2,REG_1,REG_0.
The compiler maintains a variable ts_depth which holds the number of
emulated transputer stack registers holding meaningful values.
If ts_depth = 1 then RegA = REG_0
If ts_depth = 2 then RegA = REG_1, RegB = REG_0
If ts_depth = 3 then RegA = REG_2, RegB = REG_1, RegC = REG_0
Note that the mapping from lettered registers to numbered ones
is not constant.

When a call is made to a kernel routine the emulated transputer stack
must be mapped onto known constant registers. This only gives problems
when there may be values in the transputer stack which are not used by
the kernel routine and which must survive the call to it.

When necesary, register shuffling operations are generated in the compiled
code to ensure that the kernel routines can operate on known registers.
*/
/*{{{  fpu modes*/
#define FPU_NONE -1
#define FPU_N     0
#define FPU_P     1
#define FPU_M     3
#define FPU_Z     2
/*}}}  */
#define MININT16 0x8000
#define BYTEMASK 0xFF
#define WORDMASK 0xFFFF

/* #define GEN_NOTALPHA 40   -- moved to generror.h */
/* needs revision of error text also */
/*{{{  kernel entries and kernel-defined constants*/
/* code segment address of kernel jump table */
#define K_IN        1
#define K_OUT       2
#define K_OUTWORD   3
#define K_OUTBYTE   4
#define K_RUNP      5
#define K_STARTP    6
#define K_ENDP      7
#define K_STOPP     8
#define K_PAUSE     9
#define K_LDTIMER   10
#define K_TIN       11
#define K_ALTWT     12
#define K_TALTWT    13
#define K_ENBC      14
#define K_ENBT      15
#define K_DISS      16
#define K_DISC      17
#define K_DIST      18
#define K_RANGERR   19
#define K_SETERR    20
#define K_NORM      21
#define K_UNPACKSN  22
#define K_POSTNORMSN 23
#define K_ROUNDSN   24
#define K_MOVE      25
#define K_DIV       26
#define K_REM       27
#define K_LDIV      28

#define W_TIME     (-5<<WSH)
#define W_TLINK    (-4<<WSH)
#define W_STATUS   (-3<<WSH)
#define W_LINK     (-2<<WSH)
#define W_IPTR     (-1<<WSH)

#define NOT_PROCESS MOSTNEG_INT32
#define Z_ENABLING  NOT_PROCESS + 1
#define Z_WAITING   NOT_PROCESS + 2
#define Z_READY     NOT_PROCESS + 3
#define Z_TIMESET    NOT_PROCESS + 1
#define Z_TIMENOTSET NOT_PROCESS + 2
/*}}}  */
/*{{{  DEC alpha instruction opcodes, etc*/
#define IA_LDA     0x08
#define IA_LDAH    0x09
#define IA_LDQ_U   0x0B
#define IA_STQ_U   0x0F
#define IA_LDS     0x22
#define IA_LDT     0x23
#define IA_STS     0x26
#define IA_STT     0x27
#define IA_LDL     0x28
#define IA_LDQ     0x29
#define IA_STL     0x2C
#define IA_STQ     0x2D
#define IA_JMP     0x1A
#define IA_BR      0x30
#define IA_BSR     0x34
#define IA_BEQ     0x39
#define IA_BLT     0x3A
#define IA_BNE     0x3D
#define IA_BGE     0x3E
#define IA_BGT     0x3F
#define IAO_ADDL   0x1000
#define IAO_ADDQ   0x1020
#define IAO_ADDLV  0x1040
#define IAO_ADDQV  0x1060
#define IAO_SUBL   0x1009
#define IAO_SUBQ   0x1029
#define IAO_SUBLV  0x1049
#define IAO_SUBQV  0x1069
#define IAO_S4ADDL 0x1002
#define IAO_S8ADDL 0x1012
#define IAO_CMPULE 0x103D
#define IAO_CMPLE  0x106D
#define IAO_AND    0x1100
#define IAO_BIC    0x1108
#define IAO_BIS    0x1120
#define IAO_ORNOT  0x1128
#define IAO_XOR    0x1140
#define IAO_EQV    0x1148
#define IAO_CMOVEQ 0x1124
#define IAO_CMOVNE 0x1126
#define IAO_EXTBL  0x1206
#define IAO_INSBL  0x120B
#define IAO_MSKBL  0x1202
#define IAO_MSKLL  0x1222
#define IAO_ZAP    0x1230
#define IAO_ZAPNOT 0x1231
#define IAO_SLL    0x1239
#define IAO_SRL    0x1234
#define IAO_SRA    0x123C
#define IAO_MULL   0x1300
#define IAO_MULQ   0x1320
#define IAO_MULLV  0x1340
#define IAO_MULQV  0x1360
#define IAO_CMPEQ  0x102D
#define IAO_CMPLT  0x104D
#define IAF_ADDS   0x16080
#define IAF_ADDT   0x160A0
#define IAF_SUBS   0x16081
#define IAF_SUBT   0x160A1
#define IAF_MULS   0x16082
#define IAF_MULT   0x160A2
#define IAF_DIVS   0x16083
#define IAF_DIVT   0x160A3
#define IAF_CVTTQ  0x160AF
#define IAF_CVTTQC 0x1602F
#define IAF_CVTQS  0x160BC
#define IAF_CVTQT  0x160BE
#define IAF_CVTTS  0x160AC
#define IAF_CMPTUN 0x160A4
#define IAF_CMPTEQ 0x160A5
#define IAF_CMPTLT 0x160A6
#define IAF_CMPTLE 0x160A7
#define IAF_CPYS   0x17020
#define IAF_MT_FPCR   0x17024
#define IAF_MF_FPCR   0x17025
#define IA_TRAPB   0x18
/*}}}  */

